LAB REPORT

➢ Open the Download_lab_data and select

tessent_atpg_data_v2020.1_20200611.tgz file and save it.
➢ Move the file from Downloads to Home directory using command
mv ./Downloads/tessent_atpg_data_v2020.1_20200611.tgz .
➢ Extract the files from compressed tar file using command
Tar xzvf ./tessent_atpg_data_v2020.1_20200611.tgz
Exercise 1
➢ Select the directory as atpg_data/Lab2/Exercise1 using command
cd $atpg_data/Lab2/Exercise1
➢ Invoke Tessent shell to perform scan insertion
tessent -shell
➢ It enters into setup mode (which is default system mode) where we setup circuit, scan
and tool behavior using command
 set context dft -scan
➢ Read the Verilog netlist and cell library files by giving respective commands.
➢ Now, set the current design using command
set_current_design
It will set the current design to the top.
Note: By defining control signals, we set up pin to constant values by command
add_pin_constraints <pin_name> [c0|c1]
c0 means set to constant value 0 and c1 means set to constant value 1.
➢ analyze_control_signals gives the details of cell instances,gates,PIs and POs.

➢ check_design_rules runs DRC and gives the S- violations

It identifies the number of flipflops to be converted to scan flops and runs scan rules checking for
them.
Here, we have noticed ‘34’ S1 violations
➢ Command analyze_drc_violation s1-1 gives the violations at the specific pins
such as clocks, resets, sets as shown in figure opened in flat schematic.

➢ These violations can be set by setting to their off state values using commands. The
command below is used to off the reset pin
add_clocks 1 rstn
and run DRCs again and it will show remaining violations (Here 17 s1 remaining).
➢ Run command again analyze_drc_violation s1-1
➢ Command add_clocks 0 clk1 will set the clock to off state value and run DRC again
to see any violations left.
If no violations, then it will enter into ANALYSIS mode.

➢ In ANALYSIS mode, Command report_scan_cells will give the number of identified

scannable cells. In this example it is 17 scan cells.
 ➢ Command set_scan_insertion_options \-port_index_start_value 1 -
single_clock_edge_chains on
This will turn on the scan chains with single clock edge ( it may be either pos edge or neg edge
clock ).
➢ Command set_scan_insertion_options \-module_uniquification_suffix _scan#

Here, we indicate to use separate scan chains for different clock edges.
➢ Command add_scan_mode unwrapped -chain count 1
This will create scan chain in unwrapped mode with a chain count of 1.
➢ Command analyze_scan_chains distributes scan elements into new scan chains.
scan elements identified as non-scannable are not considered for distribution.
Here, it will create 1 distributed scan chain of size 17 in unwrapped mode.
➢ Command insert_test_logic inserts the test structures you define into the netlist and
stitches up the scan chains to increase the design’s testability.
The tool inserts test structures into a design to increase the fault coverage (testability) of the
design by doing following.
• Identifies sequential cells and replaces them with corresponding scan cells, and
stitches them together into a scan chain. (ie, scan cell replacement and stitching.)
• Supports the adding of both system-defined and user-defined test points.
• Supports the automatic adding of test logic.
Here, insert_test_logic gives structural and logical data.
Structural data gives the data of top-level port count and instance count and
Logical data gives the data of retiming logic count and scan chain count.

➢ Command report_test_logic is used in insertion mode displays the test logic that the
tool added during the scan insertion process and also displays information about the
additional library cells instantiated in the design during the scan insertion process.
Here, it gives info of the new pins created , new instance and modules created.
➢ Command report_scan_chains displays report on all the current scan chains.
The report shows the following information for each scan chain:
• Name of the scan chain • Name of the scan chain group • Scan chain input and output
pins • Length of the scan chain • Name of the scan clock(s) (but only after you enable the
E8 DRC in setup mode).
➢ Command report_scan_cells displays a report on the scan cells within the specified
scan chains.
➢ The report provides the following information for each scan cell:
• Chain cell index number (cell ID), where 0 is the scan cell closest to the scan-out
pin.
• Scan chain in which the scan cell resides.
• Scan group in which the scan cell resides. (The scan group data is hidden if the
design has only scan group.)
• Sequential element type, primitive type, and latch triggering type during shifting.
The latch triggering type can be one of the following: LE, TE, AH, AL.
• Inversion data for each sequential element.
• Gate index number for each sequential element.
 • Shift clock name and inversion status at the clock input of each sequential element.
(“dft -edt” and “patterns -scan” only)
• Top-level library model cell name of each sequential element.
• Instance name of each sequential element

➢ Command write_design -output_file results/ex1_scan.v \-replace

This command writes the current design in Verilog netlist format to the specified file.
➢ Command write_atpg_setup results/ex1_scan.v \-replace
This command writes a test procedure file and a dofile that describes the chains that were
created during scan insertion and also for multi-mode scan insertion, the tool also generates
a dofile that can be used to verify all of the defined scan modes.
The dofile and test procedure file are used with FastScan to do the design setup before
creating test patterns.

If you want to verify the scan insertion that just happened you can set the system mode to
setup and run verification dofile execute following commands:
➢ Command set_system_mode_setup used in insertion mode and it will enter setup mode.
➢ Command dofile results/ex1_scan_verify_scan_modes.dofile
➢ Command exit -d
Exercise 2
➢ Same procedure is followed in exercise2 as in exercise1 in the setup mode.
➢ In the analysis mode, here we create two scan chains and their input and output pin
connections.
➢ Command set_scan_insertion_options\-port_index_start_value 1 -
si_timing any_edge \-so_timing any_edge -single_clock_edge_chains
on \-single_clock_domain_chains on
This command will on single clock edge chains and single clock domain chains.
Single clock domain chains ON means single clock is used drive single or one scan chain,
another clock is used to drive another scan chain.
➢ Command set_insertion_options \-module_uniquification_suffix -scan#

➢ Adding mode and number of scan chains using commands

add_scan_mode unwrapped -chain_count 2 \-si_connections {{/d[10]} {/d[0]}} \-

so_connections {{/q[10]} {/q[0]}}
Creates two scan chains in unwrapped mode with si and so connections specified for two
chains.
➢ Command analyze_scan_chains gives the info about scan chains. Here two chains
are formed one chain is of size 2 (which is the minimum size) and other chain size is
15 (which is the maximum size).
➢ After defining the scan chains next step is to insert them in the design using
Command insert_test_logic creates scan inserted netlist and enters into INSERTION
mode.
➢ Here, it gives top level port count as 0, instance count is 6, added scan chain count is
2.
➢ Command report_test_logic gives the data of instances added.
➢ Command report_scan_cells displays all the scan cells of chain1 and chain 2 and the
group name , clock to which it is driven, cell name and polarity of clock.

➢ Command report_scan_chains displays scan chain information

Here, chain1 has input /d[10] ,output /q[15] and length =15
Chain2 has input /d[0] ,output /q[0] and length =2
➢ Command report_scan_cells all the scan cells information to which group it belongs
to, clock it is driven and its polarity, its pathname and its cell number.
As clock2 is driving only two scan cells and single clock domain chains was set on
restricts it to single clock domain.
 ➢ Command write_design -output_file results/ex2_scan.v \-replace

➢ Command write_atpg_setup results/ex2_scan.v \-replace

By using above two commands following files get created:
ex2_scan.v -verilog netlist
ex2_scan.dofile -dofile
ex2_scan.testproc -test procedure file
ex2_scan_verify_scan_modes.dofile -verification dofile
We have created a scan inserted netlist and next is to generate patterns that are used with
netlist.
Exercise 3
Balancing scan chains and multiple clock domains
➢ To avoid skew issues during shift, a lock up latch needs to be inserted between the
scan cells where clock domains cross.

ATPG library does not have predefined cell to use as lock up latch.
So, identify latch and inverter from atpg cell library for use as test structures.
➢ Command add_cell_models latch -type dlat CLK D
➢ Command add_cell_models inv01 -type inv
➢ Command set_test_logic -reset on
➢ Command set_scan_insertion_options \-port_index_start_value 1 -
si_timing any_edge \-so_timing any_edge -single_clock_edge_chains
on \-single_clock_domain_chains off
This command makes a single clock can be used to drive multiple chains.
➢ add_scan_mode unwrapped -chain_count 2 \-si_connections {{/d[10]} {/d[0]}} \-
so_connections {{/q[15]} {/q[1]}}
➢ This command will create two balanced scan chains in which 17 flops divided into 9
and 8 flops in chain1 and chain2 respectively in unwrapped mode.
➢ Command report_scan_chains will display following:
chain1 has input =/d[10] ,output= /q[15] and length =9
chain2 has input =/d[0] ,output= /q[1] and length =8

➢ Command report_test_logic gives details of new pins added, instances and modules
added.
➢ Save scan inserted netlist and ATPG setup file.