Scan Compression &

Compression Techniques
 Necessity of Scan Compression
• Scan compression has become a necessity for meeting test cost and
quality requirements of today’s nanometer designs.
• When considering a scan compression technology, several key factors
should be considered in order to ensure that the compression
technology does not take anything away from the existing high quality,
low cost test.
Some of the key areas are:
- Impact on test quality (test coverage)
- Data and time compression (tolerance to X sources)
- Low pin count testing (to enable multi-site testing)
- Area and layout overhead
- Diagnostics and impact on manufacturing flow
 Why Compression
• Semiconductor companies realized a need for compression because of rising
tester costs.
• The test pattern data volume exceeded the tester memory, requiring pattern
reloads and excessive test application time.
• Over time, that need has been supplemented with the necessity to improve
test quality.
• New fault models and additional test patterns are needed to detect new types
of defects and meet the quality levels of nanometer designs.
• The undesirable option of pattern truncation results in lower test coverage and
ultimately an increase in defective parts per million (DPPM) that are shipped to
customers.
• Therefore, in order to avoid an increase in test escapes due to low test quality,
the industry has recognized an inevitable need for test pattern compression.
Uncompressed Scan Vs Compressed Scan
 Goals of Scan Compression
➢ Given that the goals of scan pattern compression are to lower tester costs and
maintain high test quality, we need to identify the specific requirements for an
effective compression technique.
• Test Cost
• Reduce the requirement of scan data memory
• Reduce test application time per part
• Reduce the number of required scan channels
• Reduce simulation time for serial load patterns
• Test Quality
• Ability to support and compress all pattern types to fit within tester memory
• Ability to support and compress patterns for several different fault models
• Ability to maintain high at-speed test coverage in the presence of many X sources
• Diagnostics of compressed scan patterns
 Scan Compression Techniques
• The key requirement of any compression technology is preservation
of high test quality when compared to standard (uncompressed)
patterns.
• Several technologies have been developed over the years in order to
meet the compression goals outlined in the previous section (Test
Cost & Test Quality)

Scan Compression Techniques:

1. Virtual Scan ---> SynTest Technologies
2. Adaptive Scan ---> Synopsys
3. On-Product Multiple Input Signature Register (OP-MISR) ---> Cadence
4. Embedded Deterministic Test (EDT) ---> Mentor Graphics
 Embedded Deterministic Test (EDT)
• EDT was developed primarily to reduce the testing time and test data
volume on large multimillion gate designs that need testing for
several fault models.
• Mentor Graphics TestKompress (TK) is the tool that can generate the
decompressor and compactor logic at the RTL level.
• The architecture consists of a decompressor and a compactor
logic embedded on the chip.
• The decompressor drives the scan chain inputs and the
compactor connects from the scan chain outputs.
• The EDT logic is inserted only in the scan path.
• In the presence of EDT logic we can have a large number of
very short scan chains.
EDT Architecture
EDT Architecture
 EDT Architecture - Decompressor
• The decompressor consists of a ring generator
• The outputs of the ring generator flops will connect to scan chain
inputs through a phase shifter consisting of XOR gates.
• Creation of the compressed stimuli from a test pattern consists of
solving a set of linear equations based on the ring generator
polynomial and the phase shifter connections.
• Inputs to the ring generator are driven from the compressed stimuli
on the ATE.
The input side is called a continuous-flow ring generator (Figure 3). It
is similar to a linear feedback shift register (LFSR) in that it can
produce random data, but the device is used to decode compressed
data with every shift of scan channel values
EDT Architecture - Decompressor
 EDT Architecture - Compressor
• The output response compactor consists of an XOR tree and the masking
logic
• The masking logic consists of a pattern mask register, decoder, and AND
gates before the XOR tree.
• The logic values for the pattern mask register are loaded from the
compressed pattern data on the ATE.
• The masking logic and the XOR tree compactor have the ability to handle
any number of unknowns (Xs) from the scan chains without any
modifications to the functional logic.
• The masking logic will also eliminate the effects of fault aliasing through
the XOR tree.
• The decompressor/compactor logic implemented in TestKompress can also
perform fault diagnosis using the same compressed patterns that is used
on the ATE.
EDT Architecture - Compressor
 Advantages of EDT Architecture
➢ Best encoding capacity.
➢A single scan channel can be used to obtain time and data compressions of more
than 100x.
➢No routing congestion, as there are no high fan-out nets. Modular
implementation can be used for easy block-level implementation.
➢ All faults that propagate to scan cells are guaranteed to be detected by the
automated masking capability of the compactor, even in the presence of any
number of Xs and fault aliasing.
➢No need to generate any top-up ATPG patterns as the test coverage in the
compressed and bypass mode are the same.
➢ Compressed patterns can be directly diagnosed for failures found on the tester,
and there is no loss of diagnostic resolution compared with bypass mode
patterns.
Limitations of EDT
The ring generator, phase shifter, XOR tree compactor and the x-masking logic
contributes to an area overhead of up to 1% generally.
 Scan Compression Ratio
• Designs require on-chip test hardware to compress the time and
memory of automatic test pattern generation (ATPG) tests to
manageable budgets.
• This on-chip test hardware is generally referred to as scan
compression or simply compression.
• The ratio of the number of scan channels to the external FULLSCAN
chains is the target compression ratio.
• When the scan chains are properly balanced, you can reduce test
time and test data volume close to the target ratio.
• In many designs, using the right architecture, DFT engineers can
expect to achieve 200X compression efficiency or more, translating
into equivalent test time and data volume savings.
 Hierarchical Compression
• When designs are very large and contain multiple IP blocks, hierarchical
physical synthesis and implementation is the preferred approach.
• In this case, it would be quite difficult, and in some situations impossible to
implement a single compression logic for the design.
• Power, timing, routing, and area considerations would have a much bigger
impact on DFT. A hierarchical approach to compression is also desired.
• In hierarchical compression architecture, multiple levels of compression are
implemented.
• The lowest-level blocks would have scan channels, with compression logic
placed around them. Many compressed blocks are then further compressed
at the next level until the chip-level I/Os are accessible.
• With this approach, test budget goals and physical parameters can be met at
each of the compressed blocks, reducing the overall impact at the chip level.
 Hierarchical Compression
• Hierarchical compression is suitable for large designs that use hierarchical methodologies.
• The choice of pattern generation would depend upon the rest of the DFT architecture, including
IEEE 1500 usage and test partitioning plans.
Thank You!