DFT basics

DFT stands for Design for Testification. DFT engineers try to make the
testing of design more cost effective by introducing some structures into
the design itself. By doing so, the overall test cost, and hence, cost of
production comes down.
Design for testability (DFT) makes it possible to: • Assure the detection of
all faults in a circuit. • Reduce the cost and time associated with test
development. • Reduce the execution time of performing test on fabricated
chips.
We will focus on DFT techniques for digital logic, although it is relevant
for memory and Analog/mixed-signal components as well. An example
chip level DFT technique is called Built-in self-test (BIST)
The DFT techniques discussed focus on improving testability of SAFs.
DFT for other fault models, e.g., delay faults, is described in the literature.

Two forms of DFT: ad-hoc and structured.

Ad-hoc DFT relies on "good" design practices: • Avoid asynchronous
logic feedbacks. Feedback can result in oscillation. ATPG are designed to
work on acyclic combinational logic. • Make FFs initializable, i.e., provide
clear and reset. • Avoid gates with a large fan-in. large fan-in makes the
inputs difficult to observe and the output difficult to control. • Provide test
control for difficult to control signals. For example, signals produced by a
long counter require many clk cycles to control. This increases the length
of the test sequence.

Structured DFT Testability measures can be used to identify circuit areas

that are difficult to test. Once identified, circuit is modified or test points
are inserted. This type of ad-hoc strategy is difficult to use in large
circuits: • Testability measures are approximations and don’t always work.
• Good fault coverage is not guaranteed from ATPG even after circuit
modifications and test point insertion is performed. Structured DFT
involves adding extra logic and signals dedicated for test according to
some procedure. The circuit has two modes, normal and test mode. The
most commonly used structured methods are Scan and BIST.

DFT stands for “Design for Test”. There are two main modes in any
design operation. Functional mode and Scan mode.
Generally the scan part can be understood as a way to discover stuck at
faults, at speed faults.
 Stuck at fault: It models manufacturing defects which occurs when a
circuit node is shorted to VDD (stuck-at-1 fault) or GND (stuck-at-0
fault) permanently. The fault can be at the input or output of a gate.
 At speed fault: This is related to the delay at the input and output
nodes of the design under consideration. So each port is tested for
logic 0-to-1 transition delay (slow-to-rise fault) or logic 1-to-0
transition delay (slow-to-fall fault).

Why do we need a reset input for DFT scan testing

I understand that the reset is required during functional mode to
initialize the flops with required values after power up. There is no such
requirement for DFT scan as we don’t depend on the reset values of
flops as we shift in the patterns and shift out the captured values. In
DFT, the reset/set pin should be directly controllable from the input.
The main aim of DFT is to provide control-ability and observability to
the design. In a good design one tries to achieve control-ability of the
inputs by constraining the primary inputs and all the outputs should be
observable at the primary outputs. The rest pin of the Flip-Flops (FFs)
used in scan chain should remain in deactivated/non-asserted state
when one is loading and unloading the patterns. In order to achieve this,
the reset/set pin should be constrained to the inactive state during
loading/unloading. Thus, it becomes necessary.
What kind of manufacturing defects (like stuck-at fault, slow-to rise/fall
issues present in gates) are possible in reset network?

Manufacturing defects like stuck-at 0, stuck-at 1 fall under stuck-at

faults category; slow-to-rise and slow-to-fall come under delay fault
model. Also there is transition faults, in which the node can toggle
from 0 to 1 but not 1 to 0 or vice-versa. For memories, we have
state-coupling faults, stuck-at faults, transition faults, address
decoder faults. Other faults are tied, redundant, blocked, unused
faults.

 I saw that i_dfx_fscan_rstbypen is used for selecting the reset

(i_dfx_fscan_byprst_b) during scan. Can i use i_dfx_fscan_mode
instead, so that we can save one extra input?

Not sure about this one, but will try to provide an analogy.
According to me the reset needs to be dedicated.
For example, The scan-mode and scan-enable are two different
signals. During the test operation of the chip, scan mode will always
remain high (means active), but scan-enable will toggle (it will be 1
during scan chain loading and unloading, while it will be 0 during
the capture cycle in the test-operation mode.

Well controlling the reset pin of the flop is only to increased the scan
coverage.
if there is not enough pads for that, the reset should in the inactive
state to be able to shift in/out the scan chains. The main reason why
test reset should be used is that you will not cover paths to
SET/RESET pins of the DFF, as functional reset should be inactive
during scan test. Thus any defect on reset path (except stuck-at
which will prevent scan chain from shifting) will not be detected.

Generally you need only 1 extra pin - 'test_mode' for DFT. Any
other can be multiplexed. (In some cases internally generated
test_mode can be used, but this technique is far more complex).
a reset signal can also be internally generated in the design, during
scan shift this reset signal can get activated and reset a particular
flop in the chain, if this happens then all the flops proceeding to the
reset flop will receive reset value and not the intended input pattern.
Hence a flop which needs to be included in the scan chain must have
its reset completely controlled in the DFT mode. With the complete
control-ability the reset will be held inactive during scan shift and
during capture the control should be given to the functional path.

Scan chains are stitched using the Flip Flops present in the design,
which is used for testing the combinatorial logic of the chip. For
testing the memories, Built in Self-Test (BIST) is performed.
Automatic Test Pattern Generation (ATPG) is a major step in this
process where patterns are generated, which are simulated (pattern
validation) to test for possible causes of failure of the chip.

How to toggle reset to get coverage?

If the reset is asynchronous (and properly bypassed during scan),

you can declare the reset pin as a clock during ATPG, and ATPG
will toggle it accordingly to get faults on reset pin.
If the reset is synchronous, you can treat the reset pin as a normal
data pin, and ATPG should be able to cover faults on the reset.
Be careful, however, if you run transition fault ATPG. Reset usually
cannot toggle at-speed, so you may not want to declare the reset as a
clock when running transition fault ATPG.
You can also try to run the patterns that toggle the reset as a clock
pin at a reduced speed on the tester, if you worry about transition
fault coverage on reset.

SCAN

Main idea is to obtain control and observability for FFs. It reduces

sequential TPG to combinational TPG. With Scan, a synchronous
sequential circuit works in two modes. Normal mode and test mode:
 In test mode, all FFs are configured as a shift register, with Scan-in
and Scan-out routed to a (possibly dedicated) PI and PO.
Once initialized, normal mode is used to apply a pattern to the PIs, and the
results are latched in the FFs. The circuit is put in test mode again and the
results scanned out.
Note that scan is usually inserted after the circuit is verified to be
functionally correct.

SCAN Styles
There are three types of scan styles that are commonly talked about in the
industry. They are, 1. Multiplexed Scan Style 2. Dual Clock Scan Style
and 3. LSSD (Level Sensitive Scan Design) style
Even though all the above three methods achieve the same goal, there are
preferences among the designers and foundries to follow one of the above
three methods. The most commonly used method is the first one
(MUXScan style) and this is a simpler method too. Most of the tools and
ASIC vendors support this method of scan design. The second method is
also not a very difficult one. The difference here is that there will be a
separate clock for the scan mode, apart from the normal functional mode
clock. These two methods are more suitable for flip-flop based designs.
The third method is more suitable for latch based designs and the ASIC
vendor has to support this scan design using special types of cells
particularly designed for this method. These scan cells occupy almost
double the size of the normal flop cell and hence there is a huge area
impact on the chip. This method is not very widely used. IBM supports
this method in their design flow due to some special reasons. In this
document we will be discussing only about the most commonly used scan
design, the muxscan design. In this flow, each of the flops in the logic will
be replaced by an equivalent scan cell. The scan cell differs from the
normal flop by the fact that it has a multiplexer in front of the input pin
“D”. The figure below shows the normal flop and an equivalent scan flop.
The multiplexer has two inputs and a select line. During the normal mode
the “TE” (test enable) pin of the scan flop will be “zero” and the MUX
selects the normal mode input to the “D” pin of the actual flop. During the
test mode, the “TE” pin will be driven to “one” for applying the input
vectors. When the “TE” pin is “one” the test input (TI) is selected by the
MUX and applied to the input pin “D” of the flop. With this arrangement
of the flop with a multiplexer, we can hook up a scan chain to test various
portions of the die.