An Introduction to DFT

Pattern Generation | Topic 6 of 10

“ Abstract
In DFT, a manufacturing defect, whether it is due to Stuck-at, bridging,
switching, or delay faults, the only way to find out is to apply certain test
patterns as per the type of fault it is; we have seen that these patterns can be
transferred into fault site through a scan chaining flops and is the most widely
used & cheap method of achieving DFT; but we have derived the patterns with
the help of truth table so far and this is not the way how the patterns are
generated practically; in this section, we’ll try to look at different ways to
generate patterns with pros & cons associated with it.
1

Where We are?

Fault Models Pattern Generation DFT Techniques

• Stuck at faults • Pattern • Scan Insertion
• Bridging faults generation • Scanned
• Delay faults • Fault simulation Flipflop
• Switch level • ATPG • Boundary scan
• Pattern (JTAG)
faults
generation • BIST
algorithms

Copyright @ Tanmoy Das, 2021

2

What is Pattern Generation (PG)?

• The aim of test generation at the gate level is to verify that

each logic gate in the circuit is functioning correctly, and the
interconnections are good
• We apply a specific set of signals to the circuit input as a
test to identify a certain fault as per fault model considered
for example, a SA0/1 at a certain node or a delay in a gate
etc. this is known as the Test Vector,
• To detect all the stuck-at faults, we need to apply a series of
test vectors sequentially, this series is also known as the
Test Pattern, here our task is to generate patterns

Copyright @ Tanmoy Das, 2021

3

Pattern Generation problems

• The simplest way to test these designs is by verifying the

responses to all input combinations, this can be done by
applying each input combination and observing each
corresponding output, called exaustive testing
• Here, for n input signals one has to consider 2n no of single
SA faults & path delay faults, 3K-1 nos of multiple SA faults
etc. as discussed previously, this means there are huge no
of set of test vectors or test patterns are associated with,
• What would happen there are millions of gates in a design?
The number of test vectors would grow drastically

Copyright @ Tanmoy Das, 2021

4

Pattern Generation problems

• With a clock frequency of100 MHz, a tester would take

probably 300 ms & 130 days!! for a 25 & 50 input designs
respectively
• Also, have to store all 250 Golden or reference responses for
the comparions with responses from the faulty design,
memory requirement increases exponentially with no of states
to compare
• A tester is a device where designs are tested after fabrication,
it is a clock speed & memory constrained device , ex. Agilent
93000 SOC Series tester has a 1024 Pins Testhead

Copyright @ Tanmoy Das, 2021

5

Pros & cons of Truth Table approach

• The most straightforward method for generating tests for a

particular fault is to compare the truth-table of the fault-free
and the faulty circuits
• It is less time consuming than ‘exhaustive testing’, where for
n inputs one has to apply 2n input patterns
• But a kind of manual approach to match the response form
faulty design, not suitable for automatic generation of
patterns

Copyright @ Tanmoy Das, 2021

6

Other Pattern Generation Methods

• All though TT method is streight forward it is not suitable for

when no of tests are very large, there are slightly improved
approaches:
1. Boolean Difference Method
2. Path Sensetization Method

Copyright @ Tanmoy Das, 2021

7

Boolean Difference Method

• The basis of this method is Fgood Ffaulty = 1, where F is the

response of a given combinational circuit
• If the given combinational circuit is F = f(A,B,C,....), where
A,B,C .. are the inputs to the circuit, then the circuit can be
represented with the help of Shanon’s expansion around
input A will be:
= . = + . =

Copyright @ Tanmoy Das, 2021

8

Boolean Difference Method contd.

• If we consider a single Stuck At fault at A, which can be SA0

& SA1 we can write the following:
⊕ = 1, for a SA0 Fault ...... (1)
⊕ = 1, for a SA1 Fault ...... (2)
• Let us take the example of SA1 fault and try to establish a
relation from equation 2 by expressing F in terms of
Shannon’s Expansion:

Copyright @ Tanmoy Das, 2021

9

Boolean Difference Method contd.

⊕ = 1
⇒ (A. + . )⊕ =1

⇒ (A. + . ). + (A. + . ). =1

By applying De-Morgan’s Theorem & simplifying LHS we can write the following:

⇒ ( ⊕ ) = 1 ................... (3)

The term ⊕ is called Boolean difference and is denoted by:

= ⊕ .............. (4)

Copyright @ Tanmoy Das, 2021

10

Boolean Difference Method contd.

So for a SA1 fault the relation from equation 3 can be written as:

. = 1 ........ (5)
Similarly, we can write same relationship for a SA0 fault as:

A. = 1 ........ (6)
Where Boolean difference can be found from equation 4

• Now, please note that the input combination for which the equation
5 satisfies are the input vectors for a SA1 fault & similarly equation 6
for a SA0 fault

Copyright @ Tanmoy Das, 2021

11

Boolean Difference Example,

In the given circuit find out patterns for a SA1 using boolean difference method

=( + ) + .( + ) , we have to calculate
A F
Here

. = 1 for SA1 & A. = 1 for SA0

B
C

Here, = ⊕ ,
Equation 7 is the relation for
=( + ) + 1. ( + )=0 SA1 fault, and the set of
=( + ) + 0. ( + ) = + pattern satisfying it is {0XX},

= + , and . = 1 => . + = 1 ...... (7)

Test vectors {000, 010,001}

Copyright @ Tanmoy Das, 2021

12

Boolean Difference Example,

To verifiy if the obtained pattern from Boolean Expression let us cosider the TT
SA1 1
A B C F FSA1 A F
0 0 0 1 0
B
0 0 1 1 0 C
0 1 0 1 0
0 1 1 1 0 • It is clear from the TT that the
1 0 0 0 0 pattern is {0XX}, and is same
1 0 1 0 0 as obtained in Boolean
1 1 0 0 0
Difference Method
1 1 1 0 0

Copyright @ Tanmoy Das, 2021

13

Boolean Difference Pros & cons

• Boolean difference takes much lesser time as compared to

Exaustive testing & even with Truth Table based approach
• It is a Mathematics based approach can be implemented
using softwares, and hence reduces human efforts to
generate patterns
• At the last step we have to findout input combinations, that
satisfy Fgood Ffaulty = 1 relation, suitable algorithm has to
be find out for this purpose, sometimes it is complex

Copyright @ Tanmoy Das, 2021

15

Path Sensitization Method Intro

• The key point in Boolean Difference is one has to know the

‘Logical Expression’ of the given circuit, F = f(A,B,C,....)
• But in practical cases such opportunities are not avaliable,
infact after synthesis DFT activity starts with the ‘netlist’,
which is just an interconnection of logic gates but no
information of ‘Logical Expression’
• So, in practical cases this method can’t be used, rather a
familly of PG methods is based on Path Sensitization
Method which as advantages over previos methods
Copyright @ Tanmoy Das, 2021
16

Path Sensitization Method

• Path Sensitization Method has 3 basic steps which doesn’t

require any logical expression of a given circuit, the steps
are:
1. Fault excitation
2. Forward Propagation
3. Backward Propagation
• With an example let’s try to understand the method

Copyright @ Tanmoy Das, 2021

17

Path Sensitization | Fault excitation

• It is the step where a Fault is introduced at the fault site by

forcing the net by an opposite value signal to which it is
stuck-at.
Forcing 0 at A
Let us take the previous circuit & try 0 Y
A F
to generate pattern through each step,
Consider a SA1 fault, B
C X Z

Copyright @ Tanmoy Das, 2021

18

Path Sensitization | Forward Propagation

• The effect of forcing is propagated till the primary output

where the resultant logical value is observed

After forcing A to 0, the effect is propagated Forced 0 at A 0

Y
along path A-Y-F & note that the result of A F
D
forcing at Y is denoted as D and it is B
propaged along the said path, now as the C X Z
Last gate is NOR and the only way to detect
the descrypency D is to observe F =

Copyright @ Tanmoy Das, 2021

19

Path Sensitization | Backward Propagation

• Once the path has been sensitized successfully, we just

need to traverse behind every gate and assign the desired
value to the net until we reach the primary inputs
For F = , Z has to be 0, which requires X = 1, Forced 0 at A 0
Y 0
for that BC needs to be {01 or 10} A F
D
Now A=0(forced), so D = 0, F = 1, hence the B 1 1
1/0
pattern is {010 or 001} & we observe F to be 1, 0
0/1 C X Z
Note: That the pattern obtained is satisfying
the Boolean difference & TT method which
was {0XX}

Copyright @ Tanmoy Das, 2021

20

Path Sensitization pros & cons

• The main advantage of Path Sensitization is it doesn’t

require any Logical Expression, so it can readily be
applicable to netlist
• Also very fast as compared to TT & boolean difference
method, as there is no of solving differnce equations like in
boolean difference
• But, here at the 3rd stage we need sophisticated backward
propagation algorithm and sometimes it becomes complex

Copyright @ Tanmoy Das, 2021

THANKS!
Any questions?
You can find me at linkedin.com/in/dastanmoy92/ or
tancarrer.ece@gmail.com