An Introduction to DFT

Fault Models | Bridging & Switch level Fault

“ Abstract
We have been dealing with stuck-at, Scan chain insertion in out previous ppts,
it is now possible to get back and explore other fault models, in this ppt the
faults associated with bridging of two nets & Some Switch level faults are of
interest, we’ll see why they are needed & ways to identify the faults
1

Hierarchy and Abstraction in VLSI Design

Algorithmic Layout

Specs Floorplan
Transitor
RTL /Switch
Placement
RTL Design

CTS
Verification
Gates
Routing
Synthesis Physical
Fabrication Fabrication Transitor
Fabrication

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2

Hierarchy and Abstraction in VLSI Design

• Stuck-at, bridging
Types of Fault Models

& transitional delay Algorithmic

models work on
gate level RTL
representation of a
design Gates Stuck-at,
Design Flow
Transitional Delay
• Switching fault
models describes Layout Bridging
a Transistor fault
Transitor
of a design /Switch
Switching

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3

Where We are?

Fault Models Pattern Generation DFT Techniques

• Stuck at faults • Pattern genration • Scan Insertion
• Bridging faults problem • Scanned
• Delay faults • Fault simulation Flipflop
• Switch level • ATPG • Boundary scan
• Pattern (JTAG)
faults
generation • BIST
algorithms

Copyright @ Tanmoy Das, 2021

4

Bridging Faults in a Design

• Bridging faults appear when

two or more normally distinct
signal lines in a Boolean logic
network are unintentionally
shorted together
• Due to direct connection a
‘wired logic’ is formed Extra metal sorting two metal
between them traces, causes bridging fault
Pic Courtesy: Mentor graphics

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5

Bridging Faults Cases

• 3 Different types of scenario can occur:

Some
Logic
Some
Gate
Logic
Input Bridging Gate

Some
Logic Some
Gate Logic
Some
Gate
Logic
Gate
Output Bridging
Feedback Bridging

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6

Input Bridging

• Both the inputs gets the same logical value

Some Logic Gate Equvallent behaviour

Logic Due to Bridging
Gate AND, OR A simple resistive wire
Input Bridging NAND, NOR NOT

XOR O/P always 0

XNOR O/P always 1

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7

Bridging at the output of two or more gate

• fanout branch of a signal line

is involved in a bridge
• Exmp, fanout of two NOT gate
under bridging
• PMOS & NMOS here working
as two resistors and the
equvallent electrical circuit
looks like:

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8

Bridging at the output of two or more gate

• Logic Level at O/P depends on

the Value of RP1 & RP2
• Vout = VDD×RN/(RN+RP)
• Two cases:
• RN << RP , N2 ON, P1 Off, A = B
= 0, Majority 0, Wired-AND (0-
Note: Due to bridging fault both A and B
dominant)
will have same voltage level
• RN ≫RP , N2 ON, P1 Off, A = B =
1, Majority 1, Wired-OR (1-
dominant)

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9

Bridging at the output of two or more gate

X
Fault Faulty Response Model
a a+
Free
{a,b} Wired-OR Wired-AND b
{a+, b+} {a+, b+} Y
b+
00 00 00 X a a+
Wired-OR
01 11 00
Y b b+ X
10 11 00 a+
a
11 11 11
Y b
b+
Note: The AND & OR are representation
(as shown dotted), not a physical gate
Wired-AND

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10

Bridging at the output of two or more gate

• The table in the previous page should be used in case of a

bridging fault (As per wire-OR or wire-AND)
• The selection of wire-OR or AND depends on the usage of
the logic family, for example, in CMOS circuits a bridging fault
has to be replaced with a wire-AND model responses

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11

Feedback Bridging Fault Model

• When an input is sorted with the output creating a feedback

connection
• Two cases can occur,
1. Latch creation, one of the output never changes
2. Sustained oscillation, constantly switches between logic 1 & 0

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12

Feedback Bridging | Latch Creation

Inputs Fault Faulty Response

Free Model X
Z
{X,Y} Z Wired-AND Z+
Y
00 0 0

01 1 0

10 1 1

11 1 1

X Z
• With a pattern {00} followed by {01} can Z+
detect this type of Fault, as both cases data Y
is latched X

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13

Feedback Bridging | Oscilattion

Inputs Fault Faulty Response

Free Model X Z
{X,Y} Z Wired-OR Z+
Y
00 1 Oscillation

01 0 1 Wired-OR
10 0 1

11 0 1
X
• Only pattern {00} can detect this type of
Y
Z
Z+
Fault, as an oscillation is found at the output
X

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14

Bridging Fault Example

There is a bridging fault between B & C, find out patterns to detect the said fault

Input Fault Wired Wired-

ABC Free -OR AND
000 0 0 0
001 1 1 0
010 1 1 0
011 1 1 1
100 0 0 0 Fault Model Pattern

101 0 1 0 Wired-OR {101} or {110}

110 0 1 0 Wired-AND {001} or {010}
111 0 1 1

Copyright @ Tanmoy Das, 2021

15

Where We are?

Fault Models Pattern Generation DFT Techniques

• Stuck at faults • Pattern genration • Scan Insertion
• Bridging faults problem • Scanned
• Delay faults • Fault simulation Flipflop
• Switch level • ATPG • Boundary scan
• Pattern (JTAG)
faults
generation • BIST
algorithms

Copyright @ Tanmoy Das, 2021

16

Switch Level Faults

• So far we have considered faults at the gate level & entirely

dealt with logical values at the output of a gate due to SA,
bridging faults
• But the transistors in a gate are also are equally
succeptable to manufacturing defects like nets, transistors
acts as switch in digital circuits and hence the name
• Two possible cases can happen:
1. Transistor doesn’t turn on at all, called stuck-open fault
2. Transistor is on always, called stuck-on fault
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17

Stuck-open Faults
VDD
• This happens when one or more
transistors doesn’t conduct TBP
• Let’s assume TBP doesn’t conduct
Inputs Fault Faulty Response TAP
Free TBP OFF
F
{A,B} F F
00 1 High Imp
TBN CL
01 0 0
TAN
10 0 0

11 0 0

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18

Stuck-open Faults
VDD
• High Impedance is something which
can’t be 0 or 1, so in this way by TBP
sending {0,0} we can’t detect the
Stuck-open fault at TBP
TAP
• Solution, Have to send a pair of F
values:
1. Send {A,B} = {1,0}, makes F = 0 TBN CL
2. Send {A,B} = {0,0}, makes F = Z TAN
• IF in step2 the logical values is not 1
we detect a Stuck-open fault at TBP
Copyright @ Tanmoy Das, 2021
19

Stuck-short Faults

• This happens when one or more transistors always conduct

• Form a conducting path between VDD and GND in static
state, just tike a voltage divider arrangement between them
• Output logic values depends on relative impedance of
transistors, and hence NOT detected by Boolean testing at
output
• Stuck-on fault can be detected by IDDQ testing, ie Drain to
source quisent current measurement

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20

Stuck-short Faults | IDDQ testing

• Apply pattern, in this case A

{1-〉0} transition,
• Measure quiescent current
Q
from power supply:
ID
1. If I shows a reading within a
D
High
limit, No fault
Current
2. If I shows a High Current
D
reading, Stuck-short fault is
there Threshold
Current

Copyright @ Tanmoy Das, 2021

21

Important points

• Not all Bridging faults is covered by SA patterns, it requires own

patterns
• Bridging fault model changes with implemented logic families
• Number of bridging faults can be too many! in the order of O(n2),
need to identify pairs of neighbor signals from layout, called ‘fault
extraction’ from layout
• Stuck-off fault requires 2 sets of patterns where SA required 1for a
single fault
• Stuck-on fault is detected by IDDQ testing, but in lower technology
nodes, detecting current change is challenging

Copyright @ Tanmoy Das, 2021

THANKS!
Any questions?
You can find me at linkedin.com/in/dastanmoy92/ or
tancarrer.ece@gmail.com