TABLE OF CONTENTS

Title Page No.

List of Figures 2
List of Tables 3
Abstract 4
CHAPTER 1:INTRODUCTION
1.1 INTRODUCTION 5
1.2 OPERATION 6
1.3 BASICS OF DIFFERENTIAL AMPLIFIER 7
1.3.1 Difference between opamp and comparator 7,8
1.3.2 characteristics of comparator 9
1.3.3 Specifications 9
1.3.4 Power consideration in CMOS 9,10
1.4 LOW POWER DESIGN 10-12
CHAPTER 2: LITERATURE SURVEY 13
CHAPTER 3: SOFTWARE REQUIRMENTS
3.1 WHAT IS LTSPICE 14
3.2 OVERVIEW 14
CHAPTER 4:PROPOSED METHOD 15-16
CHAPTER 5:RESULTS AND DISCUSSIONS 17
5.2 SIMULATION RESULTS 18
5.3 MAGINTUDE RESPONSE AND SLEW RATE 19
CHAPTER 6:CONCLUSION 20
6.1 FUTURE SCOPE 21
6.2 COMPARATORS IN PRESENT ELECTRONICS WORLD 22,23
6.3 APPLICATIONS 24

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 List Of Figures

Fig no Name of the figure Page no

1.1 Basic comparator 5

1.2 Output waveforms of basic comparator 6

1.3 Conventional opamp 7

1.4 Conventional comparator 8

4.1 Proposed design 16

5.1 Circuit for transient analysis 16

5.1.1 Transient analysis 17

5.2 Circuit for AC analysis 17

5.2.1 AC response 18

5.3 Magnitude response 19

5.3.1 Slew rate 19

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 List of Tables

Table number Table name Page no

4.2 Transistor size 16
5.4 Simulation analysis 20
6 Performance specification 21
comparision of
conventional and proposed
comparator

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 ABSTRACT
Design of very large scale analog integrated circuit (analog VLSI) is very much
complex and requires much compromising nature to achieve application specific
objective. With maximizing the efforts to reduce power consumption and to reduce W/L
ratio, the analog integrated circuit industry is constantly developing smaller power
supplies. Now days, challenges of analog integrated circuit designer are to make block
of small power supplies with little or no reduction in performance. The CMOS LOW
POWER COMPARATOR is designed in 350nm CMOS technology with 3.3V power
supply to observe the configurations. Design and simulation of CMOS LOW POWER
COMPARATOR is done using LTspice tool. Simulation results of CMOS LOW
POWER COMPARATOR shows that the Open loop gain is 80.44dB with the bias
voltages of 0.8V,0.88V,0.5V,0.3V.

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 CHAPTER – 1
INTRODUCTION

1.1 INTRODUCTION

The Op-amp comparator compares one analogue voltage level with another
analogue voltage level, or some preset reference voltage, VREF and produces an output
signal based on this voltage comparison. In other words, the op-amp voltage comparator
compares the magnitudes of two voltage inputs and determines which is the largest of
the two.
We have seen that the operational amplifier can be used with negative feedback to
control the magnitude of its output signal in the linear region performing a variety of
different functions. We have also seen that the standard operational amplifier is
characterised by its open-loop gain AO and that its output voltage is given by the
expression: VOUT = AO(V+ – V-) where V+ and V- correspond to the voltages at the
non-inverting and the inverting terminals respectively.

Voltage comparators on the other hand, either use positive feedback or no feedback
at all (open-loop mode) to switch its output between two saturated states, because in the
open-loop mode the amplifiers voltage gain is basically equal to AVO. Then due to this
high open loop gain, the output from the comparator swings either fully to its positive
supply rail, +Vcc or fully to its negative supply rail, -Vcc on the application of varying
input signal which passes some preset threshold value.
The open-loop op-amp comparator is an analogue circuit that operates in its non-linear
region as changes in the two analogue inputs, V+ and V- causes it to behave like a
digital bistable device as triggering causes it to have two possible output
states, +Vcc or -Vcc. Then we can say that the voltage comparator is essentially a 1-bit
analogue to digital converter, as the input signal is analogue but the output behaves
digitally.
Consider the basic op-amp voltage comparator circuit below.

Fig 1.1 Basic comparator

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Different types of comparators:

 Open loop comparator

 Closed loop comparator
 Hybrid comparator
1.2 OPERATION
With reference to the op-amp comparator circuit above, lets first assume that VIN is less
than the DC voltage level at VREF, ( VIN < VREF ). As the non-inverting (positive) input
of the comparator is less than the inverting (negative) input, the output will be LOW
and at the negative supply voltage, -Vcc resulting in a negative saturation of the output.
If we now increase the input voltage, VIN so that its value is greater than the reference
voltage VREF on the inverting input, the output voltage rapidly switches HIGH towards
the positive supply voltage, +Vcc resulting in a positive saturation of the output. If we
reduce again the input voltage VIN, so that it is slightly less than the reference voltage,
the op-amp’s output switches back to its negative saturation voltage acting as a
threshold detector.
Then we can see that the op-amp voltage comparator is a device whose output is
dependant on the value of the input voltage, VIN with respect to some DC voltage level
as the output is HIGH when the voltage on the non-inverting input is greater than the
voltage on the inverting input, and LOW when the non-inverting input is less than the
inverting input voltage. This condition is true regardless of whether the input signal is
connected to the inverting or the non-inverting input of the comparator.
We can also see that the value of the output voltage is completely dependent on the op-
amps power supply voltage. In theory due to the op-amps high open-loop gain the
magnitude of its output voltage could be infinite in both directions, (±&#8734).
However practically, and for obvious reasons it is limited by the op-amps supply rails
giving VOUT = +Vcc or VOUT = -Vcc.

Fig 1.2: Output waveforms

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1.3 BASICS OF DIFFERENTIAL AMPLIFIER

The differential amplifier is probably the most widely used circuit building block in
analog integrated circuits, principally op amps. when we were discussing input bias
current. The differential amplifier can be implemented with BJTs or MOSFETs. A
differential amplifier multiplies the voltage difference between two inputs (Vin+ - Vin-)
by some constant factor Ad, the differential gain. It may have either one output or a pair
of outputs where the signal of interest is the voltage difference between the two outputs.
A differential amplifier also tends to reject the part of the input signals that are common
to both inputs (Vin+ + Vin-)/2 . This is referred to as the common mode signal.

Fig 1.3: CMOS Conventional opamp diagram

1.3.1DIFFERENCES BETWEEN OPAMP AND COMPARATOR

 In CMOS opamp the output of the first stage is provided with a compensation
capacitor to make the opamp stable but in CMOS comparator the compensation
capacitor is not provided.Comparator is clocked. An op-amp is not.
 Clock controls whether comparator is acquiring the input or applying positive
feedback to produce a logic level output

 Comparator has much lower gain.

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 Comparator has infinite TIME gain. If you allow sufficient regeneration time, the
comparator will produce a logic output.
 Op-amp has extremely high small signal gain.
 Comparator small signal gain is *usually* relatively low especially compared to an
op-amp.
 Op-amp is probably not as fast for comparator applications.
 Comparator is specifically implemented to have very fast regeneration time (usually
this is a specification).
 Op-amp may have large signal slew rate limitations.

Fig 1.4: CMOS comparator conventional diagram

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1.3.2 CHARACTERESTICS OF COMPARATOR

Following are some of the important characteristics of comparator.

Speed of operation:
The switching between the two output states should be as fast as possible. Thus the
output should respond the input changes quickly.
Accuracy:
It is the smallest amount of input difference voltage required to make the output to
change its state
Strobe function:
To enable/disable the device, certain comparators are having a strobe terminal. When it
is enable, output will respond to input. If it is disabling, output will not respond to input
signal
Latch: some of the comparators are having latching facility. The required output state is
frozen in a latch flip flop.

1.3.3 SPECIFICATIONS

A power supply voltage of 3.3V with input voltage of 1V,20kHz and Input
Common Mode Range (ICMR)of 0.4-3V shows that comparator exhibits an
ultra low power consumption of 53uw at signal frequency of 100Khz having
reference voltage of 0.3V. This proposed comparator also provides Gain of 80
dB and Unity gain bandwidth of 10Mhz .Slew rate is 2.5v/usec. Load
capacitance value is 0.1pF.

1.3.4 POWER CONSIDERATION IN CMOS

Power is one of the vital resources. Hence, the designers try to save it when
designing a system. Power dissipation is dependent on the switching activity,
node capacitances (made up of gate, diffusion, and wire capacitances), and
control circuit size. There are four source of power dissipation: dynamic
switching power due to the charging and discharging of circuit capacitance,
leakage current power from reverse biased diodes and sub-threshold

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conduction, short-circuit current power due to finite signal rise/fall times, and static
biasing power found in some logic styles (i.e. pseudo-nMOS).
PT =PD + PL+ PSC +Ps
Dynamic switching power is the major component of overall power dissipation, the
low-power design methodology concentrates on minimizing total capacitance,
supply voltage, and frequency of transistor.
PD=CV2 F
For Analog circuits design power consumption is mainly depends upon the Signal to
noise ratio(S/N) and frequency of operation also
P=SNR 8Kt Vp-p/Vb
For most CMOS circuit design, the short circuit power dissipation is approximately
5-10% of the total dynamic power. The sub-threshold current is proportional to the
transistor device size (W/L) and an exponential function of the supply voltage.
Thus, the current may be minimized by reducing the transistor sizes, and by
reducing the supply voltage. Scaling in the supply voltage appears to be the most
well-known means to reduce power consumption. However, the lower-supply
voltage increases circuit delay and degrades the drivability of cells designed with
certain logic style. One of the important obstacles in decreasing the supply voltage
is the large transistor count and Vth loss problem. By selecting proper (W/L) ratio
we can minimize the power dissipation without decreasing the supply voltage.In this
paper we have achieved the W/l ratio to achieve lowest average power consumption
in .35um CMOS technology.

1.4 LOW POWER DESIGN

Power analysis of CMOS circuits:
 The power consumption of digital CMOS circuits is generally considered in terms
of three components:
 The dynamic power component, related to the charging and discharging of the load
capacitance at the gate output.
 The short-circuit power component. During the transition of the output line (of a
CMOS gate) from one voltage level to the other, there is a period of time when both
the PMOS and the NMOS transistors are on, thus creating a path from VDD to
ground.
 The static power component, due to leakage, that is present even when the circuit is

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 not switching. This, in turn, is composed of two components - gate to source
leakage, which is leakage directly though the gate insulator, mostly by tunnelling,
and source-drain leakage attributed to both tunnelling and sub-threshold
conduction. The contribution of the static power component to the total power
number is growing very rapidly in the current era of Deep Sub-Micrometre (DSM)
Design.
 Power can be estimated at a number of levels of detail. The higher levels of
abstraction are faster and handle larger circuits, but are less accurate. The main
levels include:
 Circuit Level Power Estimation, using a circuit simulator such as SPICE
 Static Power Estimation does not use the input vectors, but may use the input
statistics. Analogous to Static timing analysis
 Logic-Level Power Estimation, often linked to logic simulation
 Analysis at the Register-Transfer Level. Fast and high capacity, but not as accurate.
 Circuit-level power optimization


 A rendering of a small standard celll taken from a larger design showing heating
effects directly related to power consumption.
 Many different techniques are used to reduce power consumption at the circuit level.
Some of the main ones are:
 Transistor sizing: adjusting the size of each gate or transistor for minimum power.
 Voltage scaling: lower supply voltages use less power, but go slower.
 Voltage islands: Different blocks can be run at different voltages, saving power.
This design practice may require the use of level-shifters when two blocks with
different supply voltages communicate with each other.
 Variable VDD: The voltage for a single block can be varied during operation - high
voltage (and high power) when the block needs to go fast, low voltage when slow
operation is acceptable.
 Multiple threshold voltages: Modern processes can build transistors with different
thresholds. Power can be saved by using a mixture of CMOS transistors with two or
more different threshold voltages. In the simplest form there are two different
thresholds available, common called High-Vt and Low-Vt, where Vt stands for
threshold voltage. High threshold transistors are slower but leak less, and can be
used in non-critical circuits.
 Power gatingg: This technique uses high Vt sleep transistors which cut-off a circuit

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block when the block is not switching. The sleep transistor sizing is an important design
parameter. This technique, also known as MTCMOS, or Multi-Threshold CMOS
reduces stand-by or leakage power, and also enables Iddq testing.
 Long-Channel transistors: Transistors of more than minimum length leak less, but
are bigger and slower.
 Stacking and parking states: Logic gates may leak differently during logically
equivalent input states (say 10 on a NAND gate, as opposed to 01). State machines
may have less leakage in certain states.
 Logic styles: dynamic and static logic, for example, have different speed/power
tradeoffs.
 Logic synthesis for low power:
 Logic synthesis can also be optimized in many ways to keep power consumption
under control. Details of the following steps can have a significant impact on power
optimization:
 Clock gating
 Logic Factorization
 Path Balancing
 Technology Mapping
 State Encoding
 Finite-State Machine Decomposition
 Retiming
THEORITICAL ANALYSIS:

Design Equations:

 Gm1 = 2*pi*UGB*C

 (W/L)1,2,3 = (Gm1^2)/2*kn*I9

 (W/L)4,5,6,7,8=I9/Kp*(Vdd-VICMR+-VT0+VT1)^2

 (W/L)10 = I9 * Gm10/Gm6 *(W/L)6

 (W/L)9 = (Ig*2)/Kn(Vsat)^2

 (W/L)11 =( (Ig*2)/Kn(Vsat)^2)*gm11/gm9

 Kp=6.475*10^-6

 kn=0.72*10^-8

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 CHAPTER – 2

LITERATURE SURVEY

Currently research studies are focussing on designing high performance analog circuits
at reduced power and supply voltage. The comparator remain as the key element in
various analog integrated circuits. The realization of the comparator in low power
circuits to achieve high DC gain and high bandwidth is a difficult task.

The two stage operational transconductance amplifier described by Behzad Razavi

(2002) achieves high gain and voltage swing due to the presence of two stages in the
circuit. This helps in obtaining good signal to noise ratio and dynamic range. However,
this amplifier also requires a miller compensation to maintain stability, which reduces
unity gain bandwidth and speed. Yet again, the power consumption is increased due to
increased area. So, single stage amplifiers are the best choice to work in reduced voltage
and power circuits.

Hernes and Sansen (2005) discuss the classification of single stage, two stage and
three stage structures based on harmonic distortion. A performance comparison of
single stage amplifier and two stage amplifier shows that single stage amplifier works
well at high frequency while two stage amplifier is good at mid frequency range. The
study also assures that noise level is maintained low for differential amplifiers with an
increases in common mode rejection ratio and power supply rejection ratio. The input
stage transistors affect the overall operation of a circuit at high frequencies and output
transistors at low frequencies.

Development of opamp lead to the development of comparator . The comparator has its
first stage as a differential amplifier and second stage as a current sink inverter.

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 CHAPTER – 3
SOFTWARE REQUIRMENTS
For the simulation of operational transconductance amplifier we used LTSPICE which
is a free integrated circuit simulator.

3.1 LTSPICE

LTspice is a high performance SPICE simulation software, schematic capture and

waveform viewer with enhancements and models for easing the simulation of analog
circuits. Included in the download of LTspice are macro models for a majority of
Analog Devices switching regulators, amplifiers, as well as a library of devices for
general circuit simulation.

3.2 OVERVIEW

LTspice IV provides a schematic capture and waveform viewer with enhancements

and models to speed the simulation of switching regulators. Supplied with LTspice IV
are macro models for 80% of LTC's switching regulators and operational
amplifiers, transistors, MOSFETs, and passive components.

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 LTspice IV is node-unlimited and third-party models can be imported. Circuit
simulations based on transient, AC, noise and DC analysis can be plotted as well as
Fourier analysis. Heat dissipation of components can be calculated and efficiency
reports can also be generated. LTspice IV is used within LTC, and by many users in
fields including radio frequency electronics, power electronics, digital electronics, and
other disciplines. LTspice IV does not generate printed circuit board(PCB) layouts, but
netlists can be imported into layout programs. While LTspice does support simple logic
gate simulation, it is not designed specifically for simulating logic circuits. LTspice was
originally called SwitcherCAD and is sometimes still called by that name. The software
is maintained by Mike Engelhardt. The application is written for Microsoft
Windows but, since 2003, it will run under the Wine Windows compatibility layer
under Linux. From version IV LTspice requires at least a Pentium 4 processor and
Windows 2000 or later. In 2016 LTspice XVII was released. It runs on 32- or 64-bit
editions of Windows 7, 8, and 10.

CHAPTER – 4
PROPOSED METHOD
Figure 4.1 shows the schematic diagram of LOW POWER CMOS COMPARATOR. In
this CMOS COMPARATOR the supply voltage is Vdd= 3.3V. In the below circuit of
COMPARATOR the Transistors, Transistors M5, M6 and M7,M8 works as two current
mirror pairs. The Transistors M1, M2, M3 and M4 are the Differential amplifier. The
Transistors M10,M11 is an output stage. The design parameters of this comparator are
shown in below table I. There are several different comparator’s are used in which this
compaarator is a simple comparator with low power consumption and high gain. The
Op-amp is characterized by various parameters like open loop gain, Bandwidth, Slew
Rate, Noise and etc. The performance Measures are fixed Due to Design parameters
such as Transistors size, Bias Voltage and etc. In this project we describe design of
comparator and this design is done in 0.35μm technology.

In this architecture (Fig4.1) there are two stages first stage is composite cascode
differential amplifier Nchannel input devices (M1-M4) in series with combination of
cascode active Pmos based current mirror load such as (M5-M8) that compares the two
input but provide smaller gain while the second stage is common source provide larger
swing and greater gain similar to opamp based conventional two stage open loop

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comparator and one nchannel Mos is provided below which act as current sink for
stabilization. . Amplifiers are usually employed to achieve linear operation in closed
loop configuration which requires careful compensation to avoid unstable operation. On
the contrary the comparator does not require stability criteria as in two stage amplifier
so it eliminated need for compensation capacitor.

Fig 4.1 Proposed Comparator Design

As shown above the Comparator is designed with many input voltages. The right side
chart is the 0.35um technology file.

TRANSISTOR SIZE

DEVICE W/L(um)

M1,M2,M3,M9 20/0.4

M4,M5,M6,M7,M8 10/0.4

M10 17/0.4

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M11 0.4/0.4

W-WIDTH,L-LENGTH

TABLE 4.2
The above table shows the W/L ratios of the transistors used.

CHAPTER – 5
RESULTS AND DISCUSSIONS
The basic functionality of comparator is to compare input voltage with another
reference voltage , here the input signal is a sinusoidal signal and the reference voltage
is 0.3V. If the input signal is greater than reference voltage the output is Vdd else the
output is 0V.

Fig 5.1 Transient analysis circuit

For that particular applied input the output is 3.3V as shown below.

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Fig 5.1.1 Transient Response analysis
8
After obtaining the Transient analysis for the circuit we next found the AC analysis for
which we applied 1V AC in the circuit as shown below

Fig 5.2 AC Analysis

For the above circuit the AC response is as shown below

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 Fig 5.2.1 AC Analysis output waveforms

Fig 5.3 Magnitude response of circuit

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 Fig 5.3.1 slew rate

5.4 SIMULATION RESULTS

The design of LOW POWER CMOS COMPARATOR is done using LTspice tool.
The simulation results are done using spice environment using 0.35um CMOS
technology. The simulation results of LOW POWER CMOS COMPARATOR shows
that the open loop gain is of approximately 80.44dB and power consumption of
25.10uW.

The following table shows the simulation results:

Specifications Simulated

CMOS technology 0.35um

Input waveform(1) 1V Sinusoidal Signal of frequency

20KHz

Input waveform(2) 0.3V

Open loop gain 80.44dB

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Supply voltage 3.3V

Bias voltage Vb1:0.8V, Vb2:0.8V, Vb3:0.5V,

Vb4:0.88V

Power consumption 25.10uW

Table 5.4 Simulation Analysis

CHAPTER – 6
CONCLUSION
In this project we present a low power op amp based comparator which can be used in
bio medical applications . As this circuit consumes low power of around 25uW and it
also provides a high gain of around 80.44dB.

PERFORMANCE PROPOSED CONVENTIONAL

SUMMARY

GAIN(dB) 80.44 41

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UGB(MHz) 15 10

POWER 25.10 241

CONSUMPTION(uW)

POWER SUPPLY(V) 3.3 3.3

ICMR(V) 0.4-3.0 0.4-3.3

Table 6 performance specification comparision of proposed and conventional

comparator

6.1 FUTURE SCOPE

 The main scope of future work in CMOS comparator is that we have to reduce
the circuit area which is one of the important constraints in any VLSI design.
The comparator converts analog signal to digital signal with a high sampling
frequency. In future both area and time should be reduced so that an external
circuit can be built which should reduce the both constraints.

6.2 COMPARATORS IN PRESENT ELECTRONICS WORLD

 TPS3700
. The TPS3700 wide-supply window voltage detector operates over a 1.8-V to 18-V
range. The device has two high-accuracy comparators with an internal 400- mV
reference and two open-drain outputs rated to 18 V for over- and undervoltage

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detection. The TPS3700 can be used as a window voltage detector or as two
independent voltage monitors; the monitored voltage can be set with the use of external
resistors. OUTA is driven low when the voltage at INA+ drops below (VITP – VHYS),
and goes high when the voltage returns above the respective threshold (VITP). OUTB is
driven low when the voltage at INB– rises above VITP, and goes high when the voltage
drops below the respective threshold (VITP – VHYS). Both comparators in the
TPS3700 include built-in hysteresis for filtering to reject brief glitches, thereby ensuring
stable output operation without false triggering. The TPS3700 is available in a SOT-6
and a 1.5-mm × 1.5-mm WSON-6 package and is specified over the junction
temperature range of –40°C to 125°C.

APPLICATIONS

Industrial control systems ,Automotive systems ,Embedded computing modules ,DSP,

microcontroller, or microprocessor applications , Notebook and desktop computers
,Portable- and battery-powered products , FPGA and ASIC applications

 TPS3701
The TPS3701 wide-supply voltage window detector operates over a 1.8-V to 36-V
range. The device has two precision comparators with an internal 400-mV reference and
two open-drain outputs (OUTA and OUTB) rated to 25 V for over- and undervoltage
detection. Use the TPS3701 as a window voltage detector or as two independent voltage
monitors; set the monitored voltage with the use of external resistors.
OUTA is driven low when the voltage at the INA pin drops below the negative
threshold, and goes high when the voltage returns above the positive threshold. OUTB
is driven low when the voltage at the INB pin rises above the positive threshold, and
goes high when the voltage drops below the negative threshold. Both comparators in the
TPS3701 include built-in hysteresis for noise rejection, thereby ensuring stable output
operation without false triggering.
The TPS3701 is available in a SOT-6 package and is specified over the junction
temperature range of –40°C to 125°C.

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  Features
Wide supply voltage range: 1.8 V to 36 V
Adjustable threshold: down to 400 mV
Open-drain outputs for over- and undervoltage detection
Low quiescent current: 7 µA (Typical)
High threshold accuracy:
0.75% Over temperature
0.25% (Typical)
Internal hysteresis: 5.5 mV (typical)
Temperature range: –40°C to 125°C
Package:
SOT-6

6.3 APPLICATIONS

 Low power CMOS comparators are used in ECG that is he process of producing
an electrocardiogram (ECG or EKG[a]), a recording – a graph of voltage versus
time – of the electrical activity of the heart[4] using electrodes placed on the skin.
These electrodes detect the small electrical changes that are a consequence of
cardiac muscle depolarization followed by repolarization during each cardiac cycle
(heartbeat). Changes in the normal ECG pattern occur in numerous cardiac
abnormalities, including cardiac rhythm disturbances (such as atrial
fibrillation and ventricular tachycardia), inadequate coronary artery blood flow
(such as myocardial ischemia and myocardial infarction), and electrolyte
disturbances (such as hypokalemia and hyperkalemia).

 Low power CMOS comparators are also used in EEG that is in

electroencephalogram (EEG) is a test that detects electrical activity in your brain
using small, metal discs (electrodes) attached to your scalp. Your brain cells

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 communicate via electrical impulses and are active all the time, even when you're
asleep. This activity shows up as wavy lines on an EEG recording

 Low power comparators are also used in implanted medical devices.

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