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Cs6201 Digital Principles and System Design: Unit I
Cs6201 Digital Principles and System Design: Unit I
UNIT I
PART-A
2. Find the solution to the quadratic equation x2 -11x+22=0 is x=3 and x=6. What is the base of the numbers?
[May 2012]
3. Perform the following conversions (1010.10)2 -> ( ) 16, ( ) 8, ( ) 10. [Nov 2011]
4. State the different ways for representing signed binary number [Nov 2011]
5. Represent the decimal numbers -200 and 200 using 2’s complement binary form. [May 2011]
6. Write the truth table of logical AND and XOR gates. [May 2011]
11. Draw the logic diagram for the Boolean expression [(A+B)C]’D using NAND gates. [Nov 2009]
12. Perform subtraction using 1’s complement (11010)2 - (10000)2 [Nov 2009]
13. Perform 9’s and 10’s compliment subtraction between 18 and -24 [Nov 2009]
18. Convert the following number from one base to other (65.342) 8=( )7 [May 2007]
19. What is the advantage of gray codes over the binary number sequence? [May 2007]
(354.52)6 = ( ) 10
(100)10 = ( ) 16. [Dec 2006]
22. What are the different ways to represent a negative number? [Dec 2006]
23. Find the hexadecimal equivalent of the octal number 1024.77 [May 2006]
25. State a single rule, which can be used to form the complement of a Boolean expression in one step.
[Dec 2005]
27. Define the following terms: implicant, prime implicant, essential prime implicant. [Dec 2005]
30. Implement AND gate and OR gate using NAND gate. [May 2005]
33. Show that a positive logic NAND gate is the same as a negative logic NOR gate. [Dec 2004]
34. A hexadecimal counter capable of counting upto atleast (10,000) 10 is to be constructed. What is the
minimum number of hexadecimal digits that the counter must have? [May 2004]
36. Show that how NAND gates can be used to implement the basic Boolean functions. [May 2004]
40. Write the Boolean function of an X-OR gate give its truth table. [Dec 2008]
41. What is the largest binary number that can be expressed with 12 bits? What is the equivalent decimal and
hexadecimal? [May 2008]
42. Simplify (x+y) (x+y' ) to a minimum number of literals. [May 2008]
45. Reduce the Boolean function using K Map technique and implement using gates F(w, x, y, z) = ∑ (0, 1, 4, 8,
9, 10) which has the don’t care conditions d(w, x, y, ,z) = ∑ (2, 11). [Dec 2007]
47. Convert the following function into sum of product form (AB+C)(B+C’D). [May 2007]
PART-B
3.
ii). Write the Procedure for obtaining the logic diagram with NAND gates from a Boolean function
iii). Implement the switching function F(x,y,z,) =∑m(1,2,3,4,5,7) with NAND gates. [May 2012]
i)A’C’+AC’+ADC
ii)XYZ+XYZ’+X’Y
iii)AB’+ABD+ABD’+A’C’D’+A’BC’
iv)BD+BCD’+AB’C’D’
F= Σm(0, 1, 9, 15, 24, 29, 30) + d (8, 11, 31). [Nov 2010]
8. (i).Simplify the following Boolean function F together with don’t-care condition d, and then express the
simplified function in sum of minterms F (w, x, y, z) = Σ(1,3,7,11,15) + Σd (0,2,5)
(ii) Implement the following Boolean function with NAND gates. F (x, y, z) = (1,2,3,4,5,7) [May 2010]
9. Determine the prime-implicants of the Boolean function by using the tabulation method.
10. Simplify the following Boolean expression using Quine McCluskey method:
11. i) Implement Boolean expression for EXOR gate using NAND and NOR gates.
12. Simplify the following Boolean function F together with don’t care condition using Karnaugh map method.
(ii) ABC + AC + B
(iii) (A+B)(A+B)
(ii) Using k-map method obtain the minimal SOP and POS expressions for the f unction F(x,y,z,w) =
18. Find a minimum sum of products expression for the following function using Quine-McClusky method.
19. (i)Determine the minimum sum of products and minimum product of sums for
f = b’c’d’+bcd+acd’+ab’bc’d
20. (i) Find a network of AND and OR gates to realize f(a,b,c,d) =∑m (1,5,6,10,13,14)
(ii) Design a network to convert 8-4-2-1 BCD code to excess-3 code. [May 2005]
22. State and Prove the postulates of Boolean Algebra. [May 2004]
24. (i).Simplify the Boolean function using map method: F(w,x,y,z)= S(0,2,4,6,8,10,12,14)
(ii).Perform subtraction on the following numbers using the 9’s complement of subtrahend
(1)5763-3145
(2)59-9876
(3)5200-561 [May 2007]
26. Reduce the Boolean function using K Map technique and implement using gates
F(w,x,y,z) = ∑ (0,1,4,8,9,10) which has the don’t care conditions d(w, x, y, ,z) = ∑ (2, 11).
[Dec 2007]
27. What is the advantage of using Tabulation method? Determine the prime implicants of the following
function using Tabulation method.
PART-A
3. With block diagram show how the full adder can be designed using two half adder and one
OR gate [Nov 2011]
7. Distinguish between the combinational and sequential logic circuits. [May 2010]
11. What is the need for code conversion? Give two commonly used codes. [May 2009]
12. Give the truth table of Full adder. [Dec 2008/May 2004]
18. What are the modeling techniques available to build HDL module? [May2007]
21. Write down the truth table of a half subtractor [Nov 2005/ 2004]
23. Explain the design procedure for combinational circuits [May 2004]
25. Write down the truth table of a full subtractor. [Nov 2003]
27. What is meant by VHDL and what is its advantage [Nov 2003]
29. What are the two steps in Gray to binary conversion? [May 2003]
PART B
2. Design a circuit that converts 8421 BCD code to Excess -3 code. [MAY 2012]
5. Design a combinational logic diagram for BCD to Excess-3 code converter. [May 2010]
(ii) Write the HDL description of the circuit specified by the following Boolean function.
x =AB+ C
y= C′. [May 2010/ May 2006]
7. a) Explain the gray code to binary converter with the necessary diagram
8. With neat diagram explain BCD subtractor using 9’s and 10’s complement method [Nov 2009]
10. With a suitable block diagram explain the operation of BCD adder. [May 2009]
11. Draw and explain the working of a carry-look ahead adder. [Dec 2008]
12. Construct a full adder circuit and write a HDL program module for the same. [May 2008/ May 2007]
13. Construct a BCD adder circuit and write a HDL program module for the same. [May 2008]
16. Design a network of AND and OR gates to convert excess 3 code to 8-4-2-1 BCD code. [May 2007]
17. Explain the procedure for converting Binary to Gray code number and Gray code to Binary number with
samples. [Nov 2006]
18. Design a BCD adder to add two BCD digits [Nov 2005]
(ii) Draw the block diagram of 2’s complement adder/subtractor [May 2005]
22. What is the need of arithmetic circuits? Design a full subtractor .How it is different from a full adder?
[Nov 2003]
23. Design a combinational circuit that accepts 3 bit binary number and converts it to excess 3 code.
24. Design a 4 bit magnitude comparator two 4 bit numbers [Dec 2008]
25. Construct a combinational circuit to convert given binary coded decimal number into an Excess – 3 code.
Eg: when the input to the gate is 0110 then the circuit should generate output as 1001. [May 2008]
UNIT-III
PART A
3. Define Decoder. Draw the block diagram and truth table for 2-to-4 decoder. [Nov 2011]
What is programmable logic array? How does it differ from ROM? [Nov 2009]
7. What is Decoder? Draw the block diagram and truth table for 2 to 4 decoder. [May 2009]
10. Draw the circuit diagram for 3 bit parity generator. [May 2008]
14. Write the logic equation and draw the internal logic diagram for a 4-to-1 MUX. [May 2007]
21. What is a decoder and obtain the relation between the number of inputs ‘n’ and outputs ‘m’ of a decoder
[May 2005]
26. What is programmable logic array? How it differs from ROM? [May 2004]
28. Give the comparison between prom and PLA. [May 2003]
PART B
A(x,y,z)=m(1,2,4,6)
B(x,y,z)= m(0,1,6,7)
3. Construct a 5to 32 line decoder with four 3 to 8line decoder with enable a 2to 4 line decoder. use block
diagram for components. [Nov 2011]
4. Implement the following Boolean function using 16*1 multiplexer. [Nov 2011]
ii) Write HDL for gate level description using 3 to 8 line decoder
iii) With suitable timing diagram explain how read operation is performed in RAM
6. We have found a minimum sum of products expression for each of two function, F and G, minimizing them
individually (no sharing) F = WY′ + XY′Z, G = WX′Y ′ + X′Y +W′Y′Z .
Implement them in the PLA using no more than four terms.. [May 2010]
7. Define Decoder. Design a 3 to 8 decoder. With suitable block diagram explain how a 4-to-16 decoder can
be performed by using the same. [May 2009]
8. Explain the operation of DRAM with suitable diagram. Also explain how Read/Write operations are
performed in DRAM with timing diagram. [May 2009]
(ii) What is micro programmed control unit? Explain the different types of ROM. (8) [May 2008]
12. Explain the different types of shift registers with neat diagram. [May 2008]
13. Using ROM, implement a combinational circuit which accepts a 3 bit number and generates an output
binary number equal to the square of the input number. [Dec 2007]
ii) What are the advantages of PLA over ROM?Explain the internal construction of PLA. [May 2007]
F1(A,B,C)=Σ(3,5,6,7)
F1(A,B,C)= Σ(3,5,6,7)
17. A combinational circuit is described by the functions F1 =∑m(3,5,7), F2=∑m(4,5,7) Implement the circuit
with a PLA having 3inputs, 3 product terms and two outputs. [Nov 2005]
18. Write the structural VHDL description for 2 to 4 decoder and explain it in detail. [Nov 2005]
19. (i) Design a BCD to excess 3 code converter using a ROM [May 2005]
(ii)Design and explain the working of a 1 to 8 demultipexer. Compare the following PLDS: PROM, PLA, PAL
[May 2005]
20. Show that when two input multiplexer drive another 2 input MUX, the result is a 4 i/p MUX. [Nov 2004]
22. Draw a 4:1 Mux and implement the following function F=(0,1,2,4,6,9,12,14) [May 2004]
23. Explain with necessary diagram a BCD to 7 segment display decoder. [Nov 2009]
(ii)Design a BCD to excess-3 code converter and implement using PLA. [Nov 2009]
UNIT-IV
PART A
1. Write the characteristic table and equation of JK flip flop. [May 2012]
3. Write down the characteristic equation for JK and T flipflop [Nov 2011]
4. How many FF’s are required for designing asynchronous MOD60 couter. [Nov 2011]
6. Draw the excitation table and state diagram for JK and SR Flip-Flop. [May 2010]
7. Write down the differences between sequential and combinational circuit? [Nov 2009]
9. How many flip-flops are required for designing synchronous MOD 5 counter? [May 2009]
11. Convert a T-FF into an sr-FF. Draw the circuit. [Dec 2008]
13. What are the differences between sequential and combinational logic? [May 2008]
14. Draw the logic diagram for D-Type Latch. [May 2008]
15. How can a D flip flop be converted in to a T flip-flop? [May 2007, Nov 2005]
16. How many states are there in a 3-bit ring counter? What are they? [May 2007]
18. How does a J-K flip –flop differ from an S-R flip-flop in its basic operation. [Nov 2006]
20. What are the memory elements used in a clocked sequential circuit? [May2006]
21. What is meant by state diagram? [Nov 2005]
23. What are the states of a 4-bit ring counter [Nov 2005]
24. What are the principal between synchronous and asynchronous counters? [Apr 2005]
25. Distinguish between combinational logic circuits and sequential logic circuits? [Apr 2005]
26. What are the advantages of shift registers? [May 2005/Nov 2003]
28. What is the minimum of Flip flops required to build a counter of modulus 8. [May 2004]
32. How will you convert a JK flip-flop into a D-flip flop? [Nov 2003]
34. What are the various types of triggering of FF’S [Nov 2003]
35. The t pd for each flip-flop is 50 ns. Determine the maximum operating frequency for MOD - 32-ripple
counter [Nov 2003]
36. Why is a parallel counter faster than ripple counter? [Nov 2003]
PART B
(ii) Write the HDL for the above circuit. (10) [May 2012]
2. Design the sequential circuit specified by the state diagram using JK flip flop. [May 2012]
4. With suitable example explain state reduction and state assignment. [Nov 2011]
5. 3.Design a synchronous sequential circuit using JK flip-flop to generate the following sequence and repeat.
0, 1, 2, 4, 5, 6 [May 2010]
6. What is the aim of state reduction? Reduce the given state diagram and prove that the both state diagrams
are equal.
[May 2010]
7. (i) Write a verilog description for JK negative edge triggered flip flop with clock CLK.
8. (i) Design a sequential circuit with JK FF to satisfy the following state equations.
A(T+1) = A’B’CD+A’B’C+ACD+AC’D’
B(T+1) = A’C+CD’+A’BC’
C(T+1) = B
D(T+1) =D’
(ii) Draw the logic diagram of a D-FF using NAND gates and explain. [Dec 2008]
10. Design a T-FF giving the flow table, state table, state assignment, excitation table and excitation map.
[Dec 2008]
12. (i) Summarize the design procedure for synchronous sequential circuit (6)
(ii) Reduce the following state diagram. (10) [May 2008]
13. Explain the operation of 4-bit binary ripple counter. [Dec 2007]
ii) Write HDL code for the following Mealy sate diagram. [May 2007]
16. What are the general capabilities of universal shift register? And write the HDL code for the same.
[May 2007]
17. Draw the Four bit Johnson counter and explain its operation. [Nov 2006]
18. a)Design an Asynchronous BCD down counter using J-K flip=flop and verify its operation. [May 2006]
19. Design a synchronous mod-8 down counter and implement it [Nov 2005]
20. Design a sequence detector circuit with a single input line and a single output line. Whenever the input
consists of the sequence 101, the output should be 1. For example, if the input is 00110101…then the
output is 00000101.In other words, overlapping sequences are allowed. Use any type of flip flop.
[Nov 2005]
21. Design a modulus 5 counter using JK flip flop and implement it. Construct its Timing diagram. [Nov 2005]
23. Draw the schematic diagram of Master slave JK FF and input and output waveforms. Discuss how does it
prevent race around condition. [Nov 2005/May 2005/Nov 2006]
24. Design and explain the working of a synchronous mod-3 counter [May 2005]
25. Design and explain the working of a up-down ripple counter. [May 2005]
26. Using JK flip-flops design a parallel counter, which counts in the sequence 101,110,001,010,000,111,101…
[Nov 2004]
27. Using SR flip-flops design a parallel counter, which counts in the sequence 000,111,101,110,001,010,000….
[May 2004]
28. Draw the state diagram and characteristic equation of T FF, D FF, and JK FF. [Nov 2003]
29. Design and implement a Mod-5 synchronous counter using JK flip-flop. Draw the timing diagram also.
[Nov 2009]
UNIT-V
PART A
2. What is Race Condition? [May 2012/Nov 2011/May 2010/Dec 2008/ Dec 2006]
14. What is a critical race? Why should it be avoided? [Nov 2005/May 2005]
15. Define the terms race, critical race and non-critical race [Nov 2005/2003]
17. Define static 0-hazard,static 1-hazard and dynamic hazard [Apr 2005/ Nov 2004/Nov 2003]
18. What is the most important consideration in making state assignments for asynchronous networks
[Apr 2005]
19. What is the difference between Mealy machine and Moore machine [Apr 2005]
20. Give the comparison between state Assignment Synchronous circuit and state assignment asynchronous
circuit. [May 2004/ Dec 2005]
21. Explain the procedure for state minimization. [May 2004/Dec 2005]
22. What are the types of asynchronous circuits [May 2004/ Dec 2005]
23. What are the steps for the design of asynchronous sequential circuit? [May 2004]
24. What is fundamental mode sequential circuit? [May 2003/ May 2004]
PART B
1. Design an asynchronous sequential circuit that has 2 inputs X2 and X1 and one output Z. When X1=0, the
output is 0. The first change in X2 that occurs while X1 is 1 will cause output Z to be 1. The output Z will
remain 1 until X1 returns to 0. [May 2012]
2. Find a circuit that has no static hazards and implements the Boolean function
F(A,B,C,D)=(1,3,5,7,8,9,14,15). [May 2012]
5. With suitable example and diagram explain the hazards in combinational and sequential logic circuits.
[May 2010]
6. With necessary example and diagram explain the concept of reduction of state and flow tables.
[May 2010]
7. (i)Design a comparator.
(ii)Design a non-sequential ripple counter which will go through the states 3,4,5,7,8,9,10,3,4…Draw bush
diagram also [Nov2009]
11
9. Design an asynchronous sequential circuit with inputs x1 and x2 and one output z. Initially both the inputs
are equal to 0. When x1 and x2 becomes 1, z becomes 1. When second input also becomes 1, z = 0; The
output stays at 0 until circuit goes back to initial state. [May 2009]
11. a) Develop the state diagram and primitive flow table for a logic system that has 2 inputs, x and y and an
output z. And reduce primitive flow table. The behavior of the circuit is stated as follows. Initially x = y = 0.
Whenever x = 1 and y = 0 then z = 1, whenever x = 0 and y = 1 then z = 0. When x = y = 0 or x = y = 1 no
change in z it remains in the previous state. The logic system has edge-triggered inputs without having a
clock. The logic system changes state on the rising edges of the 2 inputs. Static input values are not to have
any effect in changing the z output. [Dec 2008]
12. (i) What is the objective of state assignment in asynchronous circuit? Give hazard – free realization for the
following Boolean functions f(A, B, C, D) = m(0, 2, 6, 7, 8, 10, 12) (8)
(ii) Summarize the design procedure for asynchronous sequential circuit. (8) [Dec 2008]
13. a).An asynchronous sequential circuit is described by the following excitation and output function
X=(Y1Z1’W2)X +(Y1’Z1W2’)
S=X’
(i) Draw the logic diagram of the circuit
(ii) Derive the translation table and output map
(iii) Describe the behavior of the circuit [May 2008]
14. Explain essential, static and dynamic hazards in digital circuit. Give hazard-free realization for the following
Boolean function .F(I,J,K,L)= S(1,3,4,5,6,7,9,11,15) [May 2008]
15. An asynchronous network has two inputs and one output. The input sequence X1X2=00, 01,11causes the
output to become 1.The next input change then causes the output to return to 0. No other input sequence
will produce a 1 output. Construct the state diagram using primitive flow table. [Dec 2007]
16. i)Give hazard-free realization for the following Boolean function
F(A,B,C,D)=Σm(1,3,6,7,13,15)
ii) Summarize the design procedure for asynchronous sequential circuit. [May 2007]
17. An asynchronous sequential circuit is described by the following excitation and output function
Y=X1X2+(X1+X2)Y &Z=Y
18. a)Draw the fundamental mode Asynchronous circuits and explain in detail
b)Define the following terms.
i) Critical-race
iii)Hazards
c) Draw waveform diagram, total state diagram, primitive flow table for designing the circuit [May 2006]
20. What are the two types of asynchronous circuits? Differentiate between them. [Nov 2005]
21. Discuss on Hazards and Races [Nov 2005]
22. Design a asynchronous sequential circuit with 2 inputs X and Y and with one output Z whenever Y is 1,
input X is transferred to Z.When Y is 0,the output does not change for any change in X. use SR latch for
implementation of the circuit. [May 2005]
23. Write notes on asynchronous sequential circuits and VHDL [Nov 2004]
24. What is a merger graph .How itis used to reduce states in the incompletely specified table [May 2004]
25. What are the problems in asynchronous circuits and what are essential hazards and static hazards how it
can be eliminated? [Nov 2003]
26. Explain the meaning of Mealy machines and Moore machines [May 2003]