8rf Esd Guide

CMOS8RF/CMRF8SF ESD Reference Guide
CMOS8RF(CMRF8SF) ESD Reference

Guide
Date: 04/15/05
DocumentHistory:
Design Manual Reference Date ESD Design Kit Version/Date ESD Reference Guide Date
ES #57P9006 EC# H96317 05/24/04 Fixed layout version 10/16/03 04/15/05
© IBM Corporation, 2005. All rights reserved. Page 1 of 148

Version Date: April 2005 IBM Confidential
This Document May be Obsolete

The reader is responsible to verify that this document is the most current version.
Document Distribution, Availability, and Ownership

Distribution of this ESD Reference Guide is restricted. This document is IBM Confidential. This
ESD Reference Guide may not be copied or transferred to anyone without permission from the
IBM ESD and Latchup team located at IBM’s Burlington, Vermont site.
For internal to IBM customers, please visit http://rfweb.btv.ibm.com/ or access this document in
the CMRF8SF Design Kit.
For external IBM customers, please send a email to fdrytech@us.ibm.com to ensure you have the
latest version of the ESD Reference Guide.

General Information
The main purpose of this reference guide is to provide designers with information on the
CMOS8RF/CMRF8SF ESD Protection information beyond that which is currently available in
other documentation (see “Additional References” below).
Document Revision History Change List

Major changes over the previous version are provided in the following list. Bars at the right-hand
side are given for REFERENCE ONLY. These bars generally refer to the changes made over the
previous version, but review the document carefully for any sections pertinent to your needs.
Table 1. Documentation Revision History
April, 2005 1st edition of the ESD reference guide
Scope
This documentation contains the following types of information:
• ESD Phenomena and Test Methods
• ESD Protection Strategy Background
• ESD Device Physics
• ESD Design Kit Description
• ESD Design Kit Data
• ESD Relevant Technology Data
• ESD Compact Models
• ESD Groundrule Descriptions
• ESD Design Review
• ESD Design Guidelines
Additional References
Other ESD information can also be found in the following sources:
• Technology Design Manual
• Technology Model Reference Guide

ELECTROSTATIC DISCHARGE (ESD)

PROTECTION IN CMOS8RF/CMRF8SF
IBM Systems and Technology Group
1
IBM Confidential
15 Jan 03
IBM Confidential © 2003 IBM Corporation
This document describes ESD protection in IBM’s CMOS8RF/CMRF8SF technology.

Contents
Outline.....................................................................................................8
ESD Phenomena and Test Methods .....................................................9
ESD Events ............................................................................................................................... 10
Human Body Model.................................................................................................................. 11
Machine Model ......................................................................................................................... 12
Charged Device Model ............................................................................................................. 13
Transmission Line Pulse (TLP) ................................................................................................ 14
ESD Protection Level Targets and Requirements .................................................................... 15
ESD Model Standard Specifications......................................................................................... 16
ESD Protection Strategy Background................................................17
ESD Protection Strategy ........................................................................................................... 18
Typical Protection Circuit Topology – Double Diode Network............................................... 19
Typical Protection Circuit Topology – ESD NFET.................................................................. 20
ESD Protection Strategies......................................................................................................... 21
I/O Categories ........................................................................................................................... 22
Generic Signal Pad ESD Architecture ...................................................................................... 23
Diode-based Self Protecting ESD Strategy for Non-Mixed Voltage Applications .................. 24
Diode-based Non-Self Protecting ESD Strategy for Non-Mixed Voltage Applications.......... 25
Diode String-based Non-Self Protecting ESD Strategy for Mixed Voltage or Hot Pluggable
Applications .............................................................................................................................. 26
NMOS/Lnpn-based Non-Self Protecting ESD Strategy for Mixed-voltage and Hot pluggable
applications ............................................................................................................................... 27
NMOS-based Self Protecting ESD Strategy............................................................................. 28
Power Supply Pad ESD Architecture ....................................................................................... 29
Bus Architecture for Multiple Power Supplies......................................................................... 30
Bus Architecture for Multiple Power Supplies......................................................................... 31
ESD Devices between Power Domains .................................................................................... 32
Ground-to-Supply Discharge .................................................................................................... 33
Supply-to-Supply Discharge..................................................................................................... 34
RC-Triggered Power Clamps.................................................................................................... 35
Grounded Gate Silicide-blocked NFET Power Clamp............................................................. 36
Bus-to-bus ESD Devices........................................................................................................... 37
CDM Sensitivity ....................................................................................................................... 38
Basic CDM Protection .............................................................................................................. 39
CDM Protection Strategies ....................................................................................................... 40
ESD Device Physics ..............................................................................41
Devices of interest..................................................................................................................... 42
Resistors.................................................................................................................................... 43
Interconnects ............................................................................................................................. 44
P+/NW Diodes .......................................................................................................................... 45
P+/NW Diode Strings ............................................................................................................... 47
N+/SX Diodes........................................................................................................................... 50
Silicide blocked NMOS ............................................................................................................ 53

ESD Design Kit Description ................................................................55

ESD Design Kit (Fixed layout version) .................................................................................... 56
ESD Full Design Kit (PCell version)........................................................................................ 76
ESD device set in cmrf8sf library............................................................................................. 77
ESD Design Kit Data............................................................................78
P+/NW Diodes data .................................................................................................................. 79
String P+/NW Diodes data ....................................................................................................... 84
3-String P+/NW Diodes data .................................................................................................... 85
5-String P+/NW Diodes data .................................................................................................... 89
N+/SX Diodes data ................................................................................................................... 93
ESD NFETs data....................................................................................................................... 96
1.2V ESD NFETs data.............................................................................................................. 97
2.5V ESD NFETs data............................................................................................................ 100
1.2V Silicided RC-triggered Power Clamp data..................................................................... 103
ESD Relevant Technology Data ........................................................106
Additional ESD diode data ..................................................................................................... 107
Interconnects ESD data........................................................................................................... 114
ESD Compact Models ........................................................................115
ESD Device Models................................................................................................................ 116
ESD Groundrule Descriptions ..........................................................117
ESD Layout Rules................................................................................................................... 118
HBM Rules – Protection Devices ........................................................................................... 119
HBM Rules – Wiring Guidelines............................................................................................ 120
HBM Rules - Lateral Parasitic Devices .................................................................................. 121
HBM Rules – FETs Connected to Pads.................................................................................. 122
ESD OP Rules – FETs Connected to Pads ............................................................................. 123
CDM Rules ............................................................................................................................. 124
ESD Ground Rule Checking................................................................................................... 125
Net Definitions for ESD Ground Rule Checking ................................................................... 126
ESD Design Review ............................................................................127
ESD Design Review ............................................................................................................... 128
Recommended process............................................................................................................ 129
Obtaining the ESD Design Kit................................................................................................ 130
Obtaining the ESD Design Kit................................................................................................ 131
Requesting ESD Design Review ............................................................................................ 132
ESD Design Review Check List Form ................................................................................... 133
Review Check List file information........................................................................................ 134
ESD Design Guidelines ......................................................................135
Need for ESD protection devices............................................................................................ 136
Digital Input/Receiver protection ........................................................................................... 137
Digital Output/Driver protection............................................................................................. 139
RF/High speed circuit protection ............................................................................................ 141
Power Supply protection......................................................................................................... 142
E-Fuse Fsource pad protection................................................................................................ 143

Most common mistakes .......................................................................................................... 145

Avoid Connecting Thin-oxide Gates Directly to Power Supplies .......................................... 146
Avoid Wiring NFET Source and Substrate/Pwell to Different Ground Domains.................. 147
Minimize the Discharge Path Resistance................................................................................ 148
List of Figures
Figure 1: HBM equivalent circuit and waveform ......................................................................... 11
Figure 2: MM equivalent circuit and waveform ........................................................................... 12
Figure 3: CDM equivalent circuit and waveform ......................................................................... 13
Figure 4: TLP test setup................................................................................................................ 14
Figure 5: Typical double diode based ESD protection circuit...................................................... 19
Figure 6: Typical NFET based ESD protection circuit................................................................. 20
Figure 7: Diode-based self protecting ESD strategy..................................................................... 24
Figure 8: Diode-based non-self protecting ESD strategy ............................................................. 25
Figure 9: Diode string-based non-self protecting ESD strategy ................................................... 26
Figure 10: NMOS-based non-self protecting ESD strategy ......................................................... 27
Figure 11: NMOS-based self protecting ESD strategy................................................................. 28
Figure 12: Bus architecture for multiple power supplies.............................................................. 30
Figure 13: Bus architecture for multiple power supplies.............................................................. 31
Figure 14: ESD devices between power domains......................................................................... 32
Figure 15: Ground to supply discharge......................................................................................... 33
Figure 16: Supply to supply discharge.......................................................................................... 34
Figure 17: Typical RC-triggered power clamp circuit.................................................................. 35
Figure 18: Grounded gate silicide-blocked NFET power clamp .................................................. 36
Figure 19: Bus to bus ESD protection devices ............................................................................. 37
Figure 20: CDM sensitivity .......................................................................................................... 38
Figure 21: Basic CDM protection methodology........................................................................... 39
Figure 22: Equivalent circuit and cross-section of an ESD P+/NW diode ................................... 45
Figure 23: Equivalent circuit and cross-section of an ESD P+/NW diode string......................... 47
Figure 24: Cross-section of an ESD P+/NW diode and equivalent circuit of an ESD P+/NW three
diode string............................................................................................................................ 49
Figure 25: Equivalent circuit and cross-section of an ESD N+/SX diode.................................... 50
Figure 26: Equivalent circuit and cross-section of an ESD N+/SX diode.................................... 52
Figure 27: Typical characteristics, equivalent circuit and cross-section of an ESD silicide-
blocked NMOS ..................................................................................................................... 53

Outline
• ESD Phenomena and Test Methods
• ESD Protection Strategy Background
• ESD Device Physics
• ESD Design Kit Description
• ESD Design Kit Data
• ESD Relevant Technology Data
• ESD Compact Models
• ESD Groundrule Descriptions
• ESD Design Review
• ESD Design Guidelines

12
IBM Confidential
15 Jan 03
Outline
We begin with an overview of various Electrostatic Discharge (ESD) phenomena and test
methods, followed by a background section on the different ESD protection strategies employed.
This is followed by detailed explanation of device characteristics for each of the ESD devices. A
detailed documentation of the devices offered in the ESD Design Kit is followed by test data
from these devices. This is followed by a brief description of the ESD device compact models.
The next section provides an overview of the ESD design groundrules. This is followed by a
section on the ESD design review process. The last section is about ESD design guidelines -
which documents the layout and circuit aspects that are essential to be considered for good ESD
results.
ESD is an important consideration in chip design and needs to be developed from the initial
stages of the design process. Considering ESD as a last minute addition often causes problems
of unsatisfactory ESD protection or degraded chip performance.
All pins – even high speed or sensitive analog pins – must have ESD protection. Low ESD
protection causes packaging, test fallout and product failures in the field. Months of engineering
effort, failure analysis, and partitioning experiments in manufacturing are consumed trying to
understand failure of parts, only to potentially trace the problem back to ESD vulnerability.

ESD Phenomena and Test Methods
2
IBM Confidential
15 Jan 03
ESD Phenomena and Test Methods
This section describes the various ESD events and the test methods.

ESD Events
Characteristics HBM MM CDM
Equivalent Circuit 1.5k + 100pF in series
0.5-1.0uH + 200pF in Field plate to chip
series capacitance only
Discharge Path Between ANY two pins Between ANY two One pin only (Discharge
pins Pin)
Simulates Human discharging Metal tool Charged chip
through chip discharging through discharging to ground
chip
Discharge Exponential Decay 11-16 MHz damped ~1 Ghz damped
Waveform Time Const = 150ns Oscillation Oscillation
On-Chip stress Lowest Current and Intermediate Current, Highest Current,

characteristics Voltage, longest Voltage and duration Voltage and shortest
duration duration
I(HBM)=V(HBM)/
1500 Ohms
Failure Thermal failures: Junction damage, Gate oxide damage and
Mechanisms MOSFET snapback, Interconnect fusing, interconnect damage
Interconnect fusing, gate oxide damage
gate oxide damage
IBM Confidential
Table 1: ESD Events
ESD Events
ESD is a high current event that can affect chips at various stages of processing and/or handling.
The general category of ESD covers a number of different discharges that a chip may experience.
There are 3 primary ESD models considered in the microelectronics industry: Human Body
Model (HBM), Machine Model (MM) and Charged Device Model (CDM). Most chips have
specified requirements and/or targets for protection levels to these various models. The basic
characteristics of each event are mentioned in the table above, and will be described further in
the following pages.

Human Body Model (HBM)

• Represents discharge between 2 pins on
an IC from a charged human body
1.5 k
• Characteristics:
VHBM – Relatively slow (rise time 5-10ns,
100 pF pulse width ~150ns)
– Unidirectional current ~ 1-3A
2000 V HBM Current Waveform
– IHBM = VHBM/1.5k [example:
2kV HBM = 1.3A current]
– Electrically looks like a current
source
• Typical IC Testing
– Positive and negative polarity from
each pin to each power and ground
supply
– Positive and negative polarity
between all power and ground
supplies.
– Positive polarity between
representative pairs of signal pins
• IBM wafer test setup limited to 4kV
IBM Confidential
Figure 1: HBM equivalent circuit and waveform
Human Body Model
The slide above describes the characteristics of the HBM ESD event. As the name implies, this
model was developed to represent a human discharging across two pins in an IC. The equivalent
circuit for HBM is a 1.5kΩ resistor in series with a 100pF capacitor as shown in Figure 1: HBM
equivalent circuit and waveform. The capacitor is charged to the specified ESD voltage, and
then the switch is closed and the current flows through the Device Under Test (DUT). An HBM
ESD event occurs between any two pins on a module. HBM is the longest ESD event of the
three primary models, but it has the lowest current. Specialized ESD testers equipped with the
appropriate resistor and capacitor network are used to apply an HBM stress to a module to
determine its robustness. HBM can be done at wafer level on individual structures during
technology development, and at module level for product chip qualification.
The HBM data that is included later in this document comes from a wafer level HBM tester.

Machine Model (MM)

0.5H
VMM
• Represents a discharge onto an IC from a
charged machine tool
200 pF
• Characteristics
– Rapid event
200 V MM Current Waveform – Additional series inductance (0.5-
1.0uH) in equivalent ckt not shown
– High currents (~3 – 5A)
– 200V MM = 2.8-3.8A (allowed tester
range per JEDEC spec)
– Bidirectional -- current oscillates into
and out of the pin.
• Typical IC Testing
– Similar to HBM
IBM Confidential
Figure 2: MM equivalent circuit and waveform
Machine Model
Similar to HBM, the MM ESD event occurs across any two pins on a module. MM however,
simulates a tool discharging across the two pins. This event is more rapid than HBM and has a
higher current level. The waveform is also quite a bit different – the MM wave form is a bi-
directional damped oscillation. The test procedure for MM is similar to HBM, but the MM is
represented by a capacitor in series with an inductor as shown in Figure 2: MM equivalent
circuit and waveform.

Charged Device Model (CDM)

CDM Tester • Represents the discharge through a single
pin of a module that has been charged via
the triboelectric effect (frictional charging)
or by an external field
• Test can be in a fixture (socketed) or with

bare module (non-socketed)
– IBM favors non-socketed because it
more closely replicates actual
conditions.
500 V CDM Current Waveform
• Characteristics
– Very rapid event (rise time ~ 100s of
ps, duration 1-2ns).
– High currents (1-2A / 100V CDM vs.
66mA / 100V in HBM).
– Module capacitance in the range of 1-
20pF
• Typical Test Regimen

– Charge module positive, then
negative, discharging from each pin
• Repeat at higher voltage
IBM Confidential
Figure 3: CDM equivalent circuit and waveform
Charged Device Model
Unlike HBM and MM, CDM ESD events only involve a single pin on the module. Modules can
develop charge through triboelectric (frictional) effects. When this occurs, unless a high
resistive path is used to discharge the module, it may be exposed to a CDM ESD event. The
CDM event charges a chip and then discharges to ground out of a single pin. CDM is a very
high current event, but occurs in a very short time interval. CDM testing is generally
accomplished only on completed chips. A field plate is used to impose a specified charge on the
module, and then a probe with a low resistance path to ground drops down on a single pin to
discharge the module. This procedure is repeated for each pin on the module, and a functional
test is employed after CDM stressing is completed to determine if the module has been damaged.

Transmission Line Pulse (TLP)

Uses a square wave pulse to measure the
high current I-V characteristics of wafers or
modules
High-Current
Pulse Source Oscilloscope
Characteristics
500 MHz
– Rise time 5-10ns range
– Width set at 100ns for HBM simulation,
Current evaluating 30ns for MM simulation
Probe – ITLP is measured directly from setup
Commercial
source or
charged Enables determination of I/O pad voltage at
coaxial cable. high currents similar to an ESD event
Micromanipulator – HBM is more like "black box", but TLP
(wafer level) gives insight into physics of what is
happening
– HBM pulse is a 150ns decaying
Voltage exponential with <10ns rise time
Probe – IHBM = VHBM/1.5k , thus 2kV ~ 1.3A
Device
Under Test
IBM Confidential
Figure 4: TLP test setup
Transmission Line Pulse (TLP)
TLP testing is a newer test model than the ESD models described previously, and is generally
not a required stress for a product qualification. The main use of TLP is to develop current-
voltage relationships for semiconductor devices and circuits under ESD like conditions. Device
operation under the high current and short duration of an ESD event can be significantly
different than normal functionality. TLP is used extensively for analyzing discrete devices at
wafer level during technology development activities, and most of the results that will be
presented in the sections that follow are from TLP testing on devices in this technology. The
basic concept of TLP testing is applying a square wave to the DUT and measuring the current
through and voltage across the device. Different pulse widths can be used to simulate different
ESD events. Generally, a 100ns pulse is used to simulate HBM, and a 30ns pulse is being
evaluated for simulating MM. Both of these pulses can be delivered using most of the available
TLP testers. To investigate devices under CDM conditions, an extension to TLP often referred
to as Very Fast TLP (VFTLP) is employed. The pulse width used for a VFTLP tester is typically
between 1ns and 3ns, with rise and fall times on the order of 100ps – 500ps.

ESD Protection Level Targets and Requirements

• HBM and MM use the same ESD structures
• CDM protection uses additional components
• Requirements are set by product owners
• Industry standards are set by JEDEC, MIL Spec, and the ESD Association
ESD Model Industry Standard

Human Body Model 2000V
(HBM)
Machine Model 200V
(MM)
Charged Device 500V
Model (CDM)
IBM Confidential
Table 2: ESD Protection Industry Standard
ESD Protection Level Targets and Requirements
ESD protection levels are generally set by product owners based on how well the environments
where the chips will be handled are controlled and by the requirements of the customers of the
chips. The standard protection levels seen in the industry are recorded in the table above. Some
products require more or some require less protection depending on their specific circumstances.
It is important to understand the required protection levels for a given chip. The ESD
groundrules found in the IBM Design Manuals are based on achieving the industry standard ESD
protection levels as outlined in Table 2: ESD Protection Industry Standard.

ESD Model Standard Specifications

ESD Model Specification
JEDEC JESD22-A114-B
Human Body Model MIL-STD-883E Method 3015.7
(HBM) ESDA STM5.1-1998
JEDEC EIA/JESD22-A115-A 1997

Machine Model (MM) ESDA STM5.2-1999
JEDEC JESD22-C101B.01 2004

Charged Device Model ESDA STM5.3.1-1999
(CDM)
No accepted Standard Exists - Used
Transmission Line primarily for obtaining high current device
characteristics. Pulse width can be varied
Pulse (TLP) to correspond to different ESD models.
For HBM, 100ns pulse width with ~5ns
rise/fall time used at IBM
IBM Confidential
Table 3: ESD Model Standard Specifications
ESD Model Standard Specifications
Included in Table 3: ESD Model Standard Specifications are the JEDEC, MIL specification, and
ESDA standards that describe each of the ESD models. The specifications include detailed
information such as tester calibration and design requirements, and the specification numbers are
included here for reference.

ESD Protection Strategy Background
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IBM Confidential
15 Jan 03
ESD Protection Strategy Background

In this section the ESD protection strategies are described.

ESD Protection Strategy
ESD voltages can exceed the breakdown voltage

of any structure on an integrated circuit
The current will flow through the path(s) of least
resistance
ESD protection provides a preferred discharge
current path designed to carry high currents
The discharge path must carry high current while
developing a low voltage drop or the current will be
re-routed through sensitive circuits
1
IBM Confidential
15 Jan 03
IBM Confidential IBM Confidential © 2003 IBM Corporation
ESD Protection Strategy
The voltage levels that are involved during an ESD event can exceed the highest breakdown
voltage of any device in an advanced silicon technology. The objective is not to prevent current
from flowing, but to redirect it through circuits that have been designed to withstand large
currents without failure. Circuit designers must analyze the various discharge modes – where the
current will enter and leave the circuit with both possible polarities of the discharge – and design
a protection network in which these currents will flow safely. The current will flow through the
path (or paths) of least resistance to ground. The preferred path should not develop large voltage
(IR) drops that would cause current to be redirected through internal circuits.

Typical Protection Circuit Topology – Double

Diode Network
Vdd
“Up” diode typ. Discharge current paths

P+/NW
in a protected design:
Internal Power
I/O Circuitry : Positive Pulse
Clamp
: Negative Pulse
“Down” diode
typ. N+/SX
Gnd
Protection networks require a means of conducting discharge

current from the supply to ground.
The I/O voltage must remain between Vdd and ground (plus one
diode voltage drop) or the diodes become forward-biased.
A 11
string of “up” diodes may be used to tolerate input voltages >Vdd.
IBM Confidential
15 Jan 03
Figure 5: Typical double diode based ESD protection circuit
Typical Protection Circuit Topology – Double Diode Network

One of the most commonly used ESD protection strategies is to use two diodes on the pin, one to
the supply bus and the other to the ground bus. This diagram shows the current paths in the chip
for the four possible discharges between the pin and its supply and ground busses. The power
clamps will be discussed later in more detail, but essentially they are turned off during normal
operation and turn on during an ESD event to provide a very low resistance discharge path.
For a positive pulse with respect to Vdd, the current passes through the upper diode to the supply
pin. For a negative pulse with respect to Vdd, the current enters the supply pin, goes through the
power clamp, and then passes through the diode connected from the pin to ground (some ESD
protection networks utilize parasitic lateral transistor action to conduct the current directly from
Vdd to the pin).
For a positive pulse with respect to ground, the current passes through the upper diode, along the
supply rail to the power clamp, through the clamp, and out the ground pin. For a negative pulse
with respect to ground, the current passes through the lower diode and out the signal pin.
Good ESD results are achieved when the discharge paths are confined to these routes. If the
resistance of the wiring, the power clamp or the protect devices causes the signal pad or Vdd bus
to rise too high in voltage the discharge path may be rerouted through I/O or internal circuitry.
Therefore the discharge path must not only be able to handle the current, it must be able to do so
without allowing large voltages to develop across the parallel circuitry due to I-R effects.
Because the diodes appear as parasitic capacitance on the input/output node, the designer may
have to balance ESD protection against circuit performance.

Typical Protection Circuit Topology – ESD NFET
Vdd
Discharge current paths

in a protected design:
Internal Power
I/O Circuitry : Positive Pulse
Clamp
: Negative Pulse
Down diode
is optional.
Parasitic or
intentional
component.
Gnd
The single device solution depends on a diode between the power supply
and ground to carry current in one of the discharge modes.
The ESD NFET must be a specialized device with blocked silicide regions
on the S/D. The source-substrate junction can carry the negative mode
discharge.
The I/O14voltage can rise above the power supply (to the voltage limit of the
IBM Confidential
ESD NFET)
15 Jan 03without sinking DC current into the signal pin.
Figure 6: Typical NFET based ESD protection circuit
Typical Protection Circuit Topology – ESD NFET
In another typical ESD protection circuit topology, a non-silicided grounded gate NFET device is
used instead of a pair of diodes to carry the discharge current. The grounded gate NFET is a
specialized device in which the silicide is not formed on parts of the source and drain diffusions
enabling the device to have much better current carrying capability than a standard silicided
NFET.
For a positive pulse with respect to Vdd, the current passes through the ESD NFET to the ground
bus, then to the power supply either through the power clamp, an explicit ESD diode in parallel
with the power clamp, or a parasitic diode such as N-well to substrate junctions. For a negative
pulse with respect to Vdd, the current enters the supply pin, goes through the power clamp, and
then passes through either an explicit ESD diode in parallel with the ESD NFET, or through the
parasitic drain-to-substrate junction of the ESD NFET, and out the signal pin.
For a positive pulse with respect to ground, the current passes through the ESD NFET and out
the ground pin. For a negative pulse with respect to ground, the current passes through either an
explicit ESD diode in parallel with the ESD NFET, or through the parasitic drain-to-substrate
junction of the ESD NFET, and out the signal pin.
An advantage of this topology is that the I/O pin can rise above the power supply voltage without
forward-biasing the up diode of the double diode circuit as shown in Figure 5: Typical double
diode based ESD protection circuit.

ESD Protection Strategies

Two types of ESD strategies :
Self protecting
ESD pulse power dissipated by I/O circuit
Device in I/O circuit is designed to handle large
currents, but must also function correctly to meet
performance objectives
Non-self protecting
ESD pulse power dissipated by device not in I/O
circuits
Specific ESD device added in parallel to the I/O
circuits to shunt current away from input or output
2 circuits
IBM Confidential
15 Jan 03
ESD Protection Strategies
In a self protecting ESD strategy the I/O devices themselves are designed to handle the current
during an ESD event, while in a non-self protecting ESD strategy, ESD devices are added in
parallel or in addition to existing I/O devices to divert the current away from the I/O cell devices
during an ESD event.

I/O Categories
Non-Mixed Voltage (NMV) Interface Applications
I/O pad voltage will not exceed Vdd or VddIO
Vdd or VddIO supply will be powered before I/O pad will
receive signals
Mixed Voltage (MV) Interface Applications
I/O pad voltage exceeds Vdd or VddIO
Vdd or VddIO supply will be powered before I/O pad will
receive signals
Hot-Pluggable (HPL) Interface Applications
I/O pad voltage may or may not exceed Vdd or VddIO
Vdd or VddIO supply will NOT be powered before I/O pad
will receive signals
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15 Jan 03
I/O Categories
The ESD protection strategy should be compatible with various I/O categories or interface
applications. In a non-mixed voltage (NMV) interface the I/O pad voltage will not exceed the
power supply and the power supply will be powered before the I/O pad receives any signals. In a
mixed voltage (MV) interface the I/O pad voltage will exceed the power supply and the power
supply will be powered before the I/O pad receives any signals. While in a hot-pluggable (HPL)
interface the I/O pad voltage may or may not exceed the power supply and the power supply will
not be powered before the I/O pad receives any signals.

Generic Signal Pad ESD Architecture

Diode-based self protecting
Parasitic diode in driver NFET and PFET utilized for ESD
protection
Diode-based non-self protecting
Additional ESD diodes added in parallel to the I/O
NFET-based self protecting
Driver NFET designed for ESD protection
NFET-based non-self protecting
Additional ESD NFET added in parallel to the I/O
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15 Jan 03
Generic Signal Pad ESD Architecture
ESD protection on signal pads is typically accomplished by the use of diodes and/or NFETs
which are designed to both handle the ESD current and keep the pad voltage as low as possible
to avoid the turn-on of any other parasitic paths that can lead to failure of other I/O devices
connected to the pad. These diodes and NFETs can be incorporated into the I/O circuit devices
(self protecting strategy) or added in parallel to the I/O circuit devices (non-self protecting
strategy) as will be explained in a later section. The appropriate dimensions for the protection
devices are also described in a later section.

Diode-based Self Protecting ESD Strategy

(Non-Mixed Voltage Applications)
PFET (P+/NW, vpnp) and NFET (N+/SX, diode) are used to clamp pad voltage
SX and NW contacts need to be added to pull-down NFET and pull-up PFET
respectively
Diode key characteristics :
On-resistance (< 1ohm desired)
Current carrying capability (=> 2A => 3KV HBM)

Vdd
Vdd
Input
ESD Power
Clamp
CDM protection Cchip
Vdd
Pre Drive
Circuit
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IBM Confidential HBM Protection
15 Jan 03
Figure 7: Diode-based self protecting ESD strategy
Diode-based Self Protecting ESD Strategy for Non-Mixed Voltage

Applications
In such an ESD protection strategy, the parasitic diodes on the driver PFET and NFET act as
ESD devices during an ESD event. Even though Figure 7: Diode-based self protecting ESD
strategy, shows ESD protection on a bi-directional signal pad, a similar ESD protection strategy
can also be used on a output only signal pad too. The figure also shows the ESD power clamp
which serves as the ESD protection device between Vdd and ground. An additional chip
capacitance between power supply and ground can provide a parallel discharge path. During a
positive ESD zap on the I/O pad, the parasitic drain to nwell contact (P+/NW) diode of the PFET
conducts current to the Vdd bus. Similarly, during a negative ESD zap on the I/O pad, the
parasitic drain to substrate (N+/SX) diode of the NFET conducts current to the Ground bus. A
very crucial requirement for this strategy to work efficiently is the need for robust SX and NW
contacts in the NFET and PFET layouts respectively, as this would be key in determining the on-
resistance of the parasitic diodes.

Diode-based Non-Self Protecting ESD

Strategy (Non-Mixed Voltage Applications)
On-resistance (< 1ohm desired)
Current carrying capability (=> 2A => 3KV HBM)
Vdd Vdd
Vdd
Input
ESD Power Cchip

Clamp
CDM
protection Vdd
Pre-Drive
impedance Circuits
HBM Protection
matching
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Figure 8: Diode-based non-self protecting ESD strategy
Diode-based Non-Self Protecting ESD Strategy for Non-Mixed Voltage

Applications
For I/O pads whose inputs do not exceed a diode voltage above the power supply, the double-
diode network is used. The protect structure is a p-diffusion to nwell (P+/NW) diode tied
between the pad node and Vdd and a n-diffusion to substrate (N+/SX) diode tied between the pad
node and Vss chip substrate. “SX” is a general terminology for p-well which can be formed with
dual well or isolated well. During a positive ESD zap on the I/O pad, the P+/NW diode conducts
current to the Vdd bus. Similarly, during a negative ESD zap on the I/O pad, the N+/SX diode
conducts current to the Ground bus.

Diode String-based Non-Self Protecting ESD Strategy

(Mixed Voltage or Hot Pluggable Applications)
On-resistance (< 1ohm/diode desired)
Current carrying capability (=> 2A ... 3KV HBM)
Cascoded pull-down NMOS driver required with diode strings
Vdd Vdd
Vdd
Input
ESD Power
Clamp
Cchip
CDM
protection Vdd
Pre-Drive
Circuits
impedance
Vdd
matching
HBM Protection
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Figure 9: Diode string-based non-self protecting ESD strategy
Diode String-based Non-Self Protecting ESD Strategy for Mixed

Voltage or Hot Pluggable Applications
For I/O pads whose inputs do exceed a diode voltage above the power supply, a Diode String
ESD circuit is required. The appropriate numbers of diodes are required for hot pluggable
applications. In such an ESD protection strategy the on-resistance of the ESD diodes, the wiring
resistance from the pad to the input of the diodes and the wiring resistance from the output of the
diodes to the power clamp on the power bus are very crucial. This is due to the fact that high
resistances in the ESD discharge path will lead to increased voltage at the pad which in turn
leads to snapback of output driver NFETs.

NMOS/Lnpn-based Non-Self Protecting ESD Strategy

(Mixed-voltage and Hot pluggable applications)
MOSFET-based implementation
Positive mode---snapback/bipolar turn-on occurs
Negative mode--N+ drain/SX diode shunts current to ground
Key parameter--silicide blocking (OP) on NMOS drain and source
Cascoded I/O pull-down NMOS required
Vdd Vdd
Input
ESD Power
Clamp
Cchip
CDM
protection Vdd
Pre-Drive
HBM Protection impedance Circuits
matching Vdd
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Figure 10: NMOS-based non-self protecting ESD strategy
NMOS/Lnpn-based Non-Self Protecting ESD Strategy for Mixed-

voltage and Hot pluggable applications
MOSFETs are commonly used ESD protection devices for self protecting implementations. In
the non-self protecting case the I/O MOSFETs will need to have protection added to guard
against destruction during an ESD event. MOSFETs with silicide-blocking added to the drain
and source will provide effective ESD protection. Silicided MOSFETs are typically not used for
ESD protection since the silicide causes current crowding resulting in localized hot spots further
resulting in failure. In a positive mode ESD event, the ESD current is discharged via the
parasitic lateral n-p-n or p-n-p device in the ESD MOSFET. In a negative mode ESD event, the
n+ (or p+) to P-well (or N-well) parasitic diode in the MOSFET discharges the ESD current.
Cascoded or stacked FETs should be used in the driver circuit so that the ESD MOSFET triggers
at a lower voltage than the stacked driver.

NMOS-based Self Protecting ESD Strategy

MOSFET-based implementation
Positive mode, snapback/bipolar turn-on occurs
Negative mode, N+ drain/SX diode shunts current to ground
Key parameters, silicide blocking (OP or SBLK) on NMOS drain and source
Pull-down NMOS should be single NMOS, not cascoded, no series resistance between pull-
down NMOS and pad
Vdd
Vdd
Input
CDM ESD Power

Vdd Clamp
protection
Cchip
Pre Drive
Circuit
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Figure 11: NMOS-based self protecting ESD strategy
NMOS-based Self Protecting ESD Strategy
In the self protecting implementation, the MOSFET serves a dual role as an ESD protection
device and part of the I/O circuit. Self protecting features can be built into an output driver to
minimize the need for an additional ESD network. These self-protecting features are
recommended even if the plan is to use a separate ESD structure. The key requirements are
sufficient width of the driver to handle ESD events and appropriate dimension of silicide-
blocking on the source and drain of the MOSFET.

Power Supply Pad ESD Architecture

ESD for power supply bus architecture
RC triggered power clamp
Grounded gate Silicide blocked NFET power clamp
Diode strings to ground OR supply to supply
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Power Supply Pad ESD Architecture
In addition to I/O pads, it is also very crucial to protect power supply pins and ground pins
against ESD events. In this section, the various strategies for protecting power supply and ground
pins are discussed. First, the background on the need for ESD protection between various power
supply and ground pins is discussed. This is followed by a detailed description of three
commonly used strategies used for protection between power supply and ground pins. The three
common strategies used for this protection are the RC-triggered power clamp, the grounded-gate
silicide-blocked NFET and diode strings.

Bus Architecture for Multiple Power Supplies
Logic Vdd Analog Vcc

!?
Logic ESD ESD

Analog
Circuitry Power Power
Circuitry
Clamp Clamp
!?
Logic Gnd Analog Gnd
Unconnected power
and ground domains
Desired Path
will lead to poor ESD
Undesired Path results in discharges
17 between domains.
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15 Jan 03
Figure 12: Bus architecture for multiple power supplies
Consider a chip with two separate power supply and ground domains. Each power supply
domain has the required ESD devices and power clamps. For simplicity, the CDM protection
network in these schematics is ignored and assumed to be incorporated into the LOGIC circuitry
blocks.
This circuit will exhibit good ESD performance as long as the discharges do not cross supply
domain boundaries. Conversely, if a discharge occurs between the logic I/O pin and the ground
of the analog domain the device will fail at low voltage. The desired discharge current path is
shown by the light colored arrows. The undesired path is shown by the dark colored arrows. The
current enters the logic I/O pin and follows the forward-biased “up” diode to the logic power
supply. From that point the only path to the analog ground bus is through the logic circuitry,
along the connection between the logic circuitry and the analog circuitry, and then to the logic
ground. Since none of these paths are designed for high current, the failure voltage will be
unacceptably low.
Power and ground domains without explicit ESD protection paths in both positive and negative
polarities will lead to poor ESD performance.

Logic Vdd Optional Analog Vcc

ESD
Device
Logic ESD ESD

Analog
Circuitry
Clamp Clamp
Required
ESD
Logic Gnd Device Analog Gnd
Desired Path
Undesired Path
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Figure 13: Bus architecture for multiple power supplies
This slide shows the corrected version of Figure 12: Bus architecture for multiple power
supplies and the resulting discharge current path for a discharge between supply domains. This
design connects the ground domain with an ESD device.
The current enters the I/O pin and travels to the LOGIC Vdd bus. The power clamp in the
LOGIC supply domain conducts the current to the LOGIC ground bus and the added ESD device
allows that current to flow to the logic ground bus. The designer may also add an ESD device
between the power supply buses as shown by the box bounded by dashed lines.

ESD Devices between Power Domains

ESD devices may be placed between power domains to increase
the effectiveness of power clamps by connecting them in parallel.
ESD
Device
Logic ESD ESD

Analog
Circuitry
Clamp Clamp
Required
ESD
Desired Path
Undesired Path
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Figure 14: ESD devices between power domains
ESD Devices between Power Domains
From the previous Figure 13: Bus architecture for multiple power supplies, it is clear that an
ESD path can be provided by connecting only the ground busses with an ESD device. Additional
advantage may be gained by placing an ESD device between power supply busses. As shown in
Figure 14: ESD devices between power domains, the added ESD device provides a second path
to the logic domain and allows the power clamps to operate in parallel.
If a power domain is connected to another domain through an ESD device the power clamp on
one of the domains can be omitted, though having a power clamp on each domain is the
preferred approach.
It should be noted that the ESD path shown in these figures correspond to ESD events of one
polarity. ESD devices should also be present in the circuit to discharge ESD events of the other
polarity.
Power up sequencing and leakage should be considered in all cases.

Ground-to-Supply Discharge

ESD
Device
Logic ESD ESD

Analog
Circuitry
Clamp Clamp
Required
ESD
Desired Path
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Figure 15: Ground to supply discharge
Ground-to-Supply Discharge
ESD can also occur between ground domains. The above slide illustrates the motivation for
adding the diodes in parallel with the power clamps.
Current introduced into the ground pin has many possible paths to the power supply. Parasitic
junctions in the internal logic circuitry would provide many of these paths. However, the
discharge should not be routed through these parasitic junctions since they are generally not
designed to conduct large currents. A more robust path is formed by the double diode network on
all of the logic I/O pins. The difficulty is how to get the discharge current to flow primarily in
this preferred path. There are at least two diodes in series – more if diode strings are used in
place of the “up” diode – competing with the parasitic junctions in the internal circuitry. Once
the ground-to-supply voltage rises to force a significant current through the double diodes, a
large fraction of the discharge current will flow through the parasitic junctions in the internal
circuits.
The solution is to add a set of diodes in parallel with the power clamps as shown. These provide
a conduction path to the supply bus with both low built-in voltage and low resistance. Since the
diode capacitance is not harmful on the power supply bus, the diodes can be large without
impacting chip performance. An N+/SX diode would normally be used in this application.
Some power clamps conduct efficiently in the reverse direction in which case this additional
diode can be embodied in an existing element. Otherwise it should be added as an explicit
component.

Supply-to-Supply Discharge

ESD
Device
Logic ESD ESD

Analog
Circuitry
Clamp Clamp
Required
ESD
Desired Path
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Figure 16: Supply to supply discharge
Supply-to-Supply Discharge
The final mode to consider is a supply-to-supply discharge. The current flow is shown in the
schematic diagram in Figure 16: Supply to supply discharge.
First consider the case where there is no device between the Vdd and the Vcc power supply
busses. The discharge current path will be through the logic supply power clamp, the logic
ground-to-analog ground ESD device, then to the logic Vdd. The situation in the analog supply
domain is similar to a ground-to-supply discharge. Note that the majority of the current is
conducted through the diode in parallel with the power clamp.
If the optional ESD device is added between power supply busses, the path will have lower total
resistance and less voltage will be developed on the logic Vdd bus.
ESD protection MUST exist between supply or rail busses when the busses are wired out off-
chip to external pins for disconnected power grid topologies where no current path exists
between all chip pads to the disconnected power rail. It has been shown that supply-supply ESD
protection circuits improves pin-to-supply protection levels and allows for pin-pin ESD testing.
Use the double diode, diode string, non-silicided NMOS and/or RC-triggered power clamp
specific designs without modifications. Back-to-back configurations to establish bi-directional
current paths and maintain noise isolation needs can be achieved using the specific designs. It is
the responsibility of the designer to determine the number of diodes necessary for noise,
sequencing requirements and burn-in qualification.

RC-
RC-Triggered Power Clamps
Vdd
R1 Big NFET
INV1 INV2 INV3
R2
C
yRC network used to keep NFET off during normal operation but device on
during the transient pulse of the ESD event
yNFET must be wide enough to provide a low-resistance shunt to ground
under ESD conditions
IBM Confidential
Figure 17: Typical RC-triggered power clamp circuit
ESD protection structures used from Vdd power supply pad to ground pad are often referred to
as power supply clamps. These power clamps provide a current path from power supply pad to
ground pad during various ESD events. The simplest form of RC-triggered power clamp is
shown in Figure 17: Typical RC-triggered power clamp circuit where the RC network is
designed such that the NFET remains off during normal operation and turns on during an ESD
event. This circuit should be simulated with discrete devices available in the technology, to
determine power-up leakage and Vdd noise leakage through the NFET. The NFET should also
be wide enough to handle the ESD current when it is on during an ESD event.

Grounded Gate Silicide-blocked NFET Power

Clamp
Pad NFET with silicide blocking on source and drain

Silicide blocking Silicide blocking does not extend across gate
Drain Lateral NPN during a positive ESD event on the supply pad.
Drain to p-well parasitic diode discharges during a negative
Gate
ESD event on the supply pad
Substrate
Source
Silicide blocking
Gnd
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Figure 18: Grounded gate silicide-blocked NFET power clamp
Grounded Gate Silicide-blocked NFET Power Clamp
Another power clamp that can be used between a power supply pad and a ground pad is the
grounded gate silicide-blocked NFET power clamp. This device works in exactly the same way
as the silicide-blocked NFET ESD device used on I/O pads as described back in Figure 10:
NMOS-based non-self protecting ESD strategy. The grounded gate NFET operates as a lateral
NPN during a positive ESD event and during a negative ESD event, the drain to p-well parasitic
diode discharges current to the ground. This device can be effective for protecting the power
supply itself, but generally is not the correct choice if ESD diodes from signal pins terminate on
this power supply.

Bus-to-bus ESD Devices
Anti-parallel diodes are typically used Asymmetrical arrangements couple

as bus-to-bus ESD devices. power supplies of differing voltages or
power supply and ground.
GND A GND B
VDD x VDD y or
VDD x > (VDD y or GND)
GND
Large transient signals can be blocked by

placing diodes in series.
Rule of thumb: If there are n diodes
in series, they should be n times
GND A GND B
larger than if there were only a
single diode.*
There is a trade-off between ESD performance and noise isolation. While difficult to
quantify beforehand, this can be factored into prototype experiments.
* If diode strings are protecting cascoded NFETs, using larger diodes is less critical.
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Figure 19: Bus to bus ESD protection devices
Bus-to-bus ESD Devices
The ESD devices connecting power supplies and grounds are simply various configurations of
anti-parallel diodes. The most straightforward arrangement is shown in the upper left: two diodes
connected in parallel with opposite polarity. Use the asymmetrical circuit in the upper right when
connecting power supplies with different voltages. The number of diodes in series is chosen to
prevent current from flowing between power supplies. If one of the power supplies or ground
buses has large transient signals diodes may be placed in series as shown in the schematic on the
lower left side of the page. When diodes are wired in series, the on-resistance of the series string
can become so large as to develop harmful voltages across the circuitry being protected. This can
be avoided by increasing the diode perimeter for the individual diodes in series strings. As a
general rule of thumb, use n times the diode perimeter if you wire n diodes in series. This is most
important when the device is protecting single NFETs as they will be destroyed if the voltage
exceeds the snap-back voltage.
Cascoded NFETs are less vulnerable because the snap-back voltage of the series pair is higher
than a single device. The presence of ESD devices between power supplies will influence power
supply sequencing requirements for the design. If one domain is unpowered the ESD device will
conduct current from the powered to the unpowered domain. Of course, generally the reason why
the supplies are separated is to alleviate noise or crosstalk concerns. The junction capacitances of
ESD diodes re-couple the buses to some degree; there will be a trade-off between ESD
performance and isolation.
CDM Sensitivity
In the 8RF technology, CDM is a dominant ESD problem.
To understand why, examine a CDM discharge in the earlier circuit implementation.
Module Vdd
charged to
negative -
RON 1Ω
voltage 10-20V
+ Add’l
I/O Internal Power
10-20A
Circuits & Clamp
DCAPs
*
Probe
GND
* Also note that the diode to Large voltage

ground suffers breakdown. Not develops across Thinner gates = Increased sensitivity.
typical of HBM discharges. the gate oxide.
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Figure 20: CDM sensitivity
CDM Sensitivity
In a CDM discharge, the entire chip is charged to a voltage and then discharged through a single
pin. The slide above shows a circuit diagram which emphasizes the fact that the HBM circuit
itself is not sufficient to provide CDM protection.
The device under test contains a CMOS receiver connected to the I/O pin, followed by additional
circuitry. The HBM protection diodes are present, as is the power clamp. Consider the module
charged to a negative voltage and then discharged through the I/O pin. If the module is
unpowered, all buses and devices start at the same potential. The current flowing into the pin has
two paths to charge the chip; through the “up” diode to the supply bus, or in the reverse direction
through the “down” diode to the ground bus. The preferred path is the through the “up” diode. A
very robust HBM diode has an on-resistance of about 1 Ω. The CDM current is in the range of
10 to 20 A, which develops a voltage of 10-20 V between the I/O pin – also the MOSFET gate –
and the power supply/ground busses. This voltage will be large enough to force some current
through the reverse-biased “down” diode, but more critically, it will break down the gate oxide
and destroy the receiver. Hence, HBM protection itself is clearly not adequate for CDM events.

Basic CDM Protection
Avoids large
voltage across the
gate oxide.
Module Vdd
charged to
- RON 3Ω
negative
RON 1Ω
voltage 10-20 V
+ Add’l
I/O Internal Power
10-20A + Circuits & Clamp
200Ω DCAPs
~.30 V
Probe
-
GND
The CDM double diode network

(This neglects the differential charging of Vdd may optionally be replaced by a
and ground as well as bus resistances, but this is grounded-gate ESD NFET.
the concept.) 15
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15 Jan 03
Figure 21: Basic CDM protection methodology
Basic CDM Protection
CDM protection is achieved by adding a voltage divider between the I/O pin and the MOS gates.
This is implemented by a series resistor and another set of ESD devices. The resistor should be
larger than 50 Ω. In normal operation the resistor is in series with the input impedance of the
receiver and the load capacitance of the additional ESD devices and does not significantly affect
the speed of the gate. Consider the same scenario as the previous slide where the module is
charged to a negative voltage and discharged through the I/O pin. As before, a large voltage
develops between the pin and the power supply and ground busses, but the resistor and the
forward-biased “up” diode divide this voltage based on the proportion of the resistor value and
the diode on-resistance.
This illustration neglects some of the effects such as the resistance of the power and ground
buses.

CDM Protection Strategies

Diode-based non-self protecting
ESD CDM diodes added in parallel to the gate
NFET-based non-self protecting
ESD CDM NFET added in parallel to the gate
CDM Resistors need to be added in between the ESD

HBM protection device the ESD CDM protection device
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CDM Protection Strategies
ESD CDM protection can be achieved either by using a diode-based strategy or a NFET-based
strategy. In a diode-based CDM protection strategy, appropriate sized CDM diodes and CDM
resistor are connected to the gate as shown in Figure 21: Basic CDM protection methodology. In
a NFET-based CDM protection strategy, appropriate sized CDM NFETs and a CDM resistor are
connected to the gate in a similar way. The appropriate dimensions for the CDM protection
devices are described in a later section.

ESD Device Physics
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ESD Device Physics

Devices of interest
Resistors
OP P+ Poly Resistor
Interconnects
Contacts, Vias and Metal wires
ESD Diodes
P+/NW Diode or P+/NW/SX PNP
N+/SX Diode
ESD NFET
Silicide blocked NMOS
ESD RC Power Clamp
RC triggered Silicided NFET
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Devices of interest
During an ESD event, devices enter high current regimes not encountered during normal
operation. The high-current characteristics may in some cases be very different than the low
current characteristics, and in some cases it may even be a parasitic device which turns on during
high currents. The high current characteristics of devices such as resistors, interconnects, diodes,
NFETs and power clamps which most commonly encounter these high current regimes are
reviewed in the upcoming sections.
Transmission Line Pulse (TLP) testing is performed as was described in an earlier sub-section
Transmission Line Pulse. TLP data shown in upcoming sections uses a pulse widths of either
100ns or 30ns with rise and fall times close to 5ns.

Resistors
OP P+ Poly Resistor
Resistor must be sized to handle ESD events and should
be well contacted
The specified value of CDM resistors as per the
groundrules should be used
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Resistors
The OP P+ Poly resistor is used to handle ESD events. It is also used as a CDM resistor. These
resistors should be sized as per the groundrules specified in the Design Manual.

Interconnects
Wires
Vital that the metal wires that connect the pad to the ESD
protection device be able to handle ESD events
Each metal used in the design should be wide enough to
meet the ESD groundrules
Additionally, metal wiring must be large enough so as not
to add significant resistance to the ESD discharge path
Contacts and Vias
Sufficient number of contacts and vias should connect the
diffusions of the ESD device to the metal wires and metal
wires to each other, respectively
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Interconnects
All interconnects such as wires, contacts and vias that connect the ESD protection device to the
pad, should be designed to handle ESD events.

P+/NW Diode (PNP to Vdd)
P+/NW Diode to Vdd Pad

VPNP to SX
Gnd
Vdd
p+ n+ p+ n+ p+
c P-well N-well P-well

Vdd
b
e p-
p-n-p
Pad
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Figure 22: Equivalent circuit and cross-section of an ESD P+/NW diode
P+/NW Diodes
In bulk technologies, STI-bounded or poly-bounded diodes consisting of P+/NW and N+/SX

exist. STI-bounded diodes are recommended instead of poly-bounded diodes due to increased
capacitance of poly-bounded diodes. The diode has four regions of operation: reverse bias region,
weak forward bias region, forward bias region and strong forward bias region.
When P+/NW diodes are used in bulk CMOS technologies, there is a parasitic PNP bipolar
junction transistor inherent to the structure. This PNP can be either a vertical or lateral PNP.
Depending on the β of this PNP, current may flow not only through the P+/NW diode, but also to
the substrate through the PNP. The above slide shows a cross-section of the P+/NW diode
including the parasitic PNP. The amount of leakage to the substrate depends on the β of the
parasitic PNP (β=Ic/Ib, where Ic=ISubstrate and Ib=INwell). The β of this device is dependent upon
the process (NWell doping, STI depth, and source/drain design). The perimeter of the diode and
the parasitic wiring in the structure determines the series on-resistance and therefore the clamp-
ing effectiveness of the diode.

P+/NW Diode (PNP to Vdd)
Advantages
Low capacitive loading

Competitive area consumption
Low on-resistance due to NWell Rs remaining low, leads to improved
clamping of pad voltages during ESD event
Disadvantages
Device also operates as a vertical PNP, injects holes into SX.
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P+/NW Diode String (PNP to Vdd)
P+/NW Diode String to Vdd

P+ SX contacts should be connected to Ground
Pad Vdd
p+ n+ p+ n+ p+ n+ p+ n+
NWell NWell
p-
Two-diode string shown

Diode string when zapping positive from pad to Vdd
Darlington amplifier creating with series diodes when zapping positive
and referencing ground
31
Majority of current injected into substrate
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15 Jan 03
Figure 23: Equivalent circuit and cross-section of an ESD P+/NW diode string
P+/NW Diode Strings
P+/NW diode strings (multiple diodes connected in series) are commonly used for ESD
protection devices. The slide above shows a cross-section of a series connection of a diode
string. The cross section shown is for (2) series diodes.

Advantages
Low capacitive loading
Low on-resistance due to NWell Rs remaining low, leads to improved
clamping of pad voltages during ESD event. SCR typically forms from first
P+/NW/SX/NW GR and/or P+/NW/SX/N+ (down diode)
Disadvantages
Darlington amplifier - typically => 50% current goes to substrate at lower
currents - drives SX contact area
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P+/NW diode strings create a Darlington transistor
network that directs most of the current through the
substrate at low currents
At high currents, β roll-off reduces this effect
Three Diode String
Pad
N+ P+ N+ P+ P+
N+
STI
P+
RN-WELL N+
N-Well
NWELL N+
Vdd P+
P- WAFER
Substrate
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Figure 24: Cross-section of an ESD P+/NW diode and equivalent circuit of an ESD P+/NW
three diode string
As was described, a diode string is formed by series connection of P+/NW diodes. Along with
the series diodes, a Darlington amplifier is formed which is shown in Figure 24: Cross-section of
an ESD P+/NW diode and equivalent circuit of an ESD P+/NW three diode string. The
Darlington amplifier can cause significant substrate current to be generated and only a small
percentage of the current injected at the input may actually come out of the output terminal. The
remaining goes to the substrate. The exact amount of current going to the substrate once again
depends on the parasitic PNP beta. The bipolar gain rolls off rapidly with increasing current.
This effect will be most pronounced at low currents because of the beta roll-off with current
density.
A cross-section of the P+/NW diode (PNP transistor) is also shown in the slide above. The anode
is the p+ region in the center which is placed in an N-well. The N-well contact forms a ring
around the anode. Because the P+/NW and N-well/substrate junctions are in close proximity,
bipolar action is observed and a portion of the current entering the p+ anode is injected into the
substrate. The substrate contact forms a ring around the N-well to capture this current and
prevent the local substrate voltage from rising. Only one side of the substrate contact is shown.

N+/SX Diode (Diode to Ground)
N+/SX Diode to Ground

Lateral n-p-n formed with N-well guardring that surrounds the device
β typically much less than 1 Pad
Vdd
Gnd
Vdd
n+ p+ n+ p+ n+
c
N-well P-well N-well
b
e n-p-n
p-
Pad
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Figure 25: Equivalent circuit and cross-section of an ESD N+/SX diode
N+/SX Diodes
Another type of diode which can be used is the N+/SX diode. The cross section of the N+/SX
diode is shown in the slide above.

N+/SX Diode (Diode to Ground)
Advantages
Low capacitive loading - can't easily get any lower capacitance than
a STI bounded diode in CMOS processes
Competitive area consumption
35
IBM Confidential
15 Jan 03

N+/SX Diode
Diodes are much more robust in the forward direction than the
reverse.
Diode RON is higher in the reverse direction
An N-well guard ring is required to collect injected electrons
Minority carriers in p-substrate can cause latch-up if not collected
Diode RON and robustness are determined by perimeter rather
than area
Guard ring (Vdd) Cathode Guard ring (Vdd)

Anode
N+ P+ N+ P+ N+
STI
N-WELL N-WELL
P- WAFER
36
IBM Confidential
15 Jan 03
Figure 26: Equivalent circuit and cross-section of an ESD N+/SX diode
A cross-sectional diagram of the N+/SX diode is shown in this chart. The center stripe is the
cathode. The anode connection to the substrate is made by a substrate contact ring around the
cathode. The entire structure is surrounded by an N-well guard ring to collect electrons that are
injected by the n+ cathode under forward bias. In normal operation, the anode is grounded, the
N-well guard ring is connected to Vdd and the cathode is connected to the I/O pin.
Diodes are far more tolerant of ESD pulses in the forward direction than in the reverse direction.
Recall that an ESD discharge can be considered as a current source. The joule heating of the
diode will be proportional to the product of the discharge current and the voltage developed
across the diode. The differential or on-resistance of the diode is much higher in the reverse
direction. This causes more heating within the diode itself and endangers other circuits because
of the large voltage developed across the diode.

The ESD NMOS layout must have silicide blocking between source and
drain contacts and poly.
Silicide blocking should give the device enough on-resistance to have
voltage at sustaining/holding climb back above trigger voltage (for
effective width utilization)
Source Gate Drain
SOP DOP
It2 n+
n+
IDS (A)
VG=0 P-well
Vsus Vt1
VDS (V) SOP and DOP : Source and Drain Silicide Blocking
38
IBM Confidential
15 Jan 03
Figure 27: Typical characteristics, equivalent circuit and cross-section of an ESD silicide-
blocked NMOS
The NMOS device has a parasitic lateral NPN bipolar (Lnpn) beneath it which can be seen in
cross-section in the slide above. The Lnpn turns on when large drain/source biases (Vds) are
encountered. The NMOS conducts the current until Vds reaches what is known as the trigger
voltage (Vt1) as shown in slide above. Once the bipolar turns on a stable state is reached which
is commonly referred to as the holding/sustaining voltage. The bipolar turn-on is a non-
destructive event as long as the current is limited below what is commonly referred to as the
thermal runaway current (It2). A similar lateral bipolar is observed on the PMOS. For the PMOS
the device goes into snapback when Vds sees a large negative voltage. In the case of the PNP,
negative voltages at the drain cause electrons generated to go to the nwell and holes end up at the
silicon surface.

Advantages
High voltage tolerant for mixed voltage and hot plug
applications
Disadvantages
Higher capacitive loading compared to diode-based protection
strategy
39
IBM Confidential
15 Jan 03

CMOS8RF/CMS8RFG ESD Reference Guide
ESD Design Kit Description
IBM Confidential
ESD Design Kit Description

The intent of the ESD kit is to provide graphics for ESD protection elements based on
ESD characterization results acquired during the technology development timeframe.
There are two flavors of the ESD kit depending upon the technology being designed in,
some technologies have both flavors of the kit :
1.Fixed layout version of the ESD Design Kit - Includes graphics (GL1 or GDS format).
The documentation of elements in this kit is provided in this ESD Reference Guide in
the upcoming pages.
2.Pcell version of the ESD Design Kit – Included in the Full Design Kit. The
documentation of elements in this kit is provided in the Design Kit User’s Guide.
Updated versions of these kits are released on a periodical basis.

CMRF8SF ESD
Design KIT
(Fixed layout version)

10/16/2003 Release
For further information, please contact fdrytech@us.ibm.com
IBM Confidential
ESD Design Kit (Fixed layout version)

Revision History
y6/13/01
yNW/SX diodes converted to N+/SX diodes
yMetal layout refinements
y7/27/01
yP+ width of N+/SX diode increased to 2um
yCA's added within 10um apart on SX guard ring
y01/25/02
yAddedESDIODE layer on all P+/NW diodes
yAddedSX guard rings around each diode in diode strings
yAdded levels to define Nets for ESD checking
y10/21/02
yRemoved Laser Fuse protection diode
yChanged Guard ring layout
y11/21/02
yDiode fingers fully strapped with metal
y10/16/03
yAll structures streamed out from 8RF pcells and required corrections done
yNon-silicided HBM and CDM NFET’s added to kit
yPower Clamps added to kit
IBM Confidential
When an updated version of the kit is released, the changes are documented here. This
enables designers to decide whether they need to update any designs using elements from
a previous version of the kit.

ESD Design Kit Elements

yCMRF8SF ESD design kit contains the following types of structures :
HBM Devices (Signal Pads or Power Supplies)
• Double Diodes
• 2-String Diodes
• 3-String Diodes
• 5-String Diodes
• 1.2V and 2.5V Silicide-Blocked ESD NFETs
CDM Devices (Signal Pads or Low-Capacitance Supplies with Gates Connected)
• Double Diodes
• 1.2V and 2.5V Silicide-Blocked ESD NFETs
RC-Triggered power clamps (Power Supplies)
y 1.2V Power Clamps
y 1.5V Power Clamps
yPlease note that this kit is meant to serve as an addendum to the standard 8SF ESD Design Kit.
The structures in this kit are specifically designed for lower capacitance on pads that need to have
high frequency capability, and will not necessarily provide an ESD protection level that is as high as
standard ESD structures. On pads where high frequency capability is not required, it is advisable
to choose structures from the standard 8SF ESD kit.
IBM Confidential
Since the ESD protection strategy used by a designer is based on a particular circuit
design and protection requirement, numerous ESD protection structures are provided in
the ESD Design Kit. The common structures provided are diodes, silicide-blocked
NFETs and RC-triggered power clamps. Both HBM/MM protection structures and CDM
protection structures are provided.

Prime Cell
y Cell Name: “CMRF8SF_DESIGN_KIT"
y Prime cell that contains all the structures included in ESD design kit
y 50 elements included to help with I/O and ESD design
y Following pages gives descriptions of the elements of design kit.
y For each device, elements are included with required and recommended
groundrules perimeters/widths.
IBM Confidential
The prime cell is a top level cell containing all the discrete ESD structures available in
the kit.

Double Diodes (HBM)
Vdd
yP+/NW and N+/SX Double Diodes
NW
y1 P+/NW Diode to Vdd and 1 N+/SX Diode to Ground
yP+/NW Diode perimeters: > 220 um
P+
yN+/SX Diode perimeters: > 110um
yNwell and Substrate Guardrings for latchup protection
Pad N+
yESDIODE level drawn where required
yESDUMMY level drawn where required around device
yFor use with 60um and 80um I/O pitches
SX
yCan be used under wirebond pads
Gnd
IBM Confidential
A single P+/NW diode and a single N+/SX diode, connected as shown in the schematic
above, is referred to as a “Double Diode”. These Double Diodes of various perimeters
are provided for use on a pad. These devices have the required guardrings for latchup
protection. They also have the required dummy level (ESDUMMY in this case) around
the structures to enable proper DRC on them.

String Diodes (HBM)

Vdd
NW

y2, 3 or 5 P+/NW Diode to Vdd and 1 N+/SX Diode to Ground
yP+/NW Diode perimeters: >220 um
yN+/SX Diode perimeters: >110 um
yNwell and Substrate Guardring for latchup protection
yESDIODE level drawn where required
P+
yCan be used under wirebond pads
Pad N+
SX
Gnd
IBM Confidential
Two or more P+/NW diodes and a single N+/SX diode, connected as shown in the
schematic above, is referred to as a “Diode String”. A diode string having 2 P+/NW
diodes is referred to as a “2-String Diode”, while a diode string having 3 P+/NW diodes
is referred to as a “3-String Diode”. These diode strings of various perimeters are
provided for use on a pad, depending on the required voltage tolerance on the pad. These
devices have the required guardrings for latchup protection. They also have the required
dummy level (ESDUMMY in this case) around the structures to enable proper DRC on
them.

Silicide-Blocked NFETs (HBM)
y1.2V and 2.5V ESD NFET

Pad yNFET with silicide blocking on Source and Drain
yNFET Width = 200um, 400um and 600um
Drain
yDrain OP width = 3.0um for 1.2V NFET
Gate
Substrate ySource OP width = 0.44um
yOP does not extend across gate
Source
ySBLK drawn where required
yConnections labeled on design for Input, Ground, Gate and
NW Guard ring
Gnd yRecommended use: As a self-protecting I/O device
yNot for use under wirebond pads
IBM Confidential
An alternative ESD protection strategy involves the use of ESD HBM silicide-blocked
NFETs for ESD HBM protection on the pads. In certain circuit configurations, this
approach is the most favorable one, as the ESD discharge path is now directly from the
pad to ground. Silicide-blocking is employed on the source and drain side to provide
ballasting resistance and ensure uniform current flow. The dimensions of the silicide-
blocking are dependent on the device type. These devices have the required guardrings
for latchup protection. They also have the required dummy level (ESDUMMY in this
case) around the structures to enable proper DRC on them.

Double Diodes (CDM)
Vdd
NW
y1 P+/NW Diode to Vdd and 1 N+/SX Diode to Ground
yP+/NW Diode perimeters: 25 um and 50um
P+
yN+/SX Diode perimeters: 25 um and 50um
yResistor (needs to be added) connects between pad and I/O
InputN+gate input gate oxide
yNwell and Substrate Guardring for latchup protection
yESDIODE drawn where required
SX
yESD_CDM level drawn where required around device
Gnd yFor use with 60um and 80um I/O pitches
IBM Confidential
CDM Double Diodes, similar in configuration to HBM Double Diodes perimeters are
provided for use on a gate that is being protected. The appropriate CDM resistor, as
required by the ESD groundrules, also needs to be added between the pad and the
junction of the CDM double diode. These devices have the required guardrings for
latchup protection. They also have the required dummy level (ESD_CDM in this case)
around the structures to enable proper DRC on them.

Silicide-Blocked NFETs (CDM)

y1.2V and 2.5V ESD NFET
yNFET with silicide blocking on Source and Drain
Input Gate yNFET Width = 25um and 50um
yResistor (needs to be added) connects between pad and I/O
Drain
input gate oxide
Gate
Substrate
ySource OP width = 0.44um
Source yOP does not extend across gate
ySBLK drawn where required
yGate, Source and Substrate are shorted.
yConnections labeled on design for Input, Ground, Gate and
Gnd NW Guard ring
yRecommended use: As a self-protecting I/O device
yESD_CDM level drawn where required around device
IBM Confidential
An alternative ESD CDM protection strategy involves the use of silicide- blocked NFETs.
The appropriate CDM resistor, as required by the ESD groundrules, also needs to be
added between the pad and the junction of the CDM NFET. In certain circuit
configurations, this approach is the most favorable one, as the ESD discharge path is now
directly from the gate to ground. Silicide-blocking is employed on the source and drain
side to provide ballasting resistance and ensure uniform current flow. The dimensions of
the silicide-blocking are dependent on the device type. These devices have the required
guardrings for latchup protection. They also have the required dummy level (ESD_CDM
in this case) around the structures to enable proper DRC on them.


Vdd
R1 Big NFET
INV1 INV2 INV3
R2
C
y 1.2V and 2.5V RC-Triggered Power Clamp

y Big NFET: Width=2000um and 4000um
y Capacitance (C): W/L= (2040/1)um
y Resistor (R1) : PFET; W/L=(0.36/1.2)um
y Resistor (R2) : P+OP Resistor ; W/L=(1/12)um= 6k ohms
yINV1: NFET Width=2um, PFET Width= 96um
yINV2: NFET Width=21.84um, PFET Width= 12um
yINV3: NFET Width=15.09um, PFET Width= 101.85um
IBM Confidential
An efficient way to provide ESD protection between the power supply and ground pads,
is to use an ESD RC-triggered power clamp. These power clamps are offered for use on
various voltage power buses. A power clamp with the appropriate NFET width should be
used, such as to maintain the I/O pad voltage below the snapback or gate breakdown
voltage of the devices connected to the I/O pad.

Double Diodes (HBM)

Device Name Diode Finger Parallel Series Parallel
Perimeters Length vpnp vpnp ndsx
(P+/NW / (um) diodes diodes diodes
N+/SX)
(um)
DBL_HBMDIO_P220_L55 220/110 55 2 1 1
*(MRFDBL_DIO_220)
DBL_HBMDIO_P330_L55 330/110 55 3 1 1
(MRFDBL_DIO_330)
DBL_HBMDIO_P282_L35 282/210 35 4 1 3
DBL_HBMDIO_P440_L55 440/110 55 4 1 1
(MRFDBL_DIO_440)
DBL_HBMDIO_P496_L35 496/210 35 7 1 3
DBL_HBMDIO_P660_L55 660/110 55 6 1 1
(MRFDBL_DIO_660)
DBL_HBMDIO_P708_L35 708/210 35 10 1 3
*Name used in previous version of the device in the previously released kit
IBM Confidential
These structures are the previously described ESD HBM Double Diodes (P+/NW and
N+/SX). Certain details of each of the structures are documented above. Some of these
details include (1) the total perimeter of the P+/NW diode and the N+/SX diode, (2) the
length of each of the finger, (3) the number of parallel fingers or diodes, that make up the
P+/NW diode, (4) the number of P+/NW diodes in series (1 in the case of Double Diodes)
and (5) the number of parallel fingers or diodes that make up the N+/SX diode. These
dummy level (ESDUMMY in this case) around the structures to enable proper DRC on
them.

2-String Diodes (HBM)

N+/SX)
(um)
2STR_HBMDIO_P220_L55 220/110 55 2 2 1
(MRFDIODE_2_STRING_220)
2STR_HBMDIO_P354_L35 354/210 35 5 2 3
2STR_HBMDIO_P330_L55 330/110 55 3 2 1
2STR_HBMDIO_P496_L35 496/210 35 7 2 3
2STR_HBMDIO_P440_L55 440/110 55 4 2 1
2STR_HBMDIO_P708_L35 708/210 35 10 2 3
2STR_HBMDIO_P660_L55 660/110 55 6 2 1
IBM Confidential
These structures are the previously described ESD HBM 2-String Diodes ((2) P+/NW
and (1) N+/SX)). Certain details of each of the structures are documented above. Some
of these details include (1) the total perimeter of the P+/NW diode and the N+/SX diode,
(2) the length of each of the finger, (3) the number of parallel fingers or diodes, that make
up the P+/NW diode, (4) the number of P+/NW diodes in series (2 in the case of 2-String
diodes) and (5) the number of parallel fingers or diodes that make up the N+/SX diode.
These devices have the required guardrings for latchup protection. They also have the
required dummy level (ESDUMMY in this case) around the structures to enable proper
DRC on them.


N+/SX)
(um)
3STR_HBMDIO_P220_L55 220/110 55 2 3 1
3STR_HBMDIO_P354_L35 354/210 35 5 3 3
3STR_HBMDIO_P330_L55 330/110 55 3 3 1
3STR_HBMDIO_P496_L35 496/210 35 7 3 3
3STR_HBMDIO_P440_L55 440/110 55 4 3 1
3STR_HBMDIO_P708_L35 708/210 35 10 3 3
3STR_HBMDIO_P660_L55 660/110 55 6 3 1
IBM Confidential
These structures are the previously described ESD HBM 3-String Diodes ((3) P+/NW
and (1) N+/SX)). Certain details of each of the structures are documented above. Some
of these details include (1) the total perimeter of the P+/NW diode and the N+/SX diode,
(2) the length of each of the finger, (3) the number of parallel fingers or diodes, that make
up the P+/NW diode, (4) the number of P+/NW diodes in series (3 in the case of 3-String
DRC on them.


N+/SX)
(um)
5STR_HBMDIO_P220_L55 220/110 55 2 5 1
5STR_HBMDIO_P354_L35 354/210 35 5 5 3
5STR_HBMDIO_P330_L55 330/110 55 3 5 1
5STR_HBMDIO_P496_L35 496/210 35 7 5 3
5STR_HBMDIO_P440_L55 440/110 55 4 5 1
5STR_HBMDIO_P708_L35 708/210 35 10 5 3
5STR_HBMDIO_P660_L55 660/110 55 6 5 1
IBM Confidential
These structures are the previously described ESD HBM 5 String Diodes ((5) P+/NW and
(1) N+/SX)). Certain details of each of the structures are documented above. Some of
these details include (1) the total perimeter of the P+/NW diode and the N+/SX diode, (2)
the length of each of the finger, (3) the number of parallel fingers or diodes, that make up
the P+/NW diode, (4) the number of P+/NW diodes in series (5 in the case of 5 string
DRC on them.

1.2V Silicide-Blocked NFETs (HBM)

Device Name Width Length No. of Y- SX NW Ring Width
(um) (um) Fingers Repetition Ring (um)
Width
(um)
1V2_W200_DOP3_HBM_60B 25 0.12 8 1 1 1
1V2_W400_DOP3_HBM_60B 25 0.12 16 1 1 1
1V2_W600_DOP3_HBM_60B 25 0.12 24 1 1 1
1V2_W200_DOP3_HBM_80B 25 0.12 4 2 1 1
1V2_W400_DOP3_HBM_80B 25 0.12 8 2 1 1
1V2_W600_DOP3_HBM_80B 25 0.12 12 2 1 1
IBM Confidential
These structures are the previously described ESD HBM silicide-blocked NFET that can
be fit in a 60um wide and 80um wide I/O cell. Certain details of each of the structures are
documented above. Some of these details include (1) the width of each NFET finger, (2)
the gate length of each of the finger, (3) the number of parallel fingers that make up the
silicide-blocked NFET and (5) the number of number of repetition in the y-direction.
DRC on them.

2.5V Silicide-Blocked NFETs (HBM)

Device Name Width Length No. of Y- SX NW Ring
(um) (um) Fingers Repetition Ring Width (um)
Width
(um)
2V5_W200_DOP5_HBM_60B 25 0.24 8 1 1 1
2V5_W400_DOP5_HBM_60B 25 0.24 16 1 1 1
2V5_W600_DOP5_HBM_60B 25 0.24 24 1 1 1
2V5_W200_DOP5_HBM_80B 25 0.24 4 2 1 1
2V5_W400_DOP5_HBM_80B 25 0.24 8 2 1 1
2V5_W600_DOP5_HBM_80B 25 0.24 12 2 1 1
IBM Confidential
These structures are the previously described ESD HBM silicide-blocked NFET that can
be fit in a 60um wide and 80um wide I/O cell. Certain details of each of the structures are
documented above. Some of these details include (1) the width of each NFET finger, (2)
the gate length of each of the finger, (3) the number of parallel fingers that make up the
silicide-blocked NFET and (5) the number of number of repetition in the y-direction.
DRC on them.

Double Diodes (CDM)

Perimeters Length vpnp vpnp ndsx diodes
(P+/NW / (um) diodes diodes
N+/SX)
(um)
DBL_CDMDIO_P25_L12 25/25 12.5 1 1 1
DBL_CDMDIO_P50_L25 50/50 25 1 1 1
IBM Confidential
These structures are the previously described ESD CDM Double Diodes (P+/NW and
N+/SX). Certain details of each of the structures are documented above. Some of these
details include (1) the total perimeter of the P+/NW diode and the N+/SX diode, (2) the
length of each of the finger, (3) the number of parallel fingers or diodes, that make up the
P+/NW diode, (4) the number of P+/NW diodes in series (1 in the case of Double Diodes)
and (5) the number of parallel fingers or diodes that make up the N+/SX diode. These
dummy level (ESD_CDM in this case) around the structures to enable proper DRC on
them.

1.2V Silicide-Blocked NFETs (CDM)

Device Name Width Length No. of Y- SX Ring NW Ring
(um) (um) Fingers Repetition Width Width (um)
(um)
1V2_W25_DOP3_CDM 25 0.12 1 1 1 1
1V2_W50_DOP3_CDM 25 0.12 2 1 1 1
IBM Confidential
These structures are the previously described ESD CDM silicide-blocked NFET. Certain
details of each of the structures are documented above. Some of these details include (1)
the width of each NFET finger, (2) the gate length of each of the finger, (3) the number of
parallel fingers that make up the silicide-blocked NFET and (5) the number of number of
repetition in the y-direction. These devices have the required guardrings for latchup
protection. They also have the required dummy level (ESD_CDM in this case) around the
structures to enable proper DRC on them.

2.5V Silicide-Blocked NFETs (CDM)

Device Name Width Length No. of Y- SX Ring NW Ring
(um) (um) Fingers Repetition Width (um) Width
(um)
2V5_W25_DOP5_CDM 25 0.24 1 1 1 1
2V5_W50_DOP5_CDM 25 0.24 2 1 1 1
IBM Confidential
These structures are the previously described ESD CDM silicide-blocked NFET. Certain
the width of each NFET finger, (2) the gate length of each of the finger, (3) the number of
parallel fingers that make up the silicide-blocked NFET and (5) the number of number of
repetition in the y-direction. These devices have the required guardrings for latchup
protection. They also have the required dummy level (ESD_CDM in this case) around the
structures to enable proper DRC on them.


Device Name NFET Capacitor Resistor width P+OP
Width width (um) (um) Resistor
(um) (k-ohm)
1V2_RC_CLAMP_W2000_A 2000 2040 0.36 6
1V2_RC_CLAMP_W4000_A 4000 2040 0.36 6
2V5_RC_CLAMP_W2000_A 2000 2040 0.36 6
2V5_RC_CLAMP_W4000_A 4000 2040 0.36 6
IBM Confidential
These structures are the previously described ESD RC-triggered power clamp. Certain
the total width of the NFET, (2) the capacitance value of the capacitor in the RC network,
(3) the resistance value of the resistor in the RC network and (4) the resistance value of
the P+OP resistor. These devices have the required guardrings for latchup protection.

CMRF8SF ESD
Full Design KIT
(PCell version)

05/11/2005 Release (Tentative future release)
For further information, please contact fdrytech@us.ibm.com
IBM Confidential
ESD Full Design Kit (PCell version)
Pcell version of ESD devices are included in the Full Design Kit. A brief introduction to
the devices in this kit is provided in the upcoming page of this reference guide.

ESD device set in cmrf8sf library

Device and circuit Device Description
Name
esdndsx N+/SX ESD Diode
esdvpnp P+/NW/SX ESD PNP
sblkndres OP resistor for ESD NFETs
double_diode_n ESD Double diode and ESD diode strings for IO pads
antiparallel_diodes ESD diodes for Power/Ground pads
esdnfet ESD Thin-oxide NFETs for IO pads
esddgnfet ESD Thick-oxide (DG) NFETs for IO pads
rc_clamp ESD Thin-oxide RC Power Clamps for Power pads
rc_clamp25 ESD Thick-oxide (DG) RC Power Clamps for Power pads
Further detailed information is provided in the CMRF8SF Process Design Kit

User’s Guide – Cadence Device Library (cdslib) Component, which can be
downloaded from IBM Customer Connect
https://www-306.ibm.com/servlet/oem/edge/index.jsp
IBM Confidential
ESD device set in cmrf8sf library
The ESD devices offered in the Full Design Kit are (1) esdndsx – a pcell for N+/SX ESD
diode, (2) esdvpnp – a pcell for P+/NW/SX ESD PNP, (3) sblkndres – a pcell for OP
resistor for ESD NFETs, (4) double_diode_n – a pcell for ESD Double diode and ESD
diode strings for IO pads, (5) antiparallel_diodes – a pcell for ESD diodes for
power/ground pads, (6) esdnfet – a pcell for ESD thin-oxide NFETs for IO pads, (7)
esddgnfet – a pcell for ESD thick-oxide (DG) NFETs for IO pads, (8) rc_clamp – a pcell
for ESD thin-oxide RC Power clamp for power pads and (9) rc_clamp25 – a pcell for
ESD thick-oxide (DG) RC Power clamp for power pads.
Detailed documentation of each of these pcells and the variable design parameters for
each of them is provided in the Design Kit User’s Guide.

ESD Design Kit Data
6
IBM Confidential
15 Jan 03
ESD Design Kit Data
The slides in this section of the ESD Reference Guide will discuss the Transmission Line
Pulse (TLP) test results of the ESD Kit elements.

P+/NW Diodes
IBM Confidential
P+/NW Diodes data

P+/NW Diodes (Finger Height: 25um) - 100ns TLP
• 8RF P+/NW diode perimeter requirement ground rule has been set at 220um
IBM Confidential
P-Cell Name: esdvpnp
This slide shows a comparison of the 100ns TLP characteristics of a P+/NW diode with
various perimeters. ESD diodes in the fixed layout version of the ESD Design Kit (Fixed
layout version) are offered with RX finger lengths of 35um and 55um for use in I/O
blocks with different form factors. As indicated on the slide, the data shown above
corresponds to a diode design with RX finger length of 25um. The P+/NW diodes are
typically connected between the I/O pad and Vdd rail. The failure current for P+/NW
diodes with 300um perimeter is approximately 2.3A. The on-resistance of the diode is
typically extracted in the 1 to 2A current range. The BEOL interconnects contribute to
the overall on-resistance of the diode. The on-resistance decreases with increasing diode
perimeter.

IBM Confidential
The 100ns TLP data shown in the slide above corresponds to P+/NW diode of various
perimeters with an RX finger length of 55um. The failure current of the 330um perimeter
diode is > 3.5A. The reason for the higher failure current and lower on-resistance of a
P+/NW diode with RX finger length of 55um compared to the 25um finger length
(shown in the previous slide) is evident from the diode layout. A longer diode RX finger
length enables more number of V1’s, V2’s and wider M2 metal lines to connect RX
fingers; therefore there is lower parasitic resistance and a higher current handling
capability.

IBM Confidential
various perimeters. The 30ns TLP data corresponds to the MM model. It can be noted
that the 30ns TLP failure current is higher than the 100ns TLP failure current for the
same device.

IBM Confidential
various perimeters. The 30ns TLP data corresponds to the MM model. It can be noted
that the 30ns TLP failure current is higher than the 100ns TLP failure current for the
same device. Again, diodes with larger RX finger length, have a higher failure current
than diodes with smaller RX finger length.

String P+/NW Diodes
IBM Confidential
String P+/NW Diodes data
The ESD devices offered in the kit include 2-String P+/NW Diodes, 3-String P+/NW
Diodes and 5-String P+/NW diodes. The following pages show data for these String
diodes.

3-String P+/NW Diode (Finger Height: 25um) - 100ns TLP
IBM Confidential
P-Cell Name: double_diode_n
3-String P+/NW Diodes data
The above slide shows a comparison of the 100ns TLP characteristics of a 3-String
P+/NW diode with different perimeters. ESD diodes in the ESD Design Kit (Fixed layout
version) are offered with RX finger lengths of 35um and 55um. The data shown above
corresponds to diodes with RX finger length of 25um.

IBM Confidential
P+/NW diode with different perimeters. The data shown above corresponds to diodes
with RX finger length of 55um.

IBM Confidential
The above slide shows a comparison of the 30ns TLP characteristics of a 3-String P+/NW
diode with different perimeters. The data shown above corresponds to diodes with RX
finger length of 25um.

IBM Confidential

• It is strongly recommended not to use 5-String P+/NW Diode as this leads to a very high pad voltage
during a positive ESD event between IO pad and ground
IBM Confidential
5-String P+/NW Diodes data
P+/NW diode with different perimeters. ESD diodes in the ESD Design Kit (Fixed layout
version) are offered with RX finger lengths of 35um and 55um. The data shown above
corresponds to diodes with RX finger length of 25um. It is strongly recommended not to
use the 5-String P+/NW diode as the voltage drop across this device during a positive
ESD event between IO pad and ground, leads to a very high pad voltage. This high pad
voltage in turn can cause the driver NFET to snapback and conduct current, possibly
leading to its failure.

IBM Confidential
P+/NW diode with different perimeters. The data shown above corresponds to diodes
with RX finger length of 55um.

IBM Confidential

IBM Confidential

N+/SX Diodes
IBM Confidential
N+/SX Diodes data

N+SX Diode (Finger Height: 55um) - 100ns TLP
• 8RF N+/SX diode perimeter requirement ground rule has been set at 110um
IBM Confidential
P-Cell Name: esdndsx
The above slide shows a comparison of the 100ns TLP characteristics of an N+/SX
(N+/PW) diode with various perimeters. ESD diodes in the ESD Design Kit (Fixed
layout version) are offered with RX finger lengths of 35um and 55um for use in I/O
blocks with different form factors. As indicated on the slide, the data shown above
corresponds to a diode design with RX finger length of 55um. The failure current for the
N+/PW diode with 220um perimeter is approximately 2.0A. The on-resistance of the
diode is extracted in the 1 to 2A current range.

N+SX Diode (Finger Height: 55um) - 30ns TLP
IBM Confidential
P-Cell Name: esdndsx
The 100ns TLP data shown in the slide above corresponds to N+/SX diode of various
perimeters with an RX finger length of 55um. The failure current of the 220um perimeter
diode is ~ 3.0A. It can be noted that the 30ns TLP failure current is higher than the 100ns
TLP failure current for the same device.

ESD NFETs
IBM Confidential
ESD NFETs data
This section discusses the 100ns TLP characteristics of 1.2V and 2.5V ESD NFETs.

1.2V ESD NFETs
IBM Confidential
1.2V ESD NFETs data

1.2V Silicide-Blocked ESD NFET - 100ns TLP
• Groundrule requirement for 1.2V ESD NFET: W=200um (width~1/2 gate perimeter), DOP=3.00um,
SOP=0.44um
IBM Confidential
P-Cell Name: esdnfet
The 100ns TLP characteristics of multi-finger 200um, 400um and 800um wide dual well
1.2V ESD NFETs is shown in the slide above. The groundrules require a 3.0um drain OP
width and 0.44um source OP width for a 1.0V ESD NFET. The trigger voltage (Vt1) of
the NFETs is ~4.0V and the holding voltage is also ~4.0V.

IBM Confidential
P-Cell Name: esdnfet
1.2V ESD NFETs is shown in the slide above. It can be noted that the 30ns TLP failure
current is higher than the 100ns TLP failure current for the same device.

2.5V ESD NFETs
IBM Confidential
2.5V ESD NFETs data

• Groundrule requirement for 2.5V ESD NFET: W=200um (width~1/2 gate perimeter), DOP=5.00um,
SOP=0.44um
IBM Confidential
P-Cell Name: esddgnfet
The above slide shows the 100ns TLP characteristics of W=200um, 400um and 800um
2.5V ESD NFETs. The groundrules require a 5.0um drain OP width and 0.44um source
OP width for a 2.5V ESD NFET. The trigger voltage (Vt1) and holding voltage of the
NFETs is ~6.0V and ~5.0V respectively.

IBM Confidential
P-Cell Name: esddgnfet
2.5V ESD NFETs is shown in the slide above. It can be noted that the 30ns TLP failure
current is higher than the 100ns TLP failure current for the same device.

1.2V Silicided RC-triggered Power

Clamp
IBM Confidential
1.2V Silicided RC-triggered Power Clamp data

1.2V Silicided RC-triggered Power Clamps - 100ns TLP
IBM Confidential
P-Cell Name: rc_clamp
The above slide shows the 100ns TLP characteristics of 1.2V Silicided RC-triggered
Power Clamp with various widths and RC constants. It can be noted the Power Clamp
turns on at ~0.5V.

1.2V Silicided RC-triggered Power Clamps - 30ns TLP
IBM Confidential
P-Cell Name: rc_clamp
The above slide shows the 30ns TLP characteristics of 1.2V Silicided RC-triggered
Power Clamp with various widths and RC constants. It can be noted the Power Clamp
turns on at ~0.5V.

ESD Relevant Technology Data
IBM Confidential
ESD Relevant Technology Data

P+/NW Diode - Junction Breakdown - 100ns TLP
• The reverse breakdown voltage is approximately 11V
IBM Confidential
Additional ESD diode data
The above slide shows the 100ns TLP reverse bias breakdown characteristics of P+/NW
diodes with various perimeters. The breakdown voltage and failure current of a 550um
perimeter (RX finger length of 25um) P+/NW diode is 11V and ~0.2A respectively. This
indicates that during a negative mode ESD event, if the pad voltage rises to 11V, the
diode connected to the Vdd rail (i.e., P+/NW diode) will breakdown and will be able to
handle ~0.2A (for a 550um perimeter).

P+/NW Diode - Junction Breakdown - 30ns TLP
IBM Confidential
The above slide shows the 30ns TLP reverse bias breakdown characteristics of P+/NW
diodes with various perimeters.

P+/NW/PW BJT, β vs. Icol - DC Data
• Current gain β(=Ic/Ib) of P+/NW/PW is a useful parameter to characterize diode performance

• β decreased sharply for collector currents larger than a 1mA
IBM Confidential
The P+/NW diode connected between an I/O pad and the Vdd rail is actually a vertical p-
n-p BJT with the collector being the substrate guardring connected to ground. The plot of
β vs. Ic, where β (=Ic/Ib) is the common emitter current gain and Ic is the collector current,
for a p-n-p BJT is useful since it provides information on the amount of current being
injected into the substrate for a given emitter current. The β roll off at large collector
currents is due to high level injection effects. The peak common emitter current gain for
the P+/NW diodes is ~1.4.

P+/NW/PW BJT - β vs. Icol - 100ns TLP Data
• Plot characterizes β behavior at higher Ic than previous plot

• Plot indicates that at high currents, P+/NW/PW BJT mainly behaves as a P+/NW diode
IBM Confidential
The previous page shows the plot of β vs. Ic using DC signals at low collector current
densities; the above plot of β vs. Ic is extracted from 100ns TLP measurements. The low
β value at high current densities indicates that, the bipolar action is small and the vertical
p-n-p BJT behaves as a diode for large emitter currents.

3-String P+/NW/PW Diode/BJT, β vs. Icol - DC Data
• β of a 3-String diode is higher than a single diode at low currents, but drops rapidly at higher collector
currents
IBM Confidential
The above slide shows the DC β vs. Ic plot for a 3-String P+/NW diode. The higher peak
β for a string diode (~13) compared to a single diode (~1.4) is due to the Darlington
amplification effect.

5-String P+/NW/PW Diode/BJT, β vs. Icol - DC Data
IBM Confidential
The above slide shows the DC β vs. Ic plot for a 5-String P+/NW diode. The higher peak
β for a string diode (~80) compared to a single diode (~1.4) is due to the Darlington
amplification effect.

P+/NW Diode - DC Leakage Data
• As expected, leakage current increases with increasing temperature
IBM Confidential
The above plot shows the forward bias and reverse bias P+/NW diode characteristics for
a 550um perimeter diode at different temperatures. The turn-on voltage decreases with
increasing temperatures. The leakage current also increases with increasing temperature.

Interconnects ESD Data
Type Number Width/Length Vfail (kV)

M1 4/1500 4.0
M3 4/1500 4.15
CA 10 Min 1.0
V1 10 Min 2.3
The interconnects meets minimum HBM requirement if Design Layout Rules ESD02
through ESD06 are followed.
IBM Confidential
Interconnects ESD data
The above slide shows the interconnect data. The M1, M3 metal width groundrules and
the CA, V1 groundrules are based on a 3kV HBM requirement.

ESD Compact Models
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IBM Confidential
15 Jan 03
ESD Compact Models

High current ESD models exist for ESD structures built using the ESD pcells from the
CMOS8RF Cadence Device Library. This section provides a brief introduction of these
models.

ESD Device Models

Device Description Model Name
(HSpice/Spectre)
Vertical PNP (P+/NW/SX) esdvpnpnw/esdvpnpnw
N+/SX Diode esdndsx/esdndsx
SBLK resistor sblkndres/sblkndres
High current ESD models exists for ESD structures built using the ESD pcells, in the
t1h00 model release version.
ESD NFETs are defined as a sub-circuit where the appropriate NFET models are
combined with the sblkndres model to simulate an ESD silicide-blocked NFET.
Further detailed information is provided in the CMRF8SF Model Reference Guide

which can be downloaded from IBM RFWEB
http://rfweb.btv.ibm.com/cgi-bin/commits/dkIntro.pl
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IBM Confidential
15 Jan 03
ESD Device Models
The models which are associated with ESD devices are (1) esdvpnpnw – a model for
P+/NW/SX ESD PNP, (2) esdndsx – a model for N+/SX ESD diode, (3) sblkndres – a
model for SBLK resistor that can be combined with regular NFET models to simulate
ESD NFETs for dual and triple well designs.
Detailed documentation of each of these models and Model to Hardware Correlation is
documented in the Model Reference Guide.

ESD Groundrule Descriptions
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IBM Confidential
15 Jan 03
ESD Groundrule Descriptions

ESD Layout Rules – Quick Tour

The ESD layout rules cover the following issues:
ESD01, 1a, 1b, 1c ESD02a, 3a ESD04, 4a, 5, 6, 6a, 6b, 6c
All I/O pads must be connected to an Sufficient contact and via area Sufficient metal wire width used
ESD HBM protection device of used in the path between the in the path between the pad and
sufficient size. pad and the protection device. the protection device.
ESD08, 9, 10 ESD11a ESD12f, 12g

Insure sufficient junction spacing to Raise snap-back voltages by Increase CA-PC spacing on FETs
shut off parasitic bipolar paths. increasing gate length connected to I/0.
ESD13a, 13b ESD14f ESD15a, 15b

Guard rings must be present. Use bordered contacts on RX Anode/cathode spacing limits on
connected to I/O. ESD diodes
ESD20, 21, 22, 23, 24, 25, 26 ESD30 to ESD40

Layout rules for silicide-blocked Layout rules for ESD CDM
ESD HBM and CDM NFET. structures.
1 Please note that all ESD rules are not mentioned above
IBM Confidential
15 Jan 03
ESD Layout Rules
The technology Design Manual has a set of checkable ESD ground rules that are
implemented in all or certain DRC decks. These rules have been formulated to achieve a
3kV HBM target.
These rules address different aspects of chip layout areas which can be affected during an
ESD event. Some of the issues are detailed in the slide above. The following pages
attempts to describe in certain detail, some of the representative ground rules that are
documented in the Design Manual.

HBM Rules – Protection Devices

ESD01: Must implement either Option 1 or Option 2 for all signal pads.
OPTION 1 OPTION 2
Vdd Vdd
HBM Up Diode
RCDM RCDM
Internal Internal
Circuitry Circuitry
CDM Network CDM Network
(if required) HBM NFET (if required)
HBM Down Diode
HBM HBM
Network Gnd Network
Silicide- Gnd
blocked
Option 1 Option
NFET
2
ESD Ground Device Structure ESD Device Structure

Rule Ground Rule
ESD01a Down N+ in ESD01c ESD NFET w/
Diode Substrate HBM silicide block
ESD01b Up Diode P+ in N- NFET on source
well and drain
2
IBM Confidential
15 Jan 03
HBM Rules – Protection Devices
The technology Design Manual has a set of checkable ESD ground rules that are
implemented in all or certain DRC decks. These rules have been formulated to achieve a
3kV HBM target with typical CMOS driver and receiver circuits.
The circuit diagrams show the I/O pin, the HBM network, the CDM network and a block
representing the I/O circuit being protected. We will focus on the HBM protect network.
Each I/O pin must use one of the HBM protection topologies shown. These are the
double diode network on the left and the ESD NFET network on the right.
For the double diode network, the “down” diode must be an N+/SX diode with the
required cathode perimeter. The “up” diode must be a P+/NW diode with the required
anode perimeter. If the I/O voltage can exceed Vdd, this diode may be replaced by a
diode string where each device has the same perimeter.
For the ESD NFET network the minimum NFET width as per the ground rule is required.
In addition, these ESD NFETs must have silicide-blocking on their source and drain side
as per ESD OP rules, which are described later in this section.

HBM Rules – Wiring Guidelines

Contacts, vias and wires carrying HBM discharge must be robust.
ESD Ground Rule Structure Description
ESD02a Vx Total area of vias
ESD03a CA Total area of contacts
ESD04 M1 Total width of metal
ESD04a M2 Total width of metal
ESD05 M3-M6 Total width of metal
ESD06 MQ, LM, MG Total width of metal
ESD06a E1 Total width of metal
ESD06b MA Total width of metal
ESD06c LY Total width of metal
These are the minimum allowable sizes. Use larger structures to minimize
series resistance.
• Rules are conservative for IBM ESD targets.
Rules checked for connections between the pad and the HBM devices.
Connection of HBM device to busses not checked, but must be equally
robust.
3
IBM Confidential
15 Jan 03
HBM Rules – Wiring Guidelines
Protection devices and circuit topologies are only part of the ESD solution. Another
critical factor is the size of the wiring in the discharge path. As with the protection
devices, there are two factors to consider: the failure current and the series resistance. The
ESD ground rules stipulate that any connection between the external pin and an HBM
ESD device must comply with the minimum sizes shown in the table in the above slide.
The minimum wire width varies depending on the wiring level since the wire thicknesses
are different.
The wiring rules are in relation to the IBM ESD tolerance targets, but this helps minimize
the wiring resistance to prevent large voltage drops. Remember that metal resistance
increases with temperature and that ESD acts like a current source. If wires are
significantly heated by the discharge, the voltage drop along the wire can become much
larger than the wire resistance tables would indicate. If there is room to use larger wires
than the table recommends, you should do so.
The ground rule deck does not check the bus resistance connecting the ESD protection
device to the power or ground bus. Since this is part of the discharge path, those wires
must also be sized per the guidelines shown in the table.

HBM Rules - Lateral Parasitic Devices

Spacing rules prevent activation of parasitic devices during discharge.
Negative
Discharge
TO DRIVER TO PAD GND OTHER CKT
N+ N+ P+ N+
STI
N-WELL RESISTOR
P- WAFER
Parasitic NPN can be formed by any combination of N+/SX and

NW/SX junctions.
ESD Ground Rule Description
ESD 08 Spacing between N-well to N-well (different net)
ESD 09 Spacing between N+ to N+ (RX spacing)
ESD 10 Spacing between N+ (RX) to N-well
4
IBM Confidential
15 Jan 03
HBM Rules - Lateral Parasitic Devices
It is well known that CMOS device structures contain parasitic bipolar devices that cause
latch-up. These same devices can also cause ESD vulnerabilities. Consider two closely-
spaced N-wells as shown in this chart. The N-well on the left is an N-well resistor that
connects the driver to the I/O pad. The adjacent N-well represents an unrelated circuit
that is placed in close proximity to the N-well resistor. This structure forms a parasitic
NPN transistor with the N-well resistor forming the emitter, the substrate as the base, and
the adjacent N-well as the collector. During a negative discharge pulse, a large current
will be drawn from the N-well resistor terminal as indicated by the “lightning bolt.”
Bipolar transistor action will cause a large current to flow from the adjacent N-well,
which is not designed to carry ESD currents. The resulting failure will occur at a much
lower voltage than the circuit could otherwise tolerate. This effect can occur between any
combination of closely spaced n+ junctions and N-wells.
The table summarizes the ESD ground rules that govern the minimum spacing between
n+ junctions and N-wells when one of the junctions is connected to an I/O pad.

HBM Rules – FETs Connected to Pads

FETs with S/D connected to pads must follow special layout rule
NFET PFET
ESD11a Add N-well
Substrate
Contact resistance to
prevent damage
ESD13a/LUP13 to N-well bias
N-well Guard ring wiring.
width
ESD14f
LUP13
No p+ junctions are
allowed in an N-well
guard ring (Latch-up)
N-well
Provide metal strapping
and adequate contact to
N-well guard ring and
substrate contact ring.
ESD12f LUP14a
RX CA
5
IBM Confidential PC N-well
15 Jan 03
Any FET connected to an I/O pad is subject to additional design rules both to ensure
adequate ESD protection and to prevent latch-up. These rules have been collected in this
illustration.
NFETs should be contained in a substrate contact and an N-well guard ring as shown. No
p+ junctions may be inside the N-well guard ring. To prevent snap-back, follow ESD11x
values as the minimum channel length. The contacts to the source/drain regions should be
placed farther inside the RX edges and farther from the polysilicon gate than would
normally be permitted.
PFETs must be placed in a substrate ring. The substrate ring must be wide enough to
meet LUP14a to ensure adequately low resistance.
Because the NFET and PFET drains appear in parallel with the ESD devices, they will be
part of the discharge circuit unless a resistor of at least 20 Ω is inserted between the
N/PFET and the ESD devices. In some designs the NFET and PFET parasitic junctions
are intentionally used to augment the ESD protection diodes. In these designs, wiring to
the FET and to the well contact must meet the ESD wiring rules.
Guard rings and contact rings must be contacted with sufficient number of CA’s and
Via’s and strapped with metal wiring to maintain very low wiring resistance.


FETs with S/D connected to pads must have silicide blocking on the
drain and source side by following OP layout rules
ESD23 ESD24
Representative
ESD rules
usage on a
Dual-well thin-
oxide ESD
NFET
ESD20
RX CA
PC OP
6
IBM Confidential
15 Jan 03
ESD OP Rules – FETs Connected to Pads
Any FET connected to an I/O pad is subject to additional design rules both to insure
adequate ESD protection. Some of them are the OP rules for silicide-blocking the ESD
NFET. These rules have been collected in this illustration.
OP shape of required widths as per the ground rules, should be drawn on the drain and
source side of the ESD NFET. The width requirements of these OP shapes depend on the
type of NFET, such as thin-oxide NFET, and thick-oxide (DG) NFET.
The OP shapes also need to be at a certain specified distance from the PC. Additional
SBLK shapes are also required

CDM Rules
ESD30: Must implement either Option 1 or Option 2 for all thin gates connected to pads.
OPTION 1 OPTION 2
Vdd Vdd
ESD32b
>250 ohm >250 ohm
ESD32a
ESD32c
Internal Internal
HBM CDM Network Circuitry HBM CDM Network Circuitry
Network Network
Gnd Gnd
CDM Network Device for thin-oxide gate protection

Rule Applicability Double Diode Diode Strings NFET
perimeter perimeter Gate perimeter
Thin ox gates with >50 Ω ESD31a/31b Prohibited ESD31c
CDM resistor
Thin ox gates with >250 ESD32a/32b ESD32a/32b ESD32c
Ω CDM resistor
ESD33 to ESD35c: CDM rules for thick-oxide gate protection

ESD39:
7
CDM resistor type and value.
ESD40: CDM resistor length.
IBM Confidential
15 Jan 03
CDM Rules
CDM rules are also implemented in DRC decks. These rules have been formulated to
achieve a 500V CDM target with typical CMOS receiver circuits.
The circuit diagrams show the I/O pin, the HBM network, the CDM network (shaded in
blue) and a block representing the I/O circuit being protected. We will focus on the CDM
protect network.
Each I/O pin must use one of the CDM protection topologies shown. These are the
double diode network on the left and the ESD NFET network on the right.
The CDM resistor must be polysilicon and its resistance should meet the ESD ground
rules.
The table at the bottom of the chart shows some of the allowable combinations of CDM
resistor and ESD device for a certain ESD HBM strategy. The protection strategy
depends on using the CDM resistor and the ESD device to reduce the pin voltage to a
value that will not damage the gate oxide. For this reason, the minimum resistor value
and the minimum ESD device size are related, and depend on the thickness of the
receiver gate oxide.

ESD Ground Rule Checking
ESD ground rule checking is dependent on user-added shapes

on dummy (non-build) layers.
Layer Purpose
ESDUMMY Place over all ESD diodes, NFET/PFET source/drain junctions,
and grounded-gate NFETs that are used for HBM protection.
ESD_CDM Place over all ESD diodes and grounded-gate NFETs that are
used for CDM protection.
IODUMMY Place rectangle on pads to designate them as signal pads to
(will be eliminated soon) receive ESD checking.
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IBM Confidential
15 Jan 03
ESD Ground Rule Checking
ESD ground rules are coded in many DRC tools. Ground rule checking depends on
certain shapes drawn on dummy, that is, non-build layers.
ESD diodes or grounded-gate NFETs that are to be used as HBM protection must be
covered by shapes on level “ESDUMMY.” In the self-protecting strategy where the
driver drain-to-well junctions are used as ESD diodes, the ESDUMMY shape should be
drawn over those junctions.
Diodes or grounded-gate NFETs used for CDM protection must be covered by shape on
level “ESD_CDM.”
One way the I/O pads are distinguished from power supply or ground pads is by adding a
shape on level “IODUMMY”. This shape should be coincident with the final passivation
opening on DV or LV. This option will soon be eliminated and all designers will need to
use the appropriate labels that are defined in the “Net Definitions for ESD Checking”
section in the technology Design Manual.

Net Definitions for ESD Ground Rule Checking
For ESD ground rule checking purposes, all cell level nets or chip
level pads are identified by one of the text label on a xxESD
design level, where xx=M1, M2, and so forth.
Some of the important labels:
Layer Purpose
FULL_ESD Place over all signal pads with ESD protection. All ESD ground
rules will be checked on these pads.
LC_POWER_ESD Place over all power supply pads that do not achieve a chip
capacitance of 100nF between supply and ground. Certain set of
ESD ground rules are checked on these pads. Refer technology
Design Manual.
HC_POWER_ESD Place over all power supply pads that do achieve a chip
capacitance of 100nF between supply and ground. Metal ESD
ground rules are checked on these pads.
In the absence of any valid label, the pad will be treated as a

1
signal IBM
pad.
Confidential
15 Jan 03
Net Definitions for ESD Ground Rule Checking
In order to enable accurate ESD checking on all pads, a set of ESD labels have been
created to distinguish between signal I/O pads and power supply pads. These text labels
should be on an xxESD design level where xx=M1, M2, and so forth. While the complete
set of ESD labels is listed in the ESD Ground Rule section of the Technology Design
Manual, a few of the important ones are listed in the slide above. The appropriate label
can be used at cell level or at chip level for ESD ground rule checking. It should be noted
here that in absence of any valid label on a net or pad, the net or pad will be treated as a
signal pad.
Low capacitance power supply pads are distinguished from the high capacitance power
supply pads by using the appropriate ESD labels. All low capacitance power supply pads
are expected to have an ESD power clamp between power supply and ground.

ESD Design Review
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IBM Confidential
15 Jan 03
ESD Design Review

ESD Design Review

ESD protection must be achieved on all off-chip drivers (OCD),
receivers, and in general ANY external pin. Since ESD protection
involves the ESD device, I/O circuitry, internal circuits and bus
architecture, it is the responsibility of the circuit designer to
guarantee ESD protection for his/her design to the above
specification for the intended markets.
In order to help the customer meet the ESD requirement, it is
recommended to request an ESD Design Review on the part.
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IBM Confidential
15 Jan 03
ESD Design Review
The ESD ground rules in the technology Design Manual and its implementation in DRC
decks assists the designer in designing a part which meets the ESD requirements. But this
alone has not proved to be sufficient for good ESD results, because of unique chip
designs and layout practices. Hence, the customer is recommended to request an ESD
Design Review on their part. This review could result in the unearthing of layout issues
which could later effect ESD results and provide an opportunity for the designer to fix it
before tape out.

Recommended process
Obtain IBM ESD kit during initial planning of a design. In all cases
usage of an exact ESD element within the kit may not be possible
however the elements in the ESD kit in these cases can serve as a
starting point or good reference design.
Consult with the ESD team customer interface early in the
design/planning phase (>2 months prior to tape out) an initial to discuss
general requirements. Access to the IBM ESD kit should be done prior
to this meeting.
Request a final ESD design review approximately 1 month prior to tape
out to allow time for design changes that may need to occur. External
customers need to have their program managers initiate this review.
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IBM Confidential
15 Jan 03
Recommended process
The designer is recommended to obtain and utilize the elements ESD Design Kit for ESD
protection on the part. An early contact with the ESD team customer interface is also
recommended as this could lead to overall understanding of ESD concepts and things to
keep in mind as the design progresses. Finally, it is recommended to request for a final
ESD Design Review on the part well in advance of the tape out, so that sufficient time is
available for the designer to make any fixes if required.

Obtaining the ESD Design Kit

Fixed layout version:
• Download from IBM Customer Connect web site:
• http://www.ibm.com/technologyconnect
• Select 'Registration" under the heading 'New User'
• After registering, sign in and specify Mark Gilbert megilber@us.ibm.com
as your Customer Connect contact.
• Internal customers can access the ESD kit directly from the intra-web.
The following steps should be followed to gain access :
• Request an intranet web server account from below web page:
• https://w3dir.btv.ibm.com/servlet/RequestUserId
• Request access to the ESD secure server from the below web page:
• https://crystal.btv.ibm.com/tdPublic/Admin/Access/ss_req_access.html
• Select the ESD design kit for the technology you are interested in.
• Now that you have the necessary permissions, the ESD kit can be
obtained at following web page:
• 3 https://crystal.btv.ibm.com/td-g39/g39data/esd/cmos9sf/esd_cmos9sf.html
IBM Confidential
15 Jan 03
The above procedure should be followed to obtain a Fixed layout version of the ESD
Design Kit.


Pcell version:
• ESD library is shipped with the design kit.
• Design kits can be downloaded from IBM Customer Connect
• http://www.ibm.com/technologyconnect
• Internal customers will find the ESD library in the installed Cadence
design kit.
4
IBM Confidential
15 Jan 03
The above procedure should be followed to obtain a Pcell version of the ESD Design Kit.

Requesting ESD Design Review

The official design review request form is located on the intra-web for
internal customers at the below web page:
https://crystal.btv.com/td-esd/esd_all.html
Access to this review request form can be obtained at the below web
page:
https://crystal.btv.ibm.com/tdPublic/Admin/Access/ss_req_access.html
Request access to ESD: Entry Level
External customers need to have their program managers initiate this
review via the review request form on the intra-web.
The following ESD Design Review Checklist Form needs to be
completed and appropriate items supplied prior to the ESD design
review being scheduled :
• Review_checklist.xls
• This checklist form can be found under “New Design Review info” link
Information required to be filled in this spreadsheet is discussed in the
upcoming pages
1
IBM Confidential
15 Jan 03
Requesting ESD Design Review
The above procedure should be followed to initiate an ESD Design Review on a given
part.

ESD Design Review Checklist Form

• A snap shot of the ESD Design Review Checklist
Form
IBM Confidential
ESD Design Review Check List Form
A snap shot of the ESD Design Review Check List Form is shown above. These tables
should be filled in with the appropriate information as explained in the following pages.

Review Check List file information

Table 1 should be filled with the ESD requirements for the product
Table 2 should be filled with the Latchup requirements for the product
Table 3 should be filled with the ESD review planning dates
Table 4 should be filled with general chip info and the name of the file
which has a high level ESD strategy block diagram
Table 5 should be filled with information for each unique I/O cell to be
reviewed
Table 6 should be filled with information for each unique Power and
Ground cell to be reviewed
Some of the items to be supplied for review in addition to the spreadsheet:
• A high level ESD strategy block diagram showing what is used on the
various I/Os and power supplies for ESD
• An example block diagram can be found at https://crystal.btv.ibm.com/td-
g39/g39data/esd/block_diagram_example.html
• Schematic and layout of all cells to be reviewed
• ESD DRC checking results
7
IBM Confidential
15 Jan 03
Review Check List file information
• ESD Product Requirements (HBM, MM, CDM). The Industry standards are:
HBM=2kV, MM=200V and CDM=500V
• Latchup Product Requirements (HBM, MM, CDM, Std Jedec JESD78 Latchup,
CDE – Cable plug latchup). During Powered HBM, standard ESD HBM testing is
conducted while the chip is powered up. During Powered HMM, HMM testing
(HMM tests for latchup occurance when a human discharges through a metal part
into a chip) is conducted while the chip is powered up. During Powered Cable
Discharge, CDE testing (CDE tests for latchup occurance when a charged cable
discharges into a chip) is conducted while the chip is powered up.
• High level block diagram of ESD strategy, showing what is used on the various
I/Os and power supplies for ESD.
• List of all I/O cells to be reviewed along with their schematic and layout. In
addition, estimates of the Vdd wiring resistance (between the connection to Vddx
by the I/O’s ESD devices AND to the connection to Vddx by the Vddx ESD
device) is needed.
• List of all Power and ground cells to be reviewed along with their schematic and
layout. In addition, information about the number of power clamps used (if any)
and the approximate capacitance connected to each of the Vdd supply, should be
provided.

ESD Design Guidelines
10
IBM Confidential
15 Jan 03
ESD Design Guidelines
• Need for ESD protection devices

• Digital Input/Receiver protection
• Digital Output/Driver protection
• RF/High speed circuit protection
• Power supply protection
• E-Fuse Fsource pad protection
• Most common mistakes

Need for ESD protection devices

• ESD damage directly responsible for approximately 10% of the total failure
returns [1] [2]
• ESD damage due to handling and testing has negative influence on product
yield [2]
• ESD event can occur between any two pads/pins of an IC
• ESD protection devices needed to shunt the ESD current and prevent/lower
flow of ESD current through driver or receiver circuit components
• ESD protection devices not only provides alternate path for ESD current but
is also capable of handling ESD event current magnitudes
• ESD protection devices required for all pads/pins
• The overall ESD robustness of a chip is a function of numerous parameters
in addition to the mere presence of ESD protection devices.
• [1] T.Green, “A review of EOS/ESD field failures in military equipment”, Proceedings of

the 10th EOS/ESD Symposium, pp. 7-14, 1988.
• [2] R.G. Wagner, J. Soden and C.F. Hawkins, “Extent and cost of EOS/ESD damage in
an IC manufacturing process”, Proceedings of the 15th EOS/ESD Symposium, pp. 49-
55, 1993.
1
IBM Confidential
15 Jan 03
Need for ESD protection devices
The need for ESD protection devices on all pads/pins of an IC has been well investigated
and documented. It has been estimated that ESD damage is directly responsible for
approximately 10% of the total failure returns [1][2]. ESD damage due to handling and
testing results in lower product yield. One of the important things to remember is that an
ESD event can occur between any two pads/pins of an IC and hence a desired path
through ESD protection devices should be available between any two pads/pins. It is also
required to keep the pad voltage at an output pad, lower than the snapback voltage of the
driver, so as to prevent current flow through it, leading to its destruction. Similarly, it is
also required to keep the gate voltage at an input pad, lower than the gate oxide
breakdown voltage of the receiver, so as to prevent oxide breakdown. The ESD
protection devices should and does not only provide a desired path for ESD discharge but
is also capable of handling the currents involved in these events. It should also be noted
that the overall ESD robustness of a part is not just dependent on the mere presence or
absence of an ESD protection device, but in the overall methodology of their placement
in the circuitry.
[1] T.Green, “A review of EOS/ESD field failures in military equipment”, Proceedings of the 10th
EOS/ESD Symposium, pp. 7-14, 1988.
[2] R.G. Wagner, J. Soden and C.F. Hawkins, “Extent and cost of EOS/ESD damage in an IC
manufacturing process”, Proceedings of the 15th EOS/ESD Symposium, pp. 49-55, 1993.

Digital Input/Receiver protection

• Minimal ESD protection network on input/receiver pad should consist
HBM/MM devices, CDM resistor and CDM devices
• HBM/MM protection considerations and recommendations:
– HBM/MM protection network benefits from additional CDM protection
network
• CDM protection considerations and recommendations:
– Designers should aim at keeping gate voltage of receiver gate below
gate oxide breakdown
– Range of CDM protection devices available based on gate oxide
thickness, CDM resistance and HBM/MM protection devices utilized
– CDM resistors greater than 100 ohm are recommended in order to
decrease current through resistor and result in lower voltage at gate
– OP P+ Poly resistors CDM resistors required for better current
handling
– Medium and thick oxide gates should be used for receivers due to their
higher oxide breakdown parameters
– CDM resistors and ESD CDM devices should be connected physically
close to receiver gates
2
IBM Confidential
15 Jan 03
At a minimum, the ESD protection network on the input/receiver pad should consist of
HBM/MM protection devices, CDM resistor and CDM protection devices. The HBM
protection devices also work as MM protection devices. The HBM/MM protection of an
input pad benefits from the additional CDM protection devices on the same pad. It is
required to keep the gate voltage at an input pad, lower than the gate oxide breakdown
voltage of the receiver, so as to prevent oxide breakdown. Appropriate sized CDM
protection devices (as required in the technology ESD ground rules) should be connected
to the input pad based on the type of gate that needs to be protected, the choice of the
CDM resistor and the type and sizing of the HBM/MM protection devices on the pad.
CDM resistors greater than 100 ohm are recommended in order to decrease the current
flow through the CDM protection network due to the fact that most of the current would
flow through the HBM protection network. OP P+ Poly resistors are recommended to be
used as CDM resistors because of their current handling capability. Medium and thick
oxide gate FETs are recommended to be used for receivers due to their higher oxide
breakdown voltages. In addition, CDM resistors and CDM protection devices should be
connected physically closer to the receiver gates.


• Standard Digital Input/Receiver circuit ESD protection:
– Consists of HBM/MM protection devices, CDM resistor and CDM
protection devices connected to gate
Vdd
Internal
Circuitry
HBM Network CDM Network
Gnd
1
IBM Confidential
15 Jan 03

• CDM protection considerations and recommendations:
– CDM protection network also required on pads which have pass gates
Vdd
Internal
Circuitry
HBM Network Pass Gate CDM Network
Network
Gnd
3
IBM Confidential
15 Jan 03
Some receiver circuits are connected to pads through a pass gate network. In such a case,
the DRC would be unable to identify such gates as gates that need CDM protection
network. But it would still be necessary to add a CDM protection network before the
gates as shown in the slide above.
Digital Output/Driver protection

• Minimal ESD protection network on output/driver pad should consist of HBM
devices.
• HBM protection considerations and recommendations:
– Designers should aim at keeping pad voltage lower than snapback
voltage of driver NFET
– Range of HBM protection network available based on pad voltage
tolerance, diode or NFET based and self or non-self based protection
– Recommended protection strategy is to use primary and secondary
protection or use of primary protection with stacked driver
– Medium and thick oxide devices are recommended for use in output
drivers due to their larger snapback voltage parameter
– Stacked NFET/PFET driver recommended instead of single
NFET/PFET driver
– Single silicide-blocked NFET drivers can be used in place of silicided
stacked NFET drivers
– Very crucial to keep power busing resistance as low as possible to
lower pad voltage during ESD event
4
IBM Confidential
15 Jan 03
At a minimum, the ESD protection network on the output/driver pad should consist of
HBM protection devices. It is required to keep the pad voltage at an output pad, lower
than the snapback voltage of the driver, so as to prevent current flow through it, leading
to its destruction. Appropriate sized HBM protection devices (as required in the
technology ESD ground rules) should be connected to the output pad. The HBM
protection devices are selected based on the pad voltage tolerance required, the choice of
diode or NFET based ESD protection and the choice of self or non-self protection
methodology. The recommended protection strategy is to use a secondary protection
network or use stacked drivers in addition to the primary HBM protection network.
Medium or thick oxide driver devices are recommended instead of thin oxide driver
devices, due to the fact that they exhibit larger snapback voltages. Stacked devices or
silicide blocked devices are recommended to be used as driver devices due to their
current handling capability and larger snapback voltages. It is also very crucial to keep
power bus resistance as low as possible to lower the pad voltage during an ESD event.


– One recommended protection strategy is the use of primary protection
with a stacked driver
Vdd
Pre-Drive
Circuits
Vdd
Gnd
Primary Stacked output
HBM Protection driver
2
IBM Confidential
15 Jan 03

– Another recommended protection strategy is use of primary and
secondary HBM protection networks
OPTION 1
Vdd
HBM Up Diode
R
Internal
Circuitry
HBM Down Diode
Gnd
Primary Secondary
HBM HBM
Network Network
5
IBM Confidential
15 Jan 03
The above slides provide a description of the recommended HBM protection strategies.

RF/High speed circuit protection

• Goal should be meet the same ESD requirements on RF pads as that on digital
pads
• Recommended ESD protection strategy on RF pads:
ESD device type Typical Capacitances

Self-protected diode based 25-100fF
Non-self protected diode based 100-200fF
Self-protected NFET based 400-500fF
• Non-self protected NFET based ESD protection strategy not recommended

• Diffusions and wiring of the ESD device should be optimized for lower capacitance
• In the case if technology ESD groundrules are not met, following recommendations
should be considered:
– Diodes used should be able to handle atleast 1.5A
– Minimize bus wiring resistance from IO cell to power cell
– Maximize power clamp size
–1 Have a good power clamp placement strategy
IBM Confidential
15 Jan 03
RF/High speed circuit protection
Designers should aim to meet the same ESD requirement on RF pads as that on digital
pads. The self-protected diode based ESD protection strategy is the recommended
protection strategy as this results in the least additional capacitance on the pad. The
additional capacitance is driven by the wiring and not by the diode which is a parasitic
diode inherent in the driver FET. The other possible options are the non-self protected
diode based ESD protection strategy and the self protected NFET based ESD protection
strategy. If the non-self protected diode based ESD protection strategy is employed,
designers could use a 2 diode string diode from pad to ground in order to cut the effective
capacitance in half. The diffusions and wiring of the ESD device should be optimized for
lower capacitance. In instances where the required ESD diode and/or NFET sizes are not
met, care should still be taken to ensure that the ESD structures that are used are atleast
able to hand 1.5A and sufficient sized power clamps should be placed so as to minimize
the bus wiring resistances. This strategy will lower the ESD requirement burden on the
signal pads while increasing the burden on the power bus and power pads.

Power supply protection

• ESD protection device should be connected between every power supply
pad and ground pad
• RC triggered silicided power clamp
– Very fast power-up ramp-up time leakage concerns
• Grounded gate silicide blocked power clamp
– CDM concerns
• Diode or diode strings
– Low leakage if few number of diodes used. Use same diode perimeter
as that required for meeting HBM requirements on signal pad
• Recommend placing an instance of 0.5ohm equivalent on-resistance power
clamp within an effective power bus resistance of 1ohm from a signal pad
• A large external resistor from supply to ground is needed for power supply
pads with low leakage
• DG NCAP recommended for capacitor in RC network of RC triggered power
clamp
2
IBM Confidential
15 Jan 03
Power Supply protection
ESD protection devices are recommended between every power supply pad and every
ground pad in a chip. A power clamp is recommended between every power supply pad
and every ground pad. On the other hand, if the power clamp is used between one power
supply pad and a ground pad, and ESD protection diodes are used between other power
supply pads and the power clamp protected power supply pad, then this could lead to
sequence independence issues. The use of RC triggered power clamp is recommended on
power supply pads which do not have very fast power-up ramp-up times (<100us). There
are CDM concerns in the use of grounded gate power clamp between power pad and
ground pad. Such grounded gate power clamps should only be used for very fast power-
up applications. Diode or diode strings with few diodes can also be used on power pads if
the leakage is acceptable. These diodes should be similarly sized as the HBM diodes on
the signal pads. Many instances of power clamps should be added to the power bus so as
to ensure that the busing resistance from any given signal pad to the nearest power clamp
is less than 1ohm. The power clamp should also be sized such that its on-resistance is
about 0.5ohms. For power supply pads with low leakage, an additional external resistor
needs to be added between the power supply pad and the ground pad. The resistor will
potentially determine the lower end of Iddq.

E-Fuse Fsource pad protection

• Fsource pads are used to blow E-fuses
• Fsource pad connected to fuse, blow FETs and other circuitry.
• Fsource pad should be connected to ESD protect devices to prevent
damage to the circuitry during any ESD event
• Any ESD protection strategy should consider the resultant Fsource pad
voltage during ESD event between Fsource pad and any other pad. This
resultant Fsource pad voltage should be lower than the snapback voltage of
the blow FET in order to avoid conduction through the blow FET
• ESD protect device options:
– RC triggered power clamp from Fsource pad to ground pad
• Appropriate voltage level power clamp should be used based on Fsource pad voltage
during fuse blow
• Power clamp and busing resistance to power clamp should be sized so as to keep the
pad voltage as low as possible during an ESD event.
– Appropriate number of ESD diodes from Fsource pad to power pad in
addition to ESD diodes from Fsource pad to ground pad. Additional
ESD protect device from power pad to ground pad
• Ensure voltage drop across the diodes, busing resistance and power pad ESD protect
device do not raise pad voltage above snapback voltage of any NFET/PFET connected
to FSource pad
3
IBM Confidential
15 Jan 03
The E-Fuse Fsource pad is used to blow the E-fuses. They are typically connected to the
fuse, blow FETs and other circuitry. These Fsource should be connected to ESD protect
devices to prevent damage to the circuitry during any ESD event on the pad. Any ESD
protection strategy scheme should evaluate the rise of Fsource pad voltage during an ESD
event between the Fsource pad and any other pad. The goal should be to keep this pad
voltage lower than the snapback voltage of any NFET/PFET connected to the FSource
pad in order to avoid conduction through this path.
The options for the ESD protection strategy on this pin are: (a) RC triggered Power
clamp based and (b) ESD diode based. The appropriate voltage level power clamp as
required by the Fsource pad voltage should be used. The power clamp should be sized
and placed so as to lower the pad voltage as much as possible during an ESD event.
Alternatively, ESD diodes can be used to protect ESD events between the Fsource pad
and the power pad. Similar ESD diodes can be used to protect ESD events between the
Fsource pad and the ground pad. Power clamps would still be needed between the power
pad and the ground pad.


• ESD protection shown between Fsource pad and Ground pad on a typical
E-Fuse Fsource pad network
Fsource
pad
protection
Fuse
ESD Blow network
network
Sense
Gnd
3
IBM Confidential
15 Jan 03
The slide above shows the ESD protection between E-Fuse Fsource pad and ground. The
E-Fuse Fsource pad is shown with a typical E-Fuse network.

Most common mistakes

• Avoid connecting thin-oxide gates directly to power supplies
• Avoid wiring NFET Source and Substrate/Pwell to different ground domains
• Avoid wiring PFET Source and Nwell to different power domains
• Minimize the discharge path resistance
4
IBM Confidential
15 Jan 03
Most common mistakes
• Avoid connecting thin-oxide gates directly to power supplies.

• Avoid wiring NFET Source and Substrate/Pwell to different ground domains.
• Avoid wiring PFET Source and Nwell to different power domains.
• Minimize the discharge path resistance.

Avoid Connecting Thin-oxide Gates Directly to Power

Supplies
Vdd!
+ 10-20 V - Chip power
BONDPAD domain
AVdd CDM Path capacitance
Power
Clamp
SOLUTION
AVdd
Vdd!
To FET
gates
+
10-20 V -
NFET is observed
to fail rather than
the PFET.
10
IBM Confidential
15 Jan 03
Avoid Connecting Thin-oxide Gates Directly to Power Supplies
When it is necessary to connect the gate of a thin-oxide FET to Vdd, do not wire the gate
directly to the power supply bus, unless these devices are ESD protection devices and are
covered by ESD_HBM or ESD_CDM levels. This practice of connecting the gate
directly to power supply bus can lead to low CDM failure voltages.
Consider a chip with two power supply domains as shown in this schematic diagram. The
circuit function calls for one of the inputs to the NAND gate to be tied high, so it was
connected directly to the AVdd power supply. Now assume that the bulk of the chip
operated from the Vdd! Supply. Therefore most of the chip capacitance will be connected
to that domain. The ESD design was done correctly in that the supplies share a common
ground bus, the supply busses are connected using an ESD device, and there is a power
clamp on the Vdd! power supply.
Now let the chip be charged to a negative voltage and grounded through the package pin
connected to BONDPAD. The CDM current will flow through the anti-parallel diodes to
the Vdd! bus to charge the chip. Since the peak CDM current will be 10- 20A, the AVdd
bus will develop 10 – 20V with respect to ground. This will break down the gate oxide of
the NAND NFET.
The solution is to tie the NAND input high through a CDM protection network as shown
in the inset. When the AVdd bus voltage rises during the CDM event, a much smaller
voltage develops across the gate oxide.

Avoid Wiring NFET Source and Substrate/Pwell

to Different Ground Domains
POOR GOOD
Discharge between grounds
agnd activates parasitic NFET agnd
source/SX diode
gnd agnd
Substrate gnd Substrate

Contact Contact M1
M1
agnd
agnd
NFET NFET
SEM of ESD Failure
11
IBM Confidential
15 Jan 03
Avoid Wiring NFET Source and Substrate/Pwell to Different

Ground Domains
If a chip has multiple ground domains, ensure that the source and substrate/pwell of the
NFET are connected to the same domain. If an NFET has the source on one domain and
the substrate/pwell connected to a different domain, low ESD failure voltages can result.
Consider a chip with two ground domains: agnd and gnd. The schematic and layout on
the left show the source and substrate/pwell connected to different grounds because of the
proximity of the gnd substrate contact to the device. During an ESD discharge from gnd
to agnd, the parasitic n+/substrate diode becomes forward biased and can carry a
substantial portion of the discharge current. Failure analysis of this device (center) shows
the damage to the device as a result of ESD conducted between the substrate contact and
the FET source junction.
The correct design is shown in the schematic and layout on the right. The local substrate
is connected to the same ground as the source.
Be especially careful at boundaries between circuit blocks were devices may be in close
proximity to substrate contacts wired to a different ground domain. If necessary, use
BFMOAT regions to increase the resistance between the substrate contact and the
parasitic junction.
Similarly, designers should avoid connecting PFET Source and Nwell to different power
domains.

Minimize the Discharge Path Resistance
High resistance in the discharge path leads to poor

ESD performance.
• Use wide bus wires, parallel metal levels is possible
• Place power clamps at multiple locations around the
chip ESD
Diode
Vdd
To Internal Power Vdd

+ Circuits Clamp Bus
Potentially
Damaging Voltage
Gnd -
12 Gnd
IBM Confidential
15 Jan 03
Minimize the Discharge Path Resistance
A high discharge path resistance will lead to a larger voltage at the pad which in turn can
lead to potential damage of the driver and/or receiver circuit. Hence, wide bus wires and
parallel metal levels should be used as much as possible. Also, power clamps from supply
to ground, should be placed at multiple locations to reduce the discharge path resistance
from any signal pad to ground.


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CMOS8RF/CMRF8SF ESD Reference Guide

CMOS8RF(CMRF8SF) ESD Reference

© IBM Corporation, 2005. All rights reserved. Page 1 of 148

This Document May be Obsolete

Document Distribution, Availability, and Ownership

© IBM Corporation, 2005. All rights reserved. Page 2 of 148

Document Revision History Change List

© IBM Corporation, 2005. All rights reserved. Page 3 of 148

ELECTROSTATIC DISCHARGE (ESD)

IBM Systems and Technology Group

IBM Confidential © 2003 IBM Corporation

This document describes ESD protection in IBM’s CMOS8RF/CMRF8SF technology.

© IBM Corporation, 2005. All rights reserved. Page 4 of 148

© IBM Corporation, 2005. All rights reserved. Page 5 of 148

ESD Design Kit Description ................................................................55

© IBM Corporation, 2005. All rights reserved. Page 6 of 148

Most common mistakes .......................................................................................................... 145

© IBM Corporation, 2005. All rights reserved. Page 7 of 148

• ESD Protection Strategy Background

• ESD Device Physics

• ESD Design Kit Description

• ESD Design Kit Data

• ESD Relevant Technology Data

• ESD Compact Models

• ESD Groundrule Descriptions

• ESD Design Review

• ESD Design Guidelines

IBM Confidential © 2003 IBM Corporation

© IBM Corporation, 2005. All rights reserved. Page 8 of 148

ESD Phenomena and Test Methods

IBM Confidential © 2003 IBM Corporation

ESD Phenomena and Test Methods

© IBM Corporation, 2005. All rights reserved. Page 9 of 148

On-Chip stress Lowest Current and Intermediate Current, Highest Current,

Table 1: ESD Events

© IBM Corporation, 2005. All rights reserved. Page 10 of 148

Human Body Model (HBM)

• IBM wafer test setup limited to 4kV

Figure 1: HBM equivalent circuit and waveform

Human Body Model

© IBM Corporation, 2005. All rights reserved. Page 11 of 148

Machine Model (MM)

Figure 2: MM equivalent circuit and waveform

© IBM Corporation, 2005. All rights reserved. Page 12 of 148

Charged Device Model (CDM)

• Test can be in a fixture (socketed) or with

• Typical Test Regimen

Figure 3: CDM equivalent circuit and waveform

Charged Device Model

© IBM Corporation, 2005. All rights reserved. Page 13 of 148

Transmission Line Pulse (TLP)

Figure 4: TLP test setup

Transmission Line Pulse (TLP)

© IBM Corporation, 2005. All rights reserved. Page 14 of 148

ESD Protection Level Targets and Requirements

ESD Model Industry Standard

Table 2: ESD Protection Industry Standard

ESD Protection Level Targets and Requirements

© IBM Corporation, 2005. All rights reserved. Page 15 of 148

ESD Model Standard Specifications

ESD voltages can exceed the breakdown voltage

Protection networks require a means of conducting discharge

Current carrying capability (=> 2A => 3KV HBM)