Multiplexer and De-multiplexer

The function of a multiplexer is to select the input of any

‘n’ input lines and feed that to one output line. The function
of a de-multiplexer is to inverse the function of the
multiplexer and the shortcut forms of the multiplexer. The
de-multiplexers are mux and demux. Some multiplexers
perform both multiplexing and de-multiplexing operations.
The main function of the multiplexer is that it combines
input signals, allows data compression, and shares a single
transmission channel.

What is a Multiplexer and De-multiplexer?

1.Multiplexer
Multiplexer is a device that has multiple inputs and a single
line output. The select lines determine which input is
connected to the output, and also to increase the amount of
data that can be sent over a network within certain time. It
is also called a data selector.

Multiplexer
The single pole multi-position switch is a simple example
of non-electronic circuit of multiplexer, and it is widely
used in many electronic circuits. The multiplexer is used to
perform high-speed switching and is constructed
by electronic components.
Multiplexers are capable of handling both analog
and digital applications. In analog applications,
multiplexers are made up of of relays and transistor
switches, whereas in digital applications, the multiplexers
are built from standard logic gates. When the multiplexer
is used for digital applications, it is called a digital
multiplexer.
Multiplexer Types
Multiplexers are classified into four types:

• 2-1 multiplexer ( 1select line)

• 4-1 multiplexer (2 select lines)
• 8-1 multiplexer(3 select lines)
• 16-1 multiplexer (4 select lines)

2-input Multiplexer Design

The input A of this simple 2-1 line multiplexer circuit

constructed from standard NAND gates acts to control
which input ( I0 or I1 ) gets passed to the output at Q.
From the truth table above, we can see that when the data
select input, A is LOW at logic 0, input I1 passes its data
through the NAND gate multiplexer circuit to the output,
while input I0 is blocked. When the data select A is HIGH
at logic 1, the reverse happens and now input I0 passes data
to the output Q while input I1 is blocked.
So by the application of either a logic “0” or a logic “1” at
A we can select the appropriate input, I0 or I1 with the
circuit acting a bit like a single pole double throw (SPDT)
switch.
As we only have one control line, (A) then we can only
switch 21 inputs and in this simple example, the 2-input
multiplexer connects one of two 1-bit sources to a common
output, producing a 2-to-1-line multiplexer. We can
confirm this in the following Boolean expression.
Q = A.I0.I1 + A.I0.I1 + A.I0.I1 + A.I0.I1
and for our 2-input multiplexer circuit above, this can be
simplified too:
Q = A.I1 + A.I0
We can increase the number of data inputs to be selected
further simply by following the same procedure and larger
multiplexer circuits can be implemented using smaller 2-
to-1 multiplexers as their basic building blocks. So for a 4-
input multiplexer we would therefore require two data
select lines as 4-inputs represents 22 data control lines give
a circuit with four inputs, I0, I1, I2, I3 and two data select
lines A and B as shown.
4-to-1 Channel Multiplexer

The Boolean expression for this 4-to-1 Multiplexer above

with inputs A to D and data select lines a, b is given as:
Q = abA + abB + abC + abD
In this example at any one instant in time only ONE of the
four analogue switches is closed, connecting only one of
the input lines A to D to the single output at Q. As to which
switch is closed depends upon the addressing input code on
lines “a” and “b“.
So for this example to select input B to the output at Q, the
binary input address would need to be “a” = logic “1” and
“b” = logic “0”. Thus we can show the selection of the data
through the multiplexer as a function of the data select bits
as shown.

Multiplexer Input Line Selection

Adding more control address lines, (n) will allow the

multiplexer to control more inputs as it can switch 2n inputs
but each control line configuration will connect only ONE
input to the output.
Then the implementation of the Boolean expression above
using individual logic gates would require the use of seven
individual gates consisting of AND, OR and NOT gates as
shown.

4 Channel Multiplexer using Logic Gates

8-to-1 Multiplexer

8-to-1 Multiplexer
The 8-to-1 multiplexer consists of 8 input lines, one output
line and 3 selection lines.

8-1 Multiplexer Circuit

For the combination of selection input, the data line is
connected to the output line. The circuit shown below is an
8*1 multiplexer. The 8-to-1 multiplexer requires 8 AND
gates, one OR gate and 3 selection lines. As an input, the
combination of selection inputs are giving to the AND gate
with the corresponding input data lines.

In a similar fashion, all the AND gates are given

connection. In this 8*1 multiplexer, for any selection line
input, one AND gate gives a value of 1 and the remaining
all AND gates give 0. And, finally, by using OR gate, all
the AND gates are added; and, this will be equal to the
selected value.
8-1 Multiplexer Circuit
Applications of Multiplexers
Multiplexers are used in various applications wherein
multiple-data need to be transmitted by using single line.

• Communication System
A communication system has both a communication
network and a transmission system. By using a multiplexer,
the efficiency of the communication system can be
increased by allowing the transmission of data, such as
audio and video data from different channels through
single lines or cables.
• Computer Memory

Multiplexers are used in computer memory to maintain a

huge amount of memory in the computers, and also to
reduce the number of copper lines required to connect the
memory to other parts of the computer.

• Telephone Network
In telephone networks, multiple audio signals are
integrated on a single line of transmission with the help of
a multiplexer.

• Transmission from the Computer System of a

Satellite
Multiplexer is used to transmit the data signals from the
computer system of a spacecraft or a satellite to the ground
system by using a GSM satellite.

De-multiplexer
De-multiplexer is also a device with one input and multiple
output lines. It is used to send a signal to one of the many
devices. The main difference between a multiplexer and a
de-multiplexer is that a multiplexer takes two or more
signals and encodes them on a wire, whereas a de-
multiplexer does reverse to what the multiplexer does.
 De-multiplexer
Types of De multiplexer
De-multiplexers are classified into four types

• 1-2 demultiplexer (1 select line)

• 1-4 demultiplexer (2 select lines)

• 1-8 demultiplexer (3 select lines)

• 1-16 demultiplexer (4 select lines)

1-8 De-multiplexers
The demultiplexer is also called as data distributors as it
requires one input, 3 selected lines and 8 outputs. De-
multiplexer takes one single input data line, and then
switches it to any one of the output line. 1-to-8
demultiplexer circuit diagram is shown below; it uses 8
AND gates for achieving the operation. The input bit is
considered as data D and it is transmitted to the output
lines. This depends on the control input value of the AB.
When AB = 01, the upper second gate F1 is enabled, while
the remaining AND gates are disabled, and the data bit is
transmitted to the output giving F1= data. If D is low, the
F1 is low, and if D is high, the F1 is high. So the value of
the F1 depends on the value of D, and the remaining
outputs are in low state.

1 -8 De-multiplexer circuit
Applications of De multiplexer
De multiplexers are used to connect a single source to
multiple destinations. These applications include the
following:

• Communication System
Mux and demux both are used in communication system to
carry out the process of data transmission. A De-
multiplexer receives the output signals from the
multiplexer and at the receiver end it converts them back
to the original form.
• Arithmetic Logic Unit

The output of the ALU is fed as an input to the De-

multiplexer, and the output of the demultiplexer is
connected to a multiple register. The output of the ALU can
be stored in multiple registers.

• Serial to Parallel Converter

This converter is used to reconstruct parallel data. In this
technique, serial data is given as an input to the De-
multiplexer at a regular interval, and a counter is attached
to the demultiplexer at the control input to detect the data
signal at the output of the demultiplexer. When all data
signals are stored, the output of the demux can be read out
in parallel.

Multiplexer vs Demultiplexer

PARAMETER MULTIPLEXER DEMULTIPLEXER

Definition A multiplexer is a A demultiplexer is a

combinational combinational circuit

circuit that provides that takes single input

single output but but that input can be

PARAMETER MULTIPLEXER DEMULTIPLEXER

accepts multiple data directed through

inputs. multiple outputs.

Symbol

Number of data Multiple Single

inputs

Number of data Single Multiple

output
PARAMETER MULTIPLEXER DEMULTIPLEXER

Conversion It performs parallel It performs serial to

technique to serial conversion. parallel conversion.

Device It is N to 1 device It is 1 to N device and

configuration and thus behaves as thus behaves as data

data selector. distributor.

Encoder and Decoder

In digital electronic projects, the encoder and decoder play
an important role. It is used to convert the data from one
form to another form. Generally, these are frequently used
in the communication systems like telecommunication,
networking, and transfer the data from one end to the other
end. In the same way it is also used in the digital domain
for easy transmission of data, placed with the codes and
then transmitted. At the end of the receiver, the coded data
are collected from the code and then processed to display.
This article discusses about what is encoder and encoder,
working and its applications.
Binary code of N digits can be used to store 2N distinct
elements of coded information. This is what encoders and
decoders are used for. Encoders convert 2N lines of input
into a code of N bits and Decoders decode the N bits into
2N lines.

1.Encoders –
An encoder is a combinational circuit that converts binary
information in the form of a 2N input lines into N output
lines, which represent N bit code for the input. For simple
encoders, it is assumed that only one input line is active at
a time.
As an example, let’s consider Octal to Binary encoder. As
shown in the following figure, an octal-to-binary encoder
takes 8 input lines and generates 3 output lines.
Truth Table –
D7 D6 D5 D4 D3 D2 D1 D0 X Y Z

0 0 0 0 0 0 0 1 0 0 0

0 0 0 0 0 0 1 0 0 0 1

0 0 0 0 0 1 0 0 0 1 0

0 0 0 0 1 0 0 0 0 1 1

0 0 0 1 0 0 0 0 1 0 0

0 0 1 0 0 0 0 0 1 0 1

0 1 0 0 0 0 0 0 1 1 0
D7 D6 D5 D4 D3 D2 D1 D0 X Y Z

1 0 0 0 0 0 0 0 1 1 1

As seen from the truth table, the output is 000 when D0 is

active; 001 when D1 is active; 010 when D2 is active and
so on.
Implementation –
From the truth table, the output line Z is active when the
input octal digit is 1, 3, 5 or 7. Similarly, Y is 1 when input
octal digit is 2, 3, 6 or 7 and X is 1 for input octal digits 4,
5, 6 or 7. Hence, the Boolean functions would be:
X = D4 + D5 + D6 + D7
Y = D2 +D3 + D6 + D7
Z = D1 + D3 + D5 + D7
Hence, the encoder can be realised with OR gates as
follows:
One limitation of this encoder is that only one input can be
active at any given time. If more than one inputs are active,
then the output is undefined. For example, if D6 and D3 are
both active, then, our output would be 111 which is the
output for D7. To overcome this, we use Priority Encoders.
Another ambiguity arises when all inputs are 0. In this case,
encoder outputs 000 which actually is the output for D0
active. In order to avoid this, an extra bit can be added to
the output, called the valid bit which is 0 when all inputs
are 0 and 1 otherwise.
Priority Encoder –
A priority encoder is an encoder circuit in which inputs are
given priorities. When more than one inputs are active at
the same time, the input with higher priority takes
precedence and the output corresponding to that is
generated.
Let us consider the 4 to 2 priority encoder as an example.
From the truth table, we see that when all inputs are 0, our
V bit or the valid bit is zero and outputs are not used. The
x’s in the table show the don’t care condition, i.e, it may
either be 0 or 1. Here, D3 has highest priority, therefore,
whatever be the other inputs, when D3 is high, output has
to be 11. And D0 has the lowest priority, therefore the
output would be 00 only when D0 is high and the other
input lines are low. Similarly, D2 has higher priority over
D1 and D0 but lower than D3 therefore the output would
be 010 only when D2 is high and D3 are low (D0 & D1 are
don’t care).
Truth Table –
D3 D2 D1 D0 X Y V

0 0 0 0 x x 0

0 0 0 1 0 0 1

0 0 1 x 0 1 1

0 1 x x 1 0 1
D3 D2 D1 D0 X Y V

1 x x x 1 1 1

Implementation –
It can clearly be seen that the condition for valid bit to be 1
is that at least any one of the inputs should be high. Hence,
V = D0 + D1 + D2 + D3
For X:

=> X = D2 + D3
For Y:
=> Y = D1 D2’ + D3
Hence, the priority 4-to-2 encoder can be realized as
follows:

2.Decoders –
A decoder does the opposite job of an encoder. It is a
combinational circuit that converts n lines of input into
2n lines of output.
Let’s take an example of 3-to-8 line decoder.
Truth Table –
X Y Z D0 D1 D2 D3 D4 D5 D6 D7

0 0 0 1 0 0 0 0 0 0 0

0 0 1 0 1 0 0 0 0 0 0

0 1 0 0 0 1 0 0 0 0 0

0 1 1 0 0 0 1 0 0 0 0

1 0 0 0 0 0 0 1 0 0 0

1 0 1 0 0 0 0 0 1 0 0

1 1 0 0 0 0 0 0 0 1 0

1 1 1 0 0 0 0 0 0 0 1
Implementation –
D0 is high when X = 0, Y = 0 and Z = 0. Hence,
D0 = X’ Y’ Z’
Similarly,
D1 = X’ Y’ Z
D2 = X’ Y Z’
D3 = X’ Y Z
D4 = X Y’ Z’
D5 = X Y’ Z
D6 = X Y Z’
D7 = X Y Z
Hence,
PLA and PAL

PLA and PAL are types of Programmable Logic Devices

(PLD) which are used to design combination logic together
with sequential logic. The significant difference between
the PLA and PAL is that the PLA consists of the
programmable array of AND and OR gates while PAL has
the programmable array of AND but a fixed array of OR
gate. PLD’s provides a more simple and flexible way of
designing the logic circuits where the number of functions
can also be increased. These are also implemented in IC.

Before PLD’s, multiplexers were used for designing a

combinational logic circuit, these circuits were highly
complex and rigid. Then Programmable logic
devices (PLD) are developed, and the first PLD was ROM.
ROM design was not very successful as it emerged the
issue of hardware wastage and increasing exponential
growth in the hardware for every large application. To
overcome the limitations of ROM, PLA and PAL were
devised. PLA and PAL are programmable and effectively
utilizes the hardware.
Comparison Chart

BASIS FOR
PLA PAL
COMPARISON

Stands for Programmable Programmable

Logic Array Array Logic

Construction Programmable Programmable

array of AND and array of AND

OR gates.
BASIS FOR
PLA PAL
COMPARISON

gates and fixed

array of OR gates.

Availability Less prolific More readily

available

Flexibility Provides more Offers less

programming flexibility, but

flexibility. more likely used.

Cost Expensive Intermediate cost

BASIS FOR
PLA PAL
COMPARISON

Number of Large number of Provides the

functions functions can be limited number of

implemented. functions.

Speed Slow High

Definition of PLA
PLA stands for the Programmable Logic Array which
presents the boolean function in the SOP (Sum of Products)
form. The PLA contains NOT, AND and OR gates
fabricated on the chip. It passes every input by a NOT gate
which makes each input and its complement available to
every AND gate. The output of each AND gate is given to
the each OR gate. At last, the OR gate output produces chip
output. So, this is how suitable connections are made to
employ SOP expressions.

In PLA the connections to both AND and OR arrays are

programmable. PLA is considered more expensive and
complex as compared to the PAL. The two different
manufacturing techniques can be used for PLA to increase
the ease of programming. In this technique, each
connection is built through a fuse at every intersection
point where the unwanted connections can be removed by
blowing the fuses. The latter technique involves the
connection making at the time of the fabrication process
with the help of the proper mask provided for the specific
interconnection pattern.
Definition of PAL
PAL (Programmable Array Logic) is also a PLD
(Programmable Logic Device) circuit which works similar
to the PLA. PAL employs the programmable AND gates
but fixed OR gates, unlike PLA. It implements two simple
functions where the number of linked AND gates to each
OR gate specifies the maximum number of product terms
that can be generated in a sum-of-products representation
of the particular function. While the AND gates are
perpetually connected to the OR gates, which signifies that
the produced product term is not shareable with the output

functions.
The main concept behind developing PLD’s is to embed a
complex boolean logic into a single chip. Therefore,
eliminating the unreliable wiring, preventing the logic
design and minimizing power consumption.

Key Differences Between PLA and PAL

1. The PLA is PLD, comprised of two levels of

programmable logic AND plane and OR plane. On the
other hand, PAL contains only programmable AND
plane and fixed OR plane.
2. When it comes to availability, the PAL is more readily
available along with easy production. In contrast, the
PLA is not easily available.
3. The PLA is more flexible than a PAL.
4. PLA is costlier as compared to the PAL.
5. A number of functions provided by PLA are more
relatively because it enables the programming of the
OR plane also.
6. PAL works faster while PLA is slower comparatively.

Link:
1. https://www.elprocus.com/what-is-multiplexer-and-
de-multiplexer-types-and-its-applications/
2. https://www.electronics-
tutorials.ws/combination/comb_2.html
3. https://techdifferences.com/difference-between-pla-
and-pal.html
4. https://www.geeksforgeeks.org/programmable-logic-
array/