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Activity 2

This document describes an activity where students implement NOR logic circuits for a voting booth monitoring system. Specifically, the circuits implement the Booth and Alarm outputs. In the previous activity, these circuits were designed using AOI and NAND gates. Now, the goal is to re-implement the circuits using only 2-input NOR gates. The circuits are designed on paper, simulated using circuit design software, tested on a digital logic board, and compared in terms of hardware efficiency to the previous AOI and NAND implementations. It is found that the NOR implementation requires fewer ICs but more gates compared to the AOI design, and is more efficient than the NAND design. A 3-input NOR chip could have provided even more efficiency.

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380 views

Activity 2

This document describes an activity where students implement NOR logic circuits for a voting booth monitoring system. Specifically, the circuits implement the Booth and Alarm outputs. In the previous activity, these circuits were designed using AOI and NAND gates. Now, the goal is to re-implement the circuits using only 2-input NOR gates. The circuits are designed on paper, simulated using circuit design software, tested on a digital logic board, and compared in terms of hardware efficiency to the previous AOI and NAND implementations. It is found that the NOR implementation requires fewer ICs but more gates compared to the AOI design, and is more efficient than the NAND design. A 3-input NOR chip could have provided even more efficiency.

Uploaded by

api-492104888
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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Date \Oil-\ / \'\ Period L


Activity 2.2.3 NOR Logic Design

Introduction l~
In this activity you will revisit the voting booth monitoring system introduced in Activity 2.2.2 NAND
Logic Design. Specifically, you will be implementing the NOR only combinational logic circuits for the
two outputs Booth and Alarm. In terms of efficiency and gate/IC utilization, these NOR only designs
will be compared with the previously designed AOI and NAND implementations.

Equipment

• Paper and pencil


• Circuit Design Software (CDS)
• Digital Logic Board (DLB)
• Integrated Circuits (74LS02)
• Jumper wire

Procedure

The truth table and K-Maps for the voting booth monitor system can be seen in Activity 2.2.2 NAND
Logic Design. For your reference, the simplify logic expressions for the outputs Booth and Alarm are
shown below:

Booth =A B + C D
Alarm= AB+ B C+C D

1. In the space provided, re-draw the AOI circuits that you designed in Activity 2.2.2 NAND Logic
Design.

Booth-AOI
A B c t)_

Alarm-AOI
A \3 C ' t)
502) are available. Draw
. . -in ut NOR gates (74L
2. Re-implement these circuits assuming that only 2 P
these circuits in the space provided.

Booth-NOR

Alarm-NOR

Using the cos 1 enter and test the two logic circuits that you designed. Use switches for the
3. the
inputs A, s, C, and D and a probe or LED circuit for the outputs Booth and Alarm. Verify that
circuits are working as expected. Label, print. and attach a copy of these circuits to th~ .
document. Note: Even though the two circuits work independently, they are part of one design
and should be simulated, tested, and prototyped together.
th
4. Usin~ th~ DLB, build ~nd test the NOR logic circuits that you designed and simulated. ver!fV at
the c1rcu1ts are working as expected and that the results match the results of the simulation,

Teacher verification of working circuit ~ f u -l-->J


- - - - . . - - - ' - - -....!::.._ _ _ _ _ __
___-
Conclusion

1. For your NOR implementations, how many ICs (i.e., 74LS02 chips) were required to implement
your circuits? Again, we are counting ICs, not gates.

I[~~ ~O\C ·,~y1~~ -n{{;\_ \ \ )·~ '-'l"'.('~ - q TC ciiY',.

2. In terms of hardware efficiency, how does the NOR implementation compare to the AOI
implementation (Refer to Activity 2.2.2 NANO Logic Design)?

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'
J\ 0 J:_ v,.-.>-J. <) V'(_ ' ~

3. In terms of hardware efficiency, how does the NOR implementation compare to the NANO
implementation in Activity 2.2.2 NAND Logic Design?
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~ .... \,-JO '( -,~,J- cvv- e"'-\ l '-'\~\ v-..l-1. < fl.A.~ '$ 0 1,,.'Vv\-{ cl(\ ,<. '-'-'h.,'- r1 .

4. NOR gates are available with three inputs (74LS27). Could this chip have been used for this
design? If so, h,ow would it have affected the efficiency of the design?

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