Department of Electrical Engineering (New Campus)

EE 213L – Analog & Digital Electronic Circuits

Semester: Spring 2021

LAB 5: JFET and MOSFET (DC Biasing Review)

Submitted to: Mam Iqra Farhat

Section: “A”

Group Members: 1- Syed M. Saweiz (2019-EE-275)

2- Syed Furqan Javed (2019-EE-280)

3- Asif Khan (2019-EE-339)

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 Experiment # 5
To study JFET and MOSFET DC Biasing

1. Objective:
i. To analyse DC biasing techniques of JFETs
ii. To analyse DC biasing techniques of MOSFETs
iii. Implementing above circuits in Proteus

2. Apparatus:

i. Resistors (500, 1.5 kΩ, 2.5 kΩ, 4 kΩ, 24 kΩ)

ii. BJT Transistors (2N3904 & 2N3055)
iii. Voltmeter
iv. DC voltage source (12 V)

3. Theory:
Importance of Biasing:
The bias circuit stabilizes the operating point of the transistor for variations in transistor
characteristics and operating temperature. The gain of a transistor can vary significantly between
different batches, which results in widely different operating points after replacement of a transistor.
The MOS transistor is biased within the saturation region to establish the desired drain
current which will define the transistors Q-point. As the instantaneous value of 𝑉𝐺𝑆 increases, the
bias point moves up the curve as shown allowing a larger drain current to flow as 𝑉𝐷𝑆 decreases.
A bias circuit may be composed of only resistors, or may include elements such as
temperature-dependent resistors, diodes, or additional voltage sources, depending on the range of
operating conditions expected.

I- For JFETs:
a) Self Biasing:
Self-bias is the most common type of JFET bias. A JFET must be operated such that the gate-
source junction is always reverse-biased. This condition requires a negative 𝑉𝐺𝑆 for an n-channel
JFET and a positive 𝑉𝐺𝑆 for a p-channel JFET.
The self-bias configuration eliminates the need for two dc supplies. The controlling
gate-to-source voltage is now determined by the voltage across a resistor RS introduced in the
source leg of the configuration as shown in Fig. 1.
This can be achieved using the self-bias arrangements. The gate resistor, 𝑅𝐺 , does not affect
the bias because it has essentially no voltage drop across it, and therefore the gate remains at 0 V.

b) Fixed Biasing:
In fixed DC biasing technique of an N channel JFET, the gate of the JFET is connected in
such a way that the VGS of the JFET remains negative all the time. So, by this biasing technique,
we can control the JFET drain current by just changing the fixed voltage thus changing the 𝑉𝐺𝑆 .

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c) Voltage divider Biasing:
The voltage at the source of the JFET must be more positive than the voltage at the gate in
order to keep the gate-source junction reverse-biased. The gate voltage is set by resistors R1 and
R2 as expressed by the following equation using the voltage-divider formula:
𝑅2
𝑉𝐺 = ( )𝑉
𝑅1 + 𝑅2 𝐷𝐷

II- For MOSFETs:

a) Fixed Biasing:
In fixed DC biasing technique of an N channel JFET, the gate of the JFET is connected in
such a way that the VGS of the JFET remains negative all the time. So, by this biasing technique,
we can control the JFET drain current by just changing the fixed voltage thus changing the 𝑉𝐺𝑆 .

b) Voltage divider Biasing:

When compared to BJTs, MOSFETs have very low transconductance, which means the
voltage gain will not be large. Voltage divider bias is reminiscent of the divider circuit used with
BJTs. Indeed, the N-channel D-MOSFET requires that its gate be higher than its source, just as
the NPN BJT requires a base voltage higher than its emitter.
The major differences between the two are that the D-MOSFET's input gate current is
negligible compared to base current and that the gate-source voltage will be most likely higher
than the 0.7 volt drop seen across the base-emitter junction. Also, the gate-source voltage will
not be locked to a specific voltage but will vary depending on the remainder of the circuit.

4. Circuit Diagram:

Fig. 1: Self bias JFET

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Fig. 2: Voltage divider bias JFET

Fig. 3: Fixed bias JFET

Fig. 4: Fixed bias MOSFET

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 Fig. 5: Voltage divider bias MOSFET

5. Procedure:
i. Firstly, open a new project in Proteus.
ii. Then goto the component library and take: a resistor, a JFET, a MOSFET and a cell.
iii. For resistor, type “RES”, for JFET “2N3819”, for MOSFET “DN2530”, and for dc voltage
source “cell”.
iv. We will use DC source and Multimeter, so for getting DC source goto “Generators” and choose
“DC”. Similarly, for Voltmeter or Ammeter goto “Instruments” and choose DC voltmeter or
ammeter.

I- For JFETs:
a) Self Biasing:
v. Keeping the above points in mind, create a circuit as shown below in Fig. 6.

Fig. 6: Self Bias JFET in Proteus

vi. Hit the simulation button and note the readings.

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b) Fixed Biasing:
vii. Create a circuit as shown below in Fig.7.

Fig. 7: Fixed bias JFET in Proteus

viii. Hit the simulation button and note the readings.

c) Voltage divider Biasing:

ix. Create a circuit as shown below in Fig.8.

Fig. 8: Voltage divider bias JFET in Proteus

x. Hit the simulation button and note the readings.

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II- For MOSFETs:
a) Fixed Biasing:
xi. Create a circuit as shown below in Fig. 9.

Fig. 9: Fixed bias MOSFET in Proteus

xii. Hit the simulation button and note the readings.

b) Voltage divider Biasing:

xiii. Create a circuit as shown below in Fig.10.

Fig. 10: Voltage divider bias MOSFET in Proteus

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xiv. Hit the simulation button and note the readings.

6. Proteus Simulation:
I- For JFETs:
a) Self Biasing:

Fig. 11: Self Bias JFET in Proteus

b) Fixed Biasing:

Fig. 12: Fixed bias JFET in Proteus

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c) Voltage divider Biasing:

Fig. 13: Voltage divider bias JFET in Proteus

II- For MOSFETs:

a) Fixed Biasing:

Fig. 14: Fixed bias MOSFET in Proteus

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b) Voltage divider Biasing:

Fig. 15: Voltage divider bias MOSFET in Proteus

7. Conclusion:
The purpose of biasing is to select the proper DC gate-to-source voltage to establish a desired
value of drain current and, thus, a proper Q-point. Three types of bias are self-bias, voltage-divider
bias, and current-source bias.
The bias circuit stabilizes the operating point of the transistor for variations in transistor
characteristics and operating temperature. A JFET must be operated such that the gate-source
junction is always reverse-biased. This condition requires a negative 𝑉𝐺𝑆 for an n-channel JFET and
a positive 𝑉𝐺𝑆 for a p-channel JFET. This can be achieved using the self-bias arrangements.
The similarities in appearance between the transfer curves of JFETs and depletion type
MOSFETs permit a similar analysis of each in the dc domain. The primary difference between the
two is the fact that depletion-type MOSFETs permit operating points with positive values of VGS
and levels of ID that exceed IDSS. In fact, for all the configurations discussed thus far, the analysis is
the same if the JFET is replaced by a depletion-type MOSFET.
The equation to check results of biasing is,

𝑉𝐷𝑆 = 𝑉𝐷𝐷 − 𝐼𝐷 (𝑅𝐷 + 𝑅𝑆 )

………………………………………………………
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