This document provides an overview of MOS field-effect transistors (MOSFETs). It begins by introducing transistors and comparing bipolar junction transistors (BJTs) to field-effect transistors (FETs). The document then focuses on MOSFETs, describing their physical structure, types (N-channel, P-channel), and key characteristics. Several figures show the structure and operation of enhancement-type NMOS transistors. The document also compares MOSFET operation in different regions (triode, saturation) and provides examples of MOSFET circuits at DC. It concludes with an overview of biasing techniques for MOSFET amplifiers.
This document provides an overview of MOS field-effect transistors (MOSFETs). It begins by introducing transistors and comparing bipolar junction transistors (BJTs) to field-effect transistors (FETs). The document then focuses on MOSFETs, describing their physical structure, types (N-channel, P-channel), and key characteristics. Several figures show the structure and operation of enhancement-type NMOS transistors. The document also compares MOSFET operation in different regions (triode, saturation) and provides examples of MOSFET circuits at DC. It concludes with an overview of biasing techniques for MOSFET amplifiers.
This document provides an overview of MOS field-effect transistors (MOSFETs). It begins by introducing transistors and comparing bipolar junction transistors (BJTs) to field-effect transistors (FETs). The document then focuses on MOSFETs, describing their physical structure, types (N-channel, P-channel), and key characteristics. Several figures show the structure and operation of enhancement-type NMOS transistors. The document also compares MOSFET operation in different regions (triode, saturation) and provides examples of MOSFET circuits at DC. It concludes with an overview of biasing techniques for MOSFET amplifiers.
This document provides an overview of MOS field-effect transistors (MOSFETs). It begins by introducing transistors and comparing bipolar junction transistors (BJTs) to field-effect transistors (FETs). The document then focuses on MOSFETs, describing their physical structure, types (N-channel, P-channel), and key characteristics. Several figures show the structure and operation of enhancement-type NMOS transistors. The document also compares MOSFET operation in different regions (triode, saturation) and provides examples of MOSFET circuits at DC. It concludes with an overview of biasing techniques for MOSFET amplifiers.
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UNIT-4
MOS FIELD-EFFECT TRANSISTORS ( MOSFETS) Introduction Transistors (Three Terminal Devices)
BJTS (Bipolar Junction Transistors) FET (Field Effect Transistor)
NPN PNP JFET MOSFET MESFET
N-Channel P-Channel Enhancement type Depletion type
N-Channel P-Channel N-Channel P-Channel
Comparison Between BJTs & FETs
BJTs FETs
1. Current Controlled Voltage Controlled
device Device
BJT FET D B G
E S 2. Bipolar device Unipolar device
3. Has low I/P impedance
Has high I/P impedance 4. Occupies more space
Occupies less space
5. Stability against temperature is less More temperature stable than BJT
6. AC voltage gains for
BJT amplifier is more AC voltage gain for FET amplifier is less 7. Highly susceptible to Less susceptible to less more noise. noise.
8. IC = ßIB ID = IDss (1-VGS/Vp )
IC = I E ID = I S
VBE = 0.7V (starting point for IG = 0A analysis) (starting point for analysis) 9. Power dissipation Power dissipation is is more. less.
10. Used in Used in amplifiers,
amplifiers, switches, filters , switches, digital memory, digital logic logic & memory. Ics such as microprocessor, microcontrollers, signal processors, etc. FIG 4.1 SHOWS THE PHYSICAL STRUCTURE OF ENHANCEMENT TYPE NMOS TRANSISTOR ; PERSPECTIVE VIEW. TYPICALLY L=0.1 TO 3μm, W=0.2 TO 100μm, AND THE THIC KNESS OF THE OXIDE LAYER (tox) IS IN THE RANGE OF 2 TO 50 nm. FIG 4.1 (B)PHYSICAL STRUCTURE OF ENHANCEMENT TYPE NMOS TRANSISTOR----- CROSS SECTIONAL VIEW.
Another name for the MOSFET is the insulated-gate FET or IGFET.
MOS FET FEATURES L is in the range of 0.1 µm to 3 µm, and W is in the range of 0.2 µm to 100µm. note that the MOSFET is a symmetrical device; thus its source and drain can be interchanged with no change in device characteristics Operation with No Gate Voltage These back -to-back diodes prevent current conduction from drain to source when a voltage VDS is applied In fact, the path between drain and source has a very high resistance (of the order of 10to power of 12 Ω). FIG 4.2 SHOWS THE ENHANCEMENT TYPE NMOS TRANSISTOR WITH A POSITIVE VOLTAGE APPLIED TO THE GATE. AN N CHANNEL IS INDUCED AT THE TOP OF THE SUBSTRATE BENEATH THE GATE. FIG 4.3 SHOWS AN NMOS TRANSISTOR WITH VGS > Vt AND WITH A SMALL VDS APPLIED. THE DEVICE ACTS AS A RESISTANCE WHOSE VALUE IS DETERMINED BY VGS. FIG 4.4 SHOWS THE ID-VDS CHARACTERISTICS OF THE MOSFET. FIG 4.5 SHOWS THE OPERATION OF THE ENHANCEMENT NMOS TRANSISTOR AS VDS IS INCREASED. THE INDUCED CHANNEL ACQUIRES A TAPERED SHAPE, AND ITS RESISTANCE INCREASES AS VDS IS INCREASED. HERE VGS IS KEPT CONSTANT AT VALUE > Vt FIG 4.6 SHOWS THE DRAIN CURRENT ID VERSUS THE DRAIN-TO-SOURCE VOLTAGE VDS FOR AN ENHANCEMENT- TYPE NMOS TRANSISTOR OPERATED WITH VGS>Vt. ACQUIRE A TAPERED SHAPE. EVENTUALLY, AS VDS REACHES VGS-Vt, THE CHANNEL IS PINCHED OFF AT HE DRAIN END. INCREASING VDS-Vt HAS LITTLE EFFECT(THEORETICALLY, NO EFFECT) ON THE CHANNEL’S SHAPE. FIG 4.8 SHOWS THE DERIVATION OF THE ID-VDS CHARACTERISTICS OF THE NMOS TRANSISTOR. FIG 4.9 SHOWS THE CROSS SECTION OF A CMOS INTEGRATED CIRCUIT. NOTE THAT THE PMOS TRANSISTOR IS FORMED IN A SEPERATE n-TYPE REGION, KNOWN AS AN n-WELL. ANOTHER ARRANGEMENT IS ALSO POSSIBLE IN WHICH AN n-TYPE BODY IS USED AND THE N DEVICE IS FORMED IN A p-WELL. ENHANCEMENT-TYPE MOSFET. FIG(B) SHOWS THE MODIFIED CIRCUIT SYMBOL WITH AN ARROWHEAD ON THE SOURCE TERMINAL TO DISTINGUISH IT FROM THE DRAIN AND TO INDICATE DEVICE POLARITY (n-CHANNEL). FIB(C) SHOWS THE SIMPLIFIED CIRCUIT SYMBOL TO BE USED WHEN THE SOURCE IS CONNECTED TO THE BODY OR WHEN THE EFFECT OF THE BODY ON DEVICE OPERATION IS UNIMPORANT. OPERATING THE MOS TRANSISTOR IN THE SUBTHRESHOLD REGION
n-channel MOSFET, for VGS< Vt, no current
flows and the device is cut off. been found that for values of VGS smaller than but close to
Vt, a small drain current flows.
In this subthreshold region of operation the drain current is exponentially related to VGS there are special, but a growing number of, applications that make use of subthreshold operation MOSFET WITH VGS AND VDS APPLIED AND WITH THE NORMAL DIRECTIONS OF CURRENT FLOW INDICATED. FIG (B) SHOWS THE ID-VDS CHARACTERISTICS FOR A DEVICE WITH K’n(W/L)=1.0 mA/V2. FIG 4.12 THE ID-VGS CHARACTERISTICS FOR AN ENHANCEMENT-TYPE NMOS TRANSISTOR IN SATURATION(Vt=1V, K’N W/L=1.0mA/V2) FIG 4.13 SHOWS THE LARGE SIGNAL EQUIVALENT –CIRCUIT MODEL OF AN n-CHANNEL MOSFET OPERATING IN THE SATURATION REGION. TERMINAL VOLTAGES OF THE ENHANCEMENT NMOS TRANSISTOR FOR OPERATION IN THE TRIODE REGION AND IN THE SATURATION REGION. FINITE OUTPUT RESISTANCE IN SATURATION FIG 4.18 (A) SHOWS THE CIRCUIT SYMBOL FOR THE P-CHANNEL ENHANCEMENT TYPE MOSFET.(B) MODIFIED SYMBOL WITH AN ARROWHEAD ON THE SOURCE LEAD. (C) SIMPLIFIED CIRCUIT SYMBOL FOR THE CASE WHERE THE SOURCE IS CONNECTED TO THE BODY . (D) THE MOSFET WITH VOLTAGES APPLIED AND THE DIRECTIONS OF THE CURRENT FLOW INDICATED. NOTE THAT VGS AND VDS ARE NEGATIVE AND ID FLOWS OUT OF THE DRAIN TERMINAL. FIG 4.19 SHOWS THE RELATIVE LEVELS OF THE TERMINAL VOLTAGES OF THE ENHANCEMENT TYPE PMOS TRANSISTOR FOR OPERATION IN THE TRIODE REGION AND IN THE SATURATION REGION. 4.4 An enhancement type NMOS transistor with Vt=0.7V has its source terminal grounded and a 1.5V dc applied to the gate. In what region does the device operate for a) VD=0.5V b) VD= 0.9V c) VD=3V
solution: The MOSFET operates in- triode region when VDS<VOv and in saturation region when VDS>VOV
hereVov=VGS-Vt= 1.5 - 0.7=0.8V
case a) when VD=VDS=0.5V is applied
VDS<VGS-Vt
Device operates in triode region.
Case b) when VDS=0.9V
VDS> VGS -Vt
Device operates in saturation region.
Case c) when VDS=3V
VDS> VGS-Vt MOSFET CIRCUITS AT DC EXAMPLE 4.2 SOLUTION FOR EXAMPLE 4.2 EXAMPLE 4.3 SOLUTION FOR EXAMPLE 4.3 EXAMPLE 4.4 EXAMPLE 4.5 SOLUTION FOR EXAMPLE 4.5 EXAMPLE 4.6 SOLUTION FOR EXAMPLE 4.6 FIG 4.26 (a) SHOWS THE BASIC STRUCTURE OF THE COMMON SOURCE AMPLIFIER. (b) SHOWS THE GRAPHICAL CONSTRUCTION TO DETERMINE THE TRANSFER CHARACTERISTIC OF THE AMPLIFIER IN (a). FIG4.26 (C) SHOWS THE TRANSFER CHARACTERISTICS SHOWING OPERATION AS AN AMPLIFIER BIASED AT POINT Q. LARGE-SIGNAL OPERATION-THE TRANSFER CHARACTERISTIC Biasing by Fixing V GSBiasing by Fixing V GSBiasing by Fixing V GS
B I AS I N G I N M O S A M P L I FI ER C I RCU I TS
An appropriate dc operating point or bias point is characterized
by a stable and predictable dc drain current ID and by a dc drain-to-source voltage V DS that ensures operation in the saturation region for all expected input-signal levels
Biasing by Fixing V GS FIG 4.27 SHOWS THE TWO LOAD LINES AND CORRESPONDING BIAS POINTS. BIAS POINT Q1 DOES NOT LEAVE SUFFICIENT ROOM FOR POSITIVE SIGNAL SWING AT THE DRAIN (TOO CLOSE TO VDD).BIAS POINT Q2 IS TOO CLOSE TO THE BOUNDARY OF THE TRIODE REGION AND MIGHT NOT ALLOW FOR SUFFICIENT NEGATIVE SIGNAL SWING. FIG 4.29 SHOWS THE USE OF FIXED BIAS (CONSTANT VGS) CAN RESULT IN A LARGE VARIABILITY IN THE VALUE OF ID. DEVICES 1 AND 2 REPRESENT EXTREMES AMONG UNITS OF THE SAME TYPE. FIG 4.30 SHOWS BIASING USING A FIXED VOLTAGE AT THE GATE, VG, AND A RESISTANCE IN THE SOURCE LEAD, RS, (a) BASIC ARRANGEMENT; (b) REDUCED VARIABILITY IN ID; FIG 4.30 SHOWS BIASING USING A FIXED VOLTAGE AT THE GATE, VG, AND A RESISTANCE IN THE SOURCE LEAD, RS, (c) PRACTICAL IMPLEMENTATION USING A SINGLE SUPPLY; (d) COUPLING OF A SIGNAL SOURCE TO THE GATE USING A CAPACITOR CC1; (e) PRACTICAL IMPLEMENTATION USING TWO SUPPLIES. FIG 4.32 SHOWS THE BIASING OF THE MOSFET USING A LARGE DRAIN TO GATE FEEDBACK RESISTOR RG. FIG 4.33(a) SHOWS THE BIASING THE MOSFET USING A CONSTANT-CURRENT SOURCE I.(b) IMPLEMENTATION OF THE CONSTANT-CURRENT SOURCE I USING A CURRENT MIRROR.
(Ebook) A First Course on Electronic Engineering by A. Mathew; Bensiker Raja Singh; Mercy Priya; Bensikar R. D. Singh ISBN 9781783320547, 1783320540 download pdf
(Ebook) A First Course on Electronic Engineering by A. Mathew; Bensiker Raja Singh; Mercy Priya; Bensikar R. D. Singh ISBN 9781783320547, 1783320540 download pdf
