V DR - RR&DR - SR Techincal University Lab Manual: Eltech
V DR - RR&DR - SR Techincal University Lab Manual: Eltech
DR.RR&DR.SR TECHINCAL
UNIVERSITY
LAB MANUAL
SEMICONDUCTOR DEVICES
LIST OF EXPERIMENTS
1.Input and output characteristics of BJT for all Configurations
2.To find out the drain resistance and transconductance of JFET
3.to find gthe scr characteristics and its parameters
4.to find the intrinsic standoff ratioof ujt
5.to de
EX.NO:3 CHARACTERISTICS OF JFET
APPARATUS
1. JFET BFW10
2. Voltmeter (0-39)v,(0-10)v
3. Ammeter (0-50)ma
4. DCPS
5. Bread board
6. Connecting wires
THEORY:
CHARACTERISTICS OF JFETS
(1) The maximum saturation drain current becomes smaller because the
conducting channel now becomes narrower.
(2) Pinch-off voltage is reached at a lower value of drain current I D than when
VGS = 0. When an external bias of, say – 1 V is applied between the gate and the
source, the gate-channel junctions are reverse-biased even when drain current,
ID is zero. Hence the depletion regions are already penetrating the channel to a
certain extent when drain-| source voltage, VDS is zero. Due to this reason, a
smaller voltage drop along the channel (i.e. smaller than that for VGS = 0) will
increase the depletion regions to the point where 1 they pinch-off the current.
Consequently, the pinch-off voltage VP is reached at a lower 1 drain current,
ID when VGS = 0.
1 V is applied, the gate-channel junctions still require -4 V to achieve pinch-off. It means that a 3 V drop is now required along the
channel instead of the previous 4.0 V. Obviously, this drop of 3 V can be achieved with a lowervalue of drain current, Similarly when
VGS = – 2 V and – 3 V, pinch-off is achieved with 2 V and 1 V respectively, along the channel. These drops of 2 V and 1 V are, of
course, achieved with further reduced values of drain current, ID. It is further observed that when the gate-source bias is numerically equal
to pinch-off voltage, VP (-4 V in this case), no channel drop is required and, therefore, drain current, ID is zero. The gate-source
bias voltage required to reduce drain current, ID to zero is designated the gate-source cut-off voltage, VGS /0FF) and, as explained,
jfet-transfer-characteristic
2. Transfer Characteristic of JFET
The transfer characteristic can also be derived from the drain characteristic by
noting values of drain current, ID corresponding to various values of gate-source
voltage, VGS for a constant drain-source voltage and plotting them.
It may be noted that a P-channel JFET operates in the same way and have the
similar characteristics as an N-channel JFET except that channel carriers are
holes instead of electrons and the polarities of VGS and VDS are reversed.
Tabular form
Drain resistance:
Vgs= Vgs=
Vds Id Vds Id
Transconductance:
Vds=
Vgs Id
RESULT:
Thus JFET has a very high input resistance and amplification factor greater than
unity.
AIM
To plot the characteristics of UJT and to determine the intrinsic standoff ratio from the graph.
1. UJT
2. Resistors
3. Voltmeter
4. Ammeter
5. Rheostat
6. Power supply
CIRCUIT DIAGRAM
THEORY
UJT is the Uni Junction Transistor. It is a three terminal device. They are: a) emitter b)
base1 c)base2.The equalent circuit is shown with the circuit diagram. So there are two resistors. One
is a variable resistor and other is a fixed resistor. The ratio of internal resistances is referred as
intrinsic standoff ratio (η).It is defined as the ratio of the variable resistance to the total resistance.
Due to the existing pn junction, there will be a voltage drop. If we apply a voltage to the emitter, the
device will not turn on until the input voltage is less than the drop across the diode plus the drop at
the variable resistance R1.When the device is turned on holes moves from emitter to base resulting in
a current flow. Due to this sudden increase in charge concentration in base1 region conductivity
increases. This causes a drop at base1.This region in the graph is known as negative resistance region.
If we further increase the emitter voltage the device undergoes saturation. So a UJT has 3 operating
regions:
PROCEDURE
1. Set up the circuit as shown in the circuit diagram
3. By varying the input voltage, take the values of voltage and current values
OBSERVATIONS
VE IE VE IE
GRAPH
CALCULATIONS
VBB=12 V
VP= Vd + ηvbb
η = Vp – Vd/VBB
Similarly find the value of intrinsic standoff ratio for all values of VBB.
RESULT
Characteristics of UJT were plotted and intrinsic standoff ratio was found.
η = ………………..
AIM
1. Transistor
3. Resistors
4. Voltmeters
5. Ammeters
CIRCUIT DIAGRAM
THEORY
PROCEDURE
3. Make the voltage at collector emitter as zero and vary the rheostat at input side in small
steps
4. Do the above step for other collector –emitter voltages (eg: Vce=3 V, Vce=5 V) and
tabulate the readings.
5. Switch off the power supplies and switch on the supplies and make the input current at 40
uA.
6. By varying the rheostat at output note down the readings of ammeter and voltmeter
readings.
7. Repeat the above step, for a few number of times for various base current values
(eg:IB =60 uA)
9. Calculate the dynamic input resistance, dynamic output resistance and common emitter
current gain.
OBSERVATIONS
IB VBE IB VBE
GRAPH
1. INPUT CHARACTERISTICS
2.OUTPUT CHARACTERISTICS
CALCULATIONS
Dynamic input resistance= slope of input characteristics=………..
Dynamic output resistance=slope of out put characteristics=……..
RESULT
\
AIM
1. Transistor
3. Resistors
4. Voltmeters
5. Ammeters
CIRCUIT DIAGRAM
THEORY
PROCEDURE
3. Make the voltage at collector emitter as zero and vary the rheostat at input side in small
steps
4. Do the above step for other collector –emitter voltages (eg: Vce=3 V, Vce=5 V) and
tabulate the readings.
5. Switch off the power supplies and switch on the supplies and make the input current at 40
uA.
6. By varying the rheostat at output note down the readings of ammeter and voltmeter
readings.
7. Repeat the above step, for a few number of times for various base current values
(eg:IB =60 uA)
9. Calculate the dynamic input resistance, dynamic output resistance and common emitter
current gain.
OBSERVATIONS
IE VBE IE VBE
GRAPH
2.OUTPUT CHARACTERISTICS
CALCULATIONS
Dynamic input resistance= slope of input characteristics=………..
RESULT
AIM
1. Transistor
3. Resistors
4. Voltmeters
5. Ammeters
CIRCUIT DIAGRAM
THEORY
PROCEDURE
3. Make the voltage at collector emitter as zero and vary the rheostat at input side in small
steps
4. Do the above step for other collector –emitter voltages (eg: Vce=3 V, Vce=5 V) and
tabulate the readings.
5. Switch off the power supplies and switch on the supplies and make the input current at 40
uA.
6. By varying the rheostat at output note down the readings of ammeter and voltmeter
readings.
7. Repeat the above step, for a few number of times for various base current values
(eg:IB =60 uA)
9. Calculate the dynamic input resistance, dynamic output resistance and common emitter
current gain.
OBSERVATIONS
IB VBE IB VBE
CALCULATIONS
Dynamic input resistance= slope of input characteristics=………..
RESULT
CHARACTERISTICS OF SCR
AIM:To draw the characteristics of SCR and to calculate gate current(IG)
COMPONENTS:
Power supply (0-30)v-2
Resistor 1KΩ-2
Ammeter (0-50) m A-2
SCR-1
Voltmeter (0-30) v -1
THEORY:
SCR acts as a switch when it is forward biased when the gate is kept open
IG=0.Operation of SCR is similar to PN diode .When IG>0, the amount of
reverse
Bias applied.I2 decreased very low voltage such that the characteristics of SCR
is similar
to that of of ordinary PN diode.
Once the SCR is turned ON , the gate loses control the gate cannot be used to
switch the device off.
PROCEDURE:
1. Connections are made as shown in the circuit diagram.
2. Power supply and voltage to gate is increased to make the voltmeter reading
zero.
3. The voltmeter is used to get supply and it is increased
4. The corresponding voltmeter and ammeter readings are noted.
5. A graph is plotted by taking voltage along x-axis and current along Y- axis.
CIRCUIT
TABULAR FORM
Vg=
IC Vak
Result:
Thus the firing characteristics of SCR and the calculations of gate current are
studied.