Ec Unit 1
Ec Unit 1
Ec Unit 1
Transistor as an amplifier
v When an Input ac signal only is supplied to the circuit (without any dc) as
shown in figure , during positive half cycle of input (Vin > Vb) then
input junction becomes forward biased results in current flows from emitter to
base then base to collector circuit
v During negative half cycle of input, the junction becomes reverse biased so, no
current flows in the circuit, results in negative cycle is not amplified as shown
in figure.
v The resultant output is the unfaithful or distorted (i.e., input and output shape
are not same).
Thus, to obtain faithful amplification the following three conditions needs to
be satisfied:
iii) there should be proper zero signal (i.e., ac input is present or not) collector
current
v The proper flow of zero signal dc collector current (proper operating point of a
transistor) and the maintenance of proper collector-emitter voltage during the
passage of signal is known as transistor biasing.
v It is important to note that the an input voltage should be smaller than the
biasing voltage, otherwise the above mentioned problem respects at every
cycle.
Stabilisation
v The maintenance of the operating point as constant is known as ‘stabilization’.
There are two techniques used for maintain the Q point as constant.
v (1) Stabilization technique:
This technique consists of a biasing circuit which permits a variation of
base current Ib so as to maintain Ic almost constant in spite of variation of Ico,
and Vbe.
Stability Factor:
v There are different compensation and stabilization techniques to compare the
biasing circuit a common factor called stability factor is used.
There are three stability factors
v 1. The stability factor S is defined as the rate of change of collector current
with respect to the reverse saturation current Ico keeping and VBE
constant, i.e.,
3. Stability Factor Sv: This is defined as the rate of change of Ic with respect to
Vbe, keeping Ib and constant i.e.,
v To find the value of resistance Rb apply the KVL to the closed circuit (input
circuit) ABKLA, then we have
Stability Factor ‘S
The stability factor ‘S can be defined as rate of change of collector current Ic w.r.t
reverse saturation current Ico, assume and VBE are constants.
INPUT CIRCUIT
Here Ic is almost independent of transistor parameters , Ib and Ico and hence good
stabilization is ensured. The collector emitter voltage Vce can be calculated as
follows:
OUTPUT CIRCUIT
The zero volt drop across Rg permits replacing Rg by a short circuit equivalent.
Apply KVL to the input circuit
If VGG is fixed then VGS is also fixed in magnitude resulting in “fixed bias
configuration”. The dc levels of voltage VGS and current ID can be determined as
follows.
VDS+IDRD=VDD (2)
VDS=VDD-IDRD (3)
We know
VDS=VD-VS if VS=0
VDS=VD (4)
Hence from equation (3) we get IDQ= VDD- VD/RD
In addition VGS=VG-VS
VGQ =VGS
The graphical analysis of FET biasing as follows
(a)JFET Self bias configuration (b)DC analysis of the self bias configuration
v In this case VGS is a function of the output current ID and not fixed in
magnitude like fixed bias configuration.
v The equation (1) and Shockkly equation relates the same two variables
ID and V GS permitteng either a mathematical or graphical solution
v . The mathematical analysis can be obtained as follows, Shockkly’s
equation is given by
Small signal analysis of CE arnplifier
v A small signal amplifier can be defined as the amplifier in which
input signal is so weak as to produce small fluctuations in the
collector current compared to its Q’ point value. It has only one
amplifying device.
v Based on the transistor configuration small signal amplifiers are
classified as CE, CC and CB amplifiers. In this chapter we will study
the analysis of small signal amplifier using different biasing.
Need for capacitance coupling in amplifiers
v Assuming all the three capacitors have impedances which are
extremely small at signal frequencies, each capacitor can be
considered as short circuit for ac signal and open circuit for dc.
v If the signal source were directly coupled to the transistor base,
source resistance Rs would be directly in parallel with resistor R2.
This would reduce the bias voltage at the transistor base end and,
consequently alter the collector current.
v Similarly if RL is directly connected to the transistor collector, the
Rc is in parallel with RL thus the dc levels of Vc and Vce would
be affected. Therefore coupling capacitors C1and C2 function as
open circuits to dc and short Circuits to ac.
The following steps are followed to obtain the small
signal equivalent circuit:
v i. Start with complete circuit diagram
v ii. Assume all the capacitors, which are large enough can be
considered to be short circuit such capacitors are used as coupling
capacitors between input, output and bypass capacitor.
v iii. Replace the dc power supply by.a short circuit.
v iv. Replace the transistor by its h parameter model.
v Connect all other circuit elements with h parameter model thus
the small signal equivalent circuit is obtained.
Construction
.1. A common emitter athplifier circuit is shown in fig. .The circuit
coxnsist of biasing tesistorR1 and R2 temperature stabilization
resistor Re, coil load resistor Rc
2. The circuit uses bypass capacitor C to eliminate ac degeneration.
3. The signal source is connected to the transistor base via coupling
capacitcor C1 &capacitor C2 couples external load resistor RL to the
transistor collector.
CE amplifier
fig.(a)
Class AB: current flows for more than one half cycle but less than full cycle
(180o<θ<360).
Class B: Current flows for one half cycle (180 o)
Class C: Current flows for less than one half cycle (θ<180o)
v V1/I1 represents the effective load resistance or the resistance seen looking into
the primary of the transformer and is designated as R’L. On the other hand,
V2/I2 represents the value of load resistance (i.e., RL).
v Therefore the equation (i) may be rewritten as,
§
The maximum value of overall or collector efficiency of a transformer coupled
class-A amplifier is 50%.
Proof:
Average power delivered by the d.c. supply,
Overall efficiency,
Pushpull operation
v The input signal is applied to the inputs of the two transistors through a tapped
transformer T1 ,The voltages at the base of the two transistors Q1& Q2 are in
pushpull. ie in phase opposition.
v That is when signal on transistor Q1 is positive, the signal at Q2 is negative an
equal amount. It can be easily obtained by centre tapped transformer.
v However, instead of such a centre tapped transformer, we may alter use other
circuit which provides two equal ‘voltages differing in phase
The collector of transistor Q1 (fourier series) is given by
v The currents i1 and i2 are flowing through the primary winding of the output
former T2 in opposite direction.
v Thus the total current in the secondary is proportional to the difference
between the two currents i1 and i2
This expression shows that a pushpull circuit will balances out all even harmonics
in the output and out of odd harmonics only third harmonic term produce
The. Significant contribution of distortion, thus all other higher harmonics are
neglected.
v The expressions for quantities such as voltage gain, current gain, power gain,
input impedance and output impedance of this ‘n’ stage CE amplifier are to be
derived.
VOLTAGE GAIN:
v In a multistage amplifier the output voltage of the first stage acts as the input
v voltage of second stage and so on.
v The voltage gain of the complete cascade amplifier is equal to the product of
the voltage gains of the individual stages.
v The voltage gain of the first stage is:
Similar expressions can be written for all ‘n’ stages of the cascade amplifier.
The gain of the overall cascade amplifier is the product of the stage gains Av1 and
Av2.
where