Transistor Biasing:

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VOLTAGE DIVIDER CIRCUIT

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TRANSISTOR BIASING AND STABILIZATION:

Review of transistor:
The transistor can be operated in three regions: cut-off active and saturation
by applying proper biasing conditions as shown in the table:
Region of operation Emitter base junction Collector base junction
Cut-off Reverse biased Reverse biased
Active Forward biased Reverse biased
Saturation Forward biased Forward biased

In order to operate transistor in the desired region we have to apply external

d.c. voltages of correct polarity and magnitude to the two junctions of the
transistor. This is nothing but the biasing of the transistor. Because d.c
voltages are used to bias the transistor, biasing is known as d.c. biasing of the
transistor.
Operating point: Q point
when we bias a transistor, we establish a certain current and voltage conditions
for the transistor. These conditions are known as operating conditions to d.c
operating point or equivalent point. The operating point must be stable for
proper operation of the transistor. The transistor parameter β, ICO, and VBE, are
temperature dependent, the operating point also varies with changes in
temperature.

Analysis of Fixed bias circuit:

The Fig. shows the fixed bias circuit. It is the simplest d.c bias configuration.
For the d.c. analysis we can replace capacitor with an open circuit because the
reactance of a capacitor for d.c is Xc=1/2πfC = Xc=1/2π(0)C = ∞. The d.c
equivalent of fixed bias circuit is shown in fig.

Circuit Analysis:
Base Circuit:
Let us consider the base circuit as shown in Fig.
Applying Kirchhoff’s voltage law to the base circuit we get,
VCC – IBRB – VBE = 0
Solving for the current IB,
𝑉𝐶𝐶−𝑉𝐵𝐸
IB = 𝑅𝐵

Collector circuit:

We now consider the collector circuit as shown in Fig. Applying Kirchhoff’s

voltage law to the collector circuit we get.
VCC – ICRC – VCE = 0
∴ VCE =VCC – ICRC ……(1)
The magnitude of collector current is given by
IC = βIB
And from the above equation (1) we get
𝑉𝐶𝐶−𝑉𝐶𝐸
IC = 𝑅𝐶

It is important to note that the base current is controlled by the value of

resistor RB
IC is related to IB by a constant β.
The magnitude of the IC is not a function of the resistance RC. Changing RC to
any level will not effect the level of IB or IC as long as we remain in the active
region of the device.
However the change in RC will change the value of VCE.
VCE =VC – VE
Similarly
VBE =VB – VE
where VC :collector voltage, VE = Emitter voltage, VB = Base voltage.
In this circuit, VE = 0
∴ VBE = VB VCE = VC
This figure shows the output characteristics of a common emitter configuration
with points A and B, and line drawn between them. The line drawn between
points A and B is called d.c. load line.
The d.c. load line is a plot of IC versus VCE. For a given value of RC and a given
level of VCC. Thus, it represents all collector current levels and corresponding
collector-emitter voltages that can exist in the circuit. Knowing any one of IC, IB
or VCE, it is easy to determine the other two from the load line. The slope of
the d.c load line depends on the value of Rc, it is negative and equal to
reciprocal of the RC.
Applying Kirchoff’s voltage law to the base circuit of Fig.

We get,
VCC – IBRB – VBE = 0
∴IB RB = VCC – VBE
 𝑉𝐶𝐶−𝑉𝐵𝐸
∴IB = 𝑅𝐵

The interaction of curves of different values of IB with dc load line gives

different operating points. For different values of IB, we have different
intersection points such as P, Q and R.

Selection of operating point:

The operating point can be selected at different positions on the d.c load line:
near saturation region, near cutoff or near active. Shown in figure. The
selection of operating point will depend on its application.

When transistor is used as an amplifier, the Q point should be selected at the

center of the d.c load line to prevent any possible distortion in the amplified
output signal.
CASE 1: Biasing circuit is designed to fix a Q point at point P is very near to the
saturation region. As shown in Figure the collector current is clipper at the
positive half cycle. So, even though base current varies sinusoidally, collector
current is not a useful sinusoidal waveform. i.e distortion is present at the
output. Therefore, point P is not a suitable operating point.

CASE 2: Biasing circuit is designed to fix a Q point at point R as shown in fig.

Point R is very near to the cut-off region. As shown in Fig. the collector current
is clipped at the negative half cycle. So, point R is also not a suitable operating
point.
CASE 3: Biasing circuit is designed to fix a Q point at point Q as shown in fig.
The output signal is sinusoidal waveform without any distortion. Thus point Q
is the best operating point.

Typical junction voltages and conditions for operating Region:

We have seen that, we can operate transistor configurations in different
operating regions by selecting appropriate operating point. For the analysis
and design of such circuits we should know the typical junction voltages in
different operating regions.
The table below shows the typical junction voltages for cut-off, active and
saturation regions for n-p-n silicon and germanium transistors. For pnp
transistors we have to reverse the polarities of voltages given in table.
Requirements of a biasing circuit:
1. The emitter-base junction must be forward biased (forward biased
voltage is 0.6 to 0.7V) and collector-base junction must be reverse biased
(within maximum limits). i.e. the transistor should be operated in the
middle of the active region operating point (Q point) should be fixed at
the center of the active region.
2. The circuit design should provide a degree of temperature stability.
3. The operating point should be made independent of the transistor
parameters (such as β).
To maintain the operating point stable by keeping IC and VCE constant so that
the transistor will always work in active region, the following techniques are
normally used:
1) Stabilization techniques
2) Compensation techniques
1.Stabilization techniques refer to the use of resistive biasing circuits which
allow IB to vary so as to keep IC relatively constant with variations in ICO , β and
VBE.
2.Compensation techniques refer to the use of temperature-sensitive devices
such as diodes, transistor, thermistor, etc., which provide compensating
voltages and currents to maintain the operating point stable.
Advantages of Fixed bias circuit:
1. This is a simple circuit which uses very few components.
2. The operating point can be fixed anywhere in the active region of the
characteristics by simply changing the value of RB. Thus, it provides
maximum flexibility in the design.
Disadvantages of Fixed bias circuit:
1. This circuit does not provide any check on the collector current which
increased with the rise in temperature. i.e thermal stability is not
provided by this circuit. So the operating point is not maintained.
IC = βIB + ICEO
2. Since IC = βIB and IB is already fixed, IC depends on β which changes unit
to unit and shifts the operating point.
Thus stabilization of operating point is very poor in the fixed bias circuit.
Analysis of Emitter Stabilized Bias Circuit:
Circuit Analysis:
Base Circuit : Let us consider the base circuit shown in Fig.

Note that the only difference between the equation for IB and that obtained for
the fixed-bias configuration is the term βRE.
VB = VBE + VE or Vcc – IBRB
Since VE = IERE
VB = VBE + IERE

Collector Circuit: We now consider the collector circuit as

shown in fig.

Since VE = IERE
VCE = VC – VE
VC = VCC – ICRC.

Problems:
VCE = VCC – ICRC – IERE = 15 – 3.318 X 10-3 X 2 X 103 – 3.351 X 10-3X 1 X 103 = 5V
VC = VCC – ICRC = 15 – 3.318 X 10-3 X 2 X 103 = 8.364 V
VE = IERE = 3.351 X 10-3 X 1 X 103 = 3.351 V
VB = VBE + VE = 3.351 +0.7 = 4.051 V
VBC = VB – VC = 4.051 – 8.364 = -4.313V

Advantages and Disadvantages:

The addition of the emitter resistance, RE in the emitter bias circuit provides
improved stability, that is, the dc bias currents and voltages remain closer to
where they were set by the circuit against the changes in temperature and
transistor β.
The maximum stability is achieved when the ratio of RB and RE is as small as
possible. However, when stability is increased by increasing the value of RE,
negative feedback increases which reduces the gain of the circuit. We can also
increase stability by reducing value of RB, however, smaller values of RB needs
separate supply voltage and adds circuit complexity.

Analysis of Voltage Divider Bias circuit:

Fig. shows the voltage divider bias circuit.
In this circuit, the biasing is provided by three resistors: R1, R2 and RE.
The resistors R1 and R2 acts as a potential divider giving a fixed voltage to point
B which is base.
If collector current increases due change in temperature or change in β, the
emitter current IE also increases and the voltage drop across RE increases,
reducing the voltage difference between base and emitter (VBE). Due to
reduction in VBE, the base current IB and hence collector current IC also reduces.
Therefore, we can say that negative feedback exists in the emitter base circuit.
This reduction in IC compensates for the original change in IC.
DC Analysis:
Base Circuit:
Let us consider the base circuit as shown in fig.
VB = I2R2
If Ib is small, then neglect IB, hence
I=I1 I = I2
Vin = R1I + R2I = I(R1+R2)
Therefore I = Vcc/(R1+R2)
VB = Vcc x R2/ (R1+R2)

Voltage across R2 is the base voltage VB, Applying the voltage divider theorem
to find VB, we get,
𝑅2(𝐼)
VB = 𝑥𝑉𝐶𝐶
(
𝑅1 𝐼+𝐼𝐵 +𝑅2(𝐼))
𝑅
2
VB= 𝑅 +𝑅 𝑥 𝑉𝐶𝐶
1 2

Collector Circuit:
Now let us consider the collector circuit as shown in Fig.

Voltage across RE (VE) can be obtained as

VE = IERE = VB – VBE
𝑉𝐵−𝑉𝐵𝐸
𝐼𝐸 = 𝑅𝐸

Applying KVL to the collector circuit we get,

VCC – ICRC - VCE - IERE = 0
VCE = VCC – ICRC - IERE

Simplified circuit of Voltage Divider Bias:

Fig shows simplified circuit of voltage divider bias. Here R1 and R2 are
replaced by RB and VT, where RB is the parallel combination of R1 and R2 and
VT is the Thevenin’s voltage. RB can be calculated as:
𝑅2 𝑅1𝑅
VT= 𝑅 +𝑅 𝑥 𝑉𝐶𝐶 RB= 𝑅 +𝑅2
1 2 1 2

Applying KVL to the base circuit shown in fig. we get

VT = IBRB – VBE - IERE
We know that IE = (1+β)IB
VT = IBRB – VBE - (1+β)IBRE
𝑉𝑇−𝑉𝐵𝐸
∴ 𝐼𝐵 = 𝑅𝐵+(1+β)𝑅𝐸
Applying KVL to the collector circuit we get,
VCC – ICRC - VCE - IERE = 0
VCE = VCC – ICRC - IERE

Approximate Method:

The Fig. shows the input configuration for voltage divider bias circuit. If we
assume that current I2>>IB we can neglect IB and current I2 is equal to I1
Therefore, we have,
𝑅
2
VB= 𝑅 +𝑅 𝑥 𝑉𝐶𝐶
1 2

VE = IERE = VB – VBE
𝑉𝐸
𝐼𝐸 = 𝑅𝐸

And VCE = VCC – ICRC - IERE

We can approximate analysis when
(1+β)RE≥10R2 condition is satisfied. Under this condition results of exact and
approximate analysis are nearly same.

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Advantages and Disadvantages:
Voltage divider bias circuit provides excellent stabilization against variations in
temperature and transistor gain (β).
The negative feedback introduced by existence of RE reduces as gain; this
problem can be solved by using capacitor CE acts as a short circuit for ac inputs
and makes ac feedback equal to zero.