Electronic Devices & Circuits

(Unit – III / Biasing & Stabilization)

Prepared By
Dr. K. Umapathy

1
 Syllabus / Unit - III
• BIASING & STABILIZATION:
• DC Load line – Operating Point – Various Biasing
methods for BJT Design - Stability – Bias
Compensation-Thermal Stability – Design of
Biasing for JFET – Design of Biasing for MOSFET.

2
Introduction to Transistor Biasing

3
 Reason for Biasing
• Transistor used for a large variety of applications.
• For that, it is required to bias the transistor.
• Reason for biasing – to turn the device ON & place it in
the linear region of operation and provides a constant
amount of voltage gain.
• Biasing deals with – setting a fixed level of current with
a desired fixed voltage drop across the transistor
junctions.
• Base current, Collector current, Base-emitter voltage &
Collector-emitter voltages to be set by biasing circuits.
• By proper biasing – faithful amplification of weak
signals can be done.
4
 Proper Vs Improper Biasing
• Figure 1(a) – properly biased – signal variations at the
input reproduced at the output.
• Figure 1(b) – improperly biased – positive portion of
the input signal clipped – biased near the cut-off point.
• Figure 1(c) – improperly biased – negative portion of
the input signal clipped – biased near the saturation
point.

5
Fig 1 - Transistor Biasing

6
 Topic 1

DC Load Line & Operating Point -

BJT

7
Fig 1 – Collector Characteristics

8
 Introduction
• For proper operation of a transistor – a set of fixed
values of currents & voltages have to be set which
define a point called Operating point.
• Also called Quiescent point or simply Q point.
• Since the level of currents & voltages are fixed – called
dc operating point.
• In figure 1 (a) – the transistor biased with two dc
supplies – VCC & VBB to obtain the fixed values of
collector current, base current & Collector-emitter
voltage.
• Figure 1(b) – shows the collector characteristics curves
of a transistor.
9
 Drawing the DC Load line
• By adjusting the VBB supply set the base current initially
to 0.3 mA & note the corresponding value of collector
current- IC = β IB = 100 * 0.3 mA = 30 mA.
• Collector-emitter voltage VCE = VCC – ICRC = 10-6= 4V.
• The values of IC & VCE define an operating point at Q1.
• Similarly change the base current to 0.4 mA & 0.2 mA,
note the corresponding values of IC & VCE – set the
operating points at Q2 & Q3 respectively.
• Hence if the base current increases – collector current
increases & VCE decreases.
• If base current decreases – collector current decreases
& VCE increases.
• If the Q points – Q1, Q2 & Q3 extended – DC Load line. 10
Fig 2 – DC Load Line

11
 Observations from Load Line
• The load line intersects the horizontal axis at a point
marked VCC called transistor cut-off point or lower end
of the load line.
• At this cut-off point – IB & IC are zero.
• The load line intersects the vertical axis at a point
marked IC called transistor saturation point or lower end
of the load line.
• At this saturation point – IC maximum & VCE very small
which is equal to VCE(sat).

12
Fig 3 – DC Load Line with operating points

13
 Simple Way of Drawing Load Line
• If the values of VCC supply & the collector resistance RC
known – the dc load line can be easily drawn.
• The collector current given by – IC = VCC – VCE / RC
• At the saturation point - VCE very small when compared
to VCC supply & hence the collector current given by-
• IC(sat) = VCC / RC
• At the cut-off point – IC value zero & hence the collector
current given by - 0 = VCC – VCE / RC
• Or VCE = VCC = VCE(cut-off)
• the region between the saturation & cut-off points of
the load line called active region or linear region for
transistor operation.
14
Fig 4 – Q point & Maximum Undistorted Output

15
 Maximum Undistorted Output
• If the Q point not fixed properly on the load line – one
peak of the output signal will be clipped.
• If the Q point fixed near the saturation point – negative
peak of the input clipped at the output.
• If the Q point fixed near the cut-off point – positive peak
of the input clipped at the output.
• If the Q point fixed at the middle of the load line –
undistorted signal at the output.

16
 Factors affecting Q point
• 1) Inherent variations of transistor parameters:
• The collector current for a CE amplifier given by –
• IC = βIB + (1+β) ICO : β – common emitter current gain; ICO
– reverse saturation current: IB – base current
• The above variables strongly depend upon temperature.
• If temperature increases – these parameters also
increase thereby increasing the collector current –
moving the Q point towards the saturation point – signal
distortion at the output.
• 2) Variation in parameter values of transistors of same
type: Transistors of same type will have large variation in
parameters based upon specifications in the data sheet.
• This will give rise to instability in the Q point. 17
Transistor Biasing – Conditions &
Methods

18
 Conditions for Proper Biasing
• 1) Proper dc value of the collector current (IC)
• 2) Proper value of VBE – 0.7 V for Si & 0.3 V for Ge.
• 3) Proper value of VCE – 1 V for Si & 0.5 V for Ge.
• Conditions 1 & 2 make sure – Emitter-base junction forward
biased.
• Condition 3 make sure – Collector-base junction reverse
biased.
• Methods of Transistor Biasing
• 1) Base Bias (Fixed bias)
• 2) Base bias with emitter feedback (Emitter-feedback bias)
• 3) Base bias with collector feedback (Collector-feedback bias)
• 4) Voltage Divider Bias (Self-bias)
• 5) Emitter Bias 19
 Topic 2

Base Bias or Fixed Bias

20
Fig 1 – Base Bias

21
 KVL for Base Loop
• Figure 1(a) shows the base bias circuit for a NPN
transistor.
• Also called fixed bias circuit.
• Two supply voltages – VCC & VBB used in figure 1(a)
whereas one supply voltage in figure 1(b) and a
simplified supply in figure 1(c).
• Apply KVL to the base loop of the circuit – ABEGA

• The base current given by –

• Since the supply voltage VCC & Base-emitter voltage VBE
are fixed – the base current depends on RB only.
22
 KVL for Collector Loop
• Since VCC >> VBE –
• IB = VCC / RB
• Apply KVL to the collector loop of the circuit –ACEGA –

• The collector current given by –

• From the above equation, the collector current is β

times the base current and not dependent upon
résistance of the collector circuit.
• The values of IC & VCE depend upon the value of β
which in turn depend upon temperature. 23
 Stability Factor
• Hence Q point of a transistor vary with respect to
temperature.
• Impossible to have a stable Q point in a base biased
circuit.
• Hence this base biasing is not used for amplifier circuits
but used for switching circuits.
• The configuration employed for base biasing is CE
configuration – hence the stability factor for this biasing
given by –
• S=1+β

24
 Topic 3

Base Bias with Emitter Feedback

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Fig 1 – Base Bias with Emitter Feedback

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 Emitter Feedback Circuit
• Also called Emitter feedback bias.
• Figure 1 shows the circuit of base bias with emitter
resistor.
• The emitter resistor provides better bias stability than
the base bias circuit.
• When the current gain (β) increases due to temperature
– the collector current in the circuit also increases.
• It produces more voltage drop across the resistor RE
which in turn reduces the voltage drop across the base
resistor.
• Now the base current decreases – collector decreases.
• Thus increase in collector current due to increase in
current gain compensated. 27
 Emitter Feedback Circuit (contd)
• Hence the emitter resistor provides the compensation
for the variations in current gain by reducing the base
current.
• So RE called emitter feedback resistor.
• The above process effective only if RE large enough.
• But practically the value of RE small in order to avoid the
transistor going into saturation.

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 KVL to Base Loop
• Apply KVL to the base-emitter loop AFBEGA-

• Susbtituting IE equal to (β+1) IB in the above equation –

• The collector current given by-

• If RE very large when compared to (RE/β), the base circuit

independent of variations in current gain.
29
 KVL to Collector Loop
• Apply KVL to the Collector loop AFCEGA-
VCE + IE.RE – VCC + IC.RC = 0
• Replacing IE with IC in the above equation & solving for
Collector-emitter voltage –
VCE = VCC– IC (RC + RE)
• Hence some compromise to be done between bias
stability & performance of the circuit.

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 Stability factor for Base Bias with Emitter Feedback
• Apply KVL to the base-emitter loop of the circuit-

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 Topic 4

Base Bias with Collector Feedback

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Fig 1 – Base Bias with Collector Feedback

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 Feedback Resistor RB
• Figure 1 shows the dc bias circuit in which base resistor
connected to the collector terminal rather than to the
VCC supply.
• Hence the collector voltage biases the base-emitter
junction.
• RB acts as a feedback resistor.
• It provides a very stable Q point by reducing the effect of
variations in current gain (β).

34
 KVL to Base Loop
• Apply KVL to the base-emitter loop –
VBE – VCC (IB + IC) RC + IBRB = 0
• Substituting IC = β IB in the above & solving for IB –

• The collector current given by –

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 KVL to Collector Loop
• Apply KVL to the collector loop AFCEGA –

• Substituting (IC + IB) equal to IC in the above equation &

solving for Collector-emitter voltage-

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 Stability Factor of Collector-Feedback Bias
• Apply KVL to the base-emitter loop –

• Rearranging the above equation & solving for base

current –

• Differentiating with respect to IC –

• Substituting the value of dIB/dIC in general expression for

stability factor –

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 Stability Factor of Collector-Feedback Bias (contd)
• The stability factor of collector feedback bias is smaller
than (1+β).
• Hence this biasing method better than fixed bias
method.

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 Topic 5

Voltage Divider Bias (Self Bias)

39
Fig 1 – Voltage Divider Bias

40
 Introduction
• In the previous biasing methods, the dc bias current &
voltage of the collector depend upon the current gain (β)
of the transistor.
• But the value of current gain is temperature sensitive
especially for silicon transistors.
• Since the nominal value of (β) not defined properly, a dc
bias circuit independent of current gain is desirable.
• The dc bias circuit shown in figure 1 is very popular &
called Voltage Divider Bias or Self Bias.
• The name voltage divider derived from – R1 & R2 form a
potential divider across the VCC supply.
• The voltage drop across R2 forward biases the base-
emitter junction. 41
 Analysis of Base-emitter Loop
• Basic assumption is that – resistance looking into the
base terminal is much larger than that of resistor R2.
• Hence the current through R1 flows completely into R2 &
the two resistors considered to be effectively in series as
shown in Figure 1 (b).
• The base voltage at the transistor determined by the
potential divider of R1 & R2 and VCC supply.
• The base voltage given by –
VB = VCC * R2 / (R1+R2)
• Since the base-emitter voltage when forward biased is
small – the base voltage approximately equal to emitter
voltage --- VB = VBE + VE --- VB = VE
42
 Collector Current & Collector-Emitter Voltage
• The value of emitter current given by –
I E = VE / R E
• And the value of collector current –
IC = I E
The voltage at the collector wrt ground –
VC = VCC – IC * RC
The collector-emitter voltage given by –
VCE = VC – VE
= VCC – IC * RC – IE * RE
= VCC – IC (RC + RE) ; Since IE = IC

43
Fig 2 – Thevenizing the Self Bias

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 Stability of Self Bias
• In figure 2 – the thevenin’s theorem applied to the left
of point A.
• The thevenin voltage & resistance given by –

• The thevenin voltage across the resistor R2 – the base

voltage of the transistor.
• Apply KVL to the base-emitter loop –

45
 Stability of Self Bias (contd)
• Replacing IB with (IE/β) [equal to IC/β] in the above
equation & solving for emitter current –

• In the above expression – the emitter current

independent of β – achieved by making emitter
resistance 10 times greater than (RTH / β).

46
 Stability of Self Bias (contd)
• The emitter resistance given by –
RE >= 10 RTH / β
RTH <= 0.1 β RE
• Usually the value of R2 smaller than R1 – hence
RTH = R2
• So R2 <= 0.1 β RE

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 Stability Factor of Self Bias
• Apply KVL to the base-emitter loop –

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 Stability Factor of Self Bias (contd)
• Rearranging the above expression –

• Substituting the value of RTH –

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 Topic 6

Emitter Bias

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Fig 1 – Emitter Bias

51
 Introduction
• Figure 1 shows the circuit for emitter bias.
• Uses both positive (+VCC) & negative supply (-VCC)
voltages.
• If the base resistance RB is large enough in the emitter
bias circuit – the base voltage approximately equal to
zero.
• The base-emitter junction of the transistor forward
biased by the negative supply (-VCC).
• The dc bias values of current & voltage derived.

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 Base Loop
• Since the value of RB higher – the base voltage is
approximately zero.
• Hence the emitter voltage –  VE = - VBE
• Value of emitter current –

• Since VEE supply is negative, emitter current –

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 Collector Loop
• Value of collector current approximately equal to
emitter current – IC = IE
• The collector voltage - VC = VCC – IC RC
• Hence collector-emitter voltage 
VCE = VC - VE

54
 Stability of Emitter Bias
• Apply KVL to the base-emitter loop –
• IB.RB + VBE + IE. RE – VEE = 0
• Substituting the value of base current IB = IC/β = IE/β in
the above equation –

55
 Stability of Emitter Bias (contd)
• From the above equation – emitter current independent
of current gain (β) & Base-emitter voltage (VBE) as long
as RE & VEE supply are large.
• In practice – value of RE 100 times greater than RB/β.
• Mathematically given by –
• RE >= 100 RB/ β
• RB <= 0.01 β RE
• Hence emitter bias provides a reasonably stable Q point.

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 Stability Factor of Emitter Bias
• Apply KVL to the base-emitter loop –

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 Topic 7

Stability Factor for Transistors

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 Definition for Stability Factor
• Stability factor defined as the change in collector
current to change in reverse saturation current keeping
the current gain ‘β’ and the base current IB constant.
• Given by – - S = dIC / dICO
• Stability factor – a measure of bias stability of a
transistor circuit.
• Higher value of stability factor indicates poor stability &
lower value – high stability.
• If the change in collector current equal to change in
reverse saturation current – then stability factor equal
to unity.
• The unity is the lowest value of stability factor.
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 Relationship between IC, ICO & IB
• The value of collector current given by –
IC = β.IB + (1+β) ICO
• Differentiating the above expression wrt IC –

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 Additional Stability Factors
• The above expression is the general expression for
stability factor for any biasing circuit.
• Apart from reverse saturation current – two other
factors which affect the stability of dc biasing circuits –
variation in base current & variation in current gain due
to temperature.
• The stabilities due to these parameters called stability
factors – S’ & S” respectively.
• In practice – the variation in base current (IB) occurs due
to variation in Base-emitter voltage (VBE) with change in
temperature.
• The stability factor - S’ = dIC / dVBE
61
 Additional Stability Factors (contd)
• The stability factor S’ for a voltage divider bias –

• Similarly the stability factor S” defined as – rate of

change of collector current wrt current gain (β) keeping
the base current (IB) & reverse saturation current (ICO)
constant.

62
 Additional Stability Factors (contd)
• The stability factor for voltage divider bias S”

• The rate of change in collector current as a function of

all stability factors given by –

• The variation may be caused due to temperature or

replacement of transistor.
63
 Stability Factor for CB Circuit
• The collector current of a transistor in CB configuration
given by –

• Differentiating this with respect to ICO –

• The value of stability factor – indicates that CB circuits

are highly stable.
• No need for bias stabilization in these circuits.

64
 Stability Factor for CE Circuit
• The collector current of a transistor in CE configuration
given by –

• Differentiating this with respect to ICO –

• From above equation – the collector current in CE

configuration strongly depend on reverse saturation
current which in turn on temperature.
• Need is there to provide bias stabilization in CE circuits
to improve the stability factor.
65
 Topic 8

Bias Compensation

66
Fig 1 – Bias Compensation

67
 Introduction
• All the dc biasing methods use a negative feedback to
stabilize the operating point.
• Negative feedback – a fraction of the collector voltage
or collector current supplied back at the input of the
transistor.
• The use of negative feedback reduces the gain of
amplifier which is not tolerable for some applications.
• In such cases – compensation techniques used to
stabilize the Q point instead of dc biasing circuits.
• Compensation techniques – use temperature sensitive
devices such as diodes, thermistors, transistors etc or
a combination of biasing circuits & temperature
sensitive devices.
68
 Diode Compensation
• Figure 1 (a) shows a diode used for bias compensation.
• The diode reverse biased by the base-emitter junction
voltage which allows reverse saturation current or
leakage current to flow through it.
• When temperature increases – the reverse saturation
current of the transistor also increases which in turn
increase the leakage current through the diode.
• This will decrease the base current by keeping the
current ‘I’ constant.
• This action required to keep the value of collector
current constant.
• Because the collector current dependent on
temperature. 69
 Thermistor Compensation
• Figure 1 (b) shows a thermistor used for bias
compensation.
• The thermistor has negative temperature co-efficient –
the resistance decreases with increase in temperature.
• It is placed in parallel with the resistance R2.
• The resistances are selected in a such way – provides a
correct bias at the normal temperature.
• If temperature increases – the drop across the
thermistor decreases.
• This in turn decreases the forward bias across the base-
emitter junction which reduces the base current &
hence the collector current.
70
 Topic 9

Thermal Stability

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Fig 1 – Fin Type Heat Sink

72
Fig 2 – Rectangular Type Heat Sink

73
 Thermal Runaway
• The reverse saturation current in a semiconductor
device changes with temperature.
• The reverse saturation current approximately doubles
for 10 deg rise in temperature.
• This creates considerable practical difficulty in using the
transistor for amplification.
• If the temperature of collector-base junction increases –
leakage current increases with increase in collector
current.
• This increase in collector current increases the power
dissipation at the collector-base junction.
• This in turn increases the collector current which further
increases the temperature at collector-base junction. 74
 Thermal Runaway (contd)
• This process becomes cumulative & the ratings of the
transistor exceeded leading to damage of the device.
• This process called thermal runaway which can be
avoided by using bias stabilization or using a heat sink
with the transistor.

75
 Types of Heat Sinks
• A heat sink – a metallic heat conducting device placed in
close contact with a transistor to increase the power
dissipation capability of the transistor.
• Heat sink not required for the transistors handling small
signals but for power transistors it is much essential.
• A fin type heat sink & a rectangular heat sink used for
low power transistors & large power transistors
respectively.
• Connecting a heat sink to a transistor – increases the
surface area from which the power dissipated into the
atmosphere.
• The heat from the transistor moves to the heat sink by
conduction and from sink to atmosphere by convection
& radiation.
76
 Types of Heat Sinks (contd)
• In order for the heat sink to radiate maximum
heat – it is generally painted black & mounted in
a position such that free air flow around it.

77
Biasing Methods for JFET

78
 Introduction
• JFET has a no of advantages over a transistor – high
input impedance, less noisy, better thermal stability
etc.
• The only disadvantage is it has small gain bandwidth
product.
• This demerit removed by using advanced
manufacturing techniques.
• It is necessary to bias the FET to use it for a particular
application.
• Biasing required to turn the device ON & operate it in a
proper region to provide a constant voltage gain.

79
 Types of FET Biasing
• Several biasing methods available but the condition –
the gate-source junction must be always reverse
biased.
• 1) Gate Bias
• 2) Self-Bias
• 3) Voltage Divider Bias
• 4) Source Bias
• 5) Current Source Bias

80
 Topic 10

DC Load Line & Operating Point -

JFET

81
 Setting the Q point
• The operating point for a self-biased JFET can be done
by setting the drain current (ID) for a desired gate-source
voltage (VGS) by the following three methods –
• 1) Analytical Method
• 2) Graphical Method
• 3) Using DC Load line
• 1) Analytical Method: From the data sheets of FET – two
values - maximum drain current (IDSS) & gate-source cut-
off voltage (VGS(off)) are noted down. The drain current
given by –
• ID = IDSS [1 – VGS/VGS(off)]
• If the value of VGS made equal to VGS(off)/4, the above
82
Fig 1 – Setting Q point

83
 Setting the Q point (contd)
• Equation becomes –
• ID = IDSS [1-0.25]2 = 0.56 IDSS
• Hence the drain current is slightly above 50 % of the
maximum value so that Q point fixed in the middle of
transfer curves.
• 2) Graphical Method: A self-biased line is drawn to
intersect the transfer characteristic curves near the mid-
point. When the intersection extended – gives the Q
point. The value of source resistance given by –
• RS = VGS / ID
• 3) Using DC Load Line: The dc load line drawn easily on
the drain characteristics as shown in figure 2.
84
Fig 2 - Q point from DC Load Line

85
 Setting the Q point (contd)
• The values of drain current and drain-source voltage
obtained at the upper & lower ends of the load line.
• VDS = VDD – ID. (RD + RS)
• At the upper end –  VDS = 0 in the above equation –
• 0 = VDD – ID.(RD + RS)
• ID = VDD / (RD + RS)
• Similarly at the lower end – ID = 0
• VDS = VDD
• Since the Q point located in the middle of the load line –
• IDQ = VDD / 2(RD + RS)
• VDSQ = VDD / 2
86
Topic 11

Gate Bias

87
Fig 1 – Gate Bias for N channel & P channel JFET

88
 Role of Gate Resistor
• Figure 1 shows the gate bias circuit for both n channel
& p-channel JFETs.
• Gate bias for FET similar to Fixed bias of bipolar junction
transistor.
• In this circuit – the gate supply voltage (-VGG) used to
ensure that – gate-source junction reverse biased.
• Since no gate current – no voltage drop across ‘RG’.
• This bias method cannot provide stable Q point for a
FET.
• Even though no gate current, no drop across ‘RG’ still
the resistor included in the biasing circuit.
• Actually RG used for the purpose of ac operation.
89
 Gate Bias for P-channel JFET
• Figure 1(b) shows the gate bias circuit for P-channel
JFET.
• Circuit similar to N-channel JFET except the polarity of
VDD & VGG supplies are reversed.

90
Topic 12

Self Bias

91
Fig 1 – Self Bias

92
 Circuit Description
• Figure 1(a) shows the self bias circuit for n-channel JFET.
• Here only one supply voltage – drain voltage supply (VDD)
applied.
• The gate terminal connected to ground through a
resistor RG.
• The source terminal connected to ground through a
resistor RS.
• When the drain voltage applied – drain current flows
even though no gate current.
• This drain current produces a voltage drop ID.RS which
reverse biases the gate-source junction.
• This feedback resistor RS – prevents any variation in the
FET drain current. 93
 Impact of Source Resistor RS
• If the drain current increases – will increase the voltage
drop ID.RS which in turn increases the reversed gate-
source voltage.
• This will decrease the effective width of the channel
which will reduce the drain current.
• Hence impact of RS – avoids the variations in drain
current.
• Figure 1 (b) shows the self bias circuit for P-channel
JEFT. The change is reversing the polarity of VDD.
• Even though the gate-source junction reverse biased – a
small amount of current called – gate leakage current
(IGSS) flows which can be neglected.
• Hence the gate terminal is at zero voltage. 94
 Determination of ID & VGS
• The source voltage wrt ground –
VS = ID.RS
• The drain voltage –
VD = VDD – ID.RD
• The drain-source voltage –
VDS = VD – VS
= VDD – ID.RD – ID.RS
= VDD – ID (RD + RS)
• The gate-source voltage –
VGS = VG – VS
= 0 - ID.RS = - ID.RS
95
 Self-Bias Line
• The drain current –
ID = - VGS / ID
• The greater the value of drain current – more negative
the gate-source voltage given by above equation.
• The value of drain current obtained from above
equation against VGS for a constant value of RS – called a
Self-bias line shown in figure 2.

96
 Topic 13

Voltage Divider Bias

97
Fig 1 – Voltage Divider Bias

98
 Determination of ID & VGS
• Figure 1 shows the circuit for voltage divider bias.
• Voltage divider – since R1 & R2 form a potential divider
across the VDD supply and ground.
• Assuming the gate current to be zero, the gate voltage-
• VG = VDD. R2 /(R1 + R2)
• The source voltage – VS = VG – VGS
• Value of drain current -  ID = VS/RS = VG - VGS/RS
• The drain voltage - VD = VDD – ID.RD

99
 Voltage Divider Bias - FET Vs BJT
• If the gate voltage is large enough when compared to
VGS – the drain current is approximately constant for
any JFET.
• In BJT – the value of base-emitter voltage (VBE) is
approximately 0.7 V with only minor variations from
one device to another.
• In JFET – the value of gate-source voltage vary several
volts from one device to another.
• Hence voltage divider bias is not effective in JFET when
compared to BJT.

100
 Topic 14

Source Bias

101
Fig 1 – Source Bias

102
 Determination of Drain Current
• Figure 1 shows the circuit of a source bias for JFET.
• The circuit is similar to the emitter bias circuit used for
biasing bipolar transistors.
• The value of drain current given by –
ID = VSS – VGS / RS
• Since VSS >> VGS, the drain current -
ID = VSS / RS

103
 Topic 15

Current Source Bias

104
Fig 1 – Current Source Bias

105
 Two Supply Circuit
• Figure 1 shows the circuit for current source bias.
• Figures 1 (a) & (b) – shows two supply bias circuit & one
supply circuit respectively.
• In the two supply bias circuit, the transistor is emitter
biased.
• The collector current given by –
• IC = (VEE-VBE) / RE
• = VEE / RE ; Since VEE >> VBE
• The drain current of JFET is equal to the collector
current because transistor acts as a dc current source.

106
 One Supply Circuit
• In the one supply current source bias circuit – the
transistor is voltage divider biased.
• The collector current given by the relation-
• IC = VB – VBE / RE
• The drain current is equal to collector current –
• ID = IC
• This bias circuit provides a stable Q point with JFET.
• Hence the current source bias used in actual practice.

107
 Topic 16

Biasing Enhancement Type

MOSFET’s

108
 Introduction
• The operation of an Enhancement type MOSFET
requires a gate-source voltage greater than its
threshold value –  VGS > VGS(th).
• This eliminates the use of self bias because it makes the
gate voltage negative with respect to source.
• Two methods for biasing the Enhancement type
MOSFET – 1) Drain Feedback Bias 2) Voltage Divider
Bias.

109
Fig 1 – Drain Feedback Bias

110
 Type 1 - Drain Feedback Bias
• The drain feedback bias is similar to the collector
feedback bias of transistors.
• Figure 1 shows the drain feedback bias for Enhancement
type MOSFET.
• This type of biasing applicable for Enhancement type
MOSFET only.
• Since the value of gate current approximately zero –
there is no voltage drop across gate resistance RG.
• Hence gate-source voltage is equal to drain-source
voltage - VGS = VDS
• The value of drain current - ID = (VDD - VDS) / RD
• Provides a stable Q point – it tends to compensate for
any changes in device parameter variations. 111
Fig 2 - Voltage Divider Bias

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 Type 2 – Voltage Divider Bias
• Figure 2 shows the circuit for voltage divider bias.
• Voltage divider – since R1 & R2 form a potential divider
across the VDD supply and ground.
• Assuming the gate current to be zero, the gate voltage-
• VG = VDD. R2 /(R1 + R2)
• The source voltage – VS = VG – VGS
• Value of drain current -  ID = VS/RS = VG - VGS/RS
• The drain voltage - VD = VDD – ID.RD

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 Voltage Divider Bias - MOSFET Vs BJT
• If the gate voltage is large enough when compared to
VGS – the drain current is approximately constant for
any MOSFET.
• In BJT – the value of base-emitter voltage (VBE) is
approximately 0.7 V with only minor variations from
one device to another.
• In MOSFET – the value of gate-source voltage vary
several volts from one device to another.
• Hence voltage divider bias is not effective in MOSFET
when compared to BJT.

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 Topic 17

Biasing Depletion Type MOSFET’s

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Fig 1 – Zero Bias of D-type MOSFET

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 Zero Bias
• The depletion type MOSFET can be operated with either
positive or negative values of gate-source voltage (VGS).
• Hence the simplest method – to set the gate-source
voltage to zero as shown in figure 1 (a).
• This will bias the MOSFET at a point lying on the vertical
axis of the transfer characteristic curve as shown in
figure 1 (b).
• If ac signal applied at the gate – it will vary the gate-
source voltage above & below the Q point.
• Since the biasing circuit has no applied gate-source
voltage – the value of VGS equal to zero and the drain
current achieves the maximum value (IDSS).
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 Zero Bias (contd)
• The drain-source voltage given by –
• VDS = VDD – ID.RD
• = VDD – IDSS.RD
• Zero Bias possible only with depletion type MOSFET &
cannot be used for biasing the JFET and transistors.
• All biasing methods of JFET discussed above – applicable
for MOSFET under depletion mode only but not in
enhancement mode.

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