ELECTRONIC CIRCUITS- I

DC Biasing Circuits

The ac operation of an
amplifier depends on the initial
dc values of IB, IC, and VCE.

By varying IB around an initial

dc value, IC and VCE are made
to vary around their initial dc
values.

DC biasing is a static operation

v
since it deals with setting a in
fixed (steady) level of current
(through the device) with a
desired fixed voltage drop
across the device.

+VCC

RC
RB

v out

ib

vce

ic

Purpose of the DC biasing circuit

To turn the device ON
To place it in operation in the region of its c
haracteristic where the device operates most
linearly, i.e. to set up the initial dc values of
IB, IC, and VCE

Voltage-Divider Bias
The voltage divider (or potentio
meter) bias circuit is by far the mos
t commonly used.
RB1, RB2
voltage-divider to set the value
of VB , IB , C3
to short circuit ac signals to gr
ound, while not effect the DC oper
ating (or biasing) of a circuit
(RE stabilizes the ac signals)
Bypass Capacitor

+VCC

R1

RC
v out

v in

C2

C1

R2
RE

C3

Graphical DC Bias Analysis

+VCC

VCC ICRC VCE IERE 0

for I C I E
1
VCC
VCE
RC RE
RC RE
Point - slope form of straight line equation :
y mx c
IC

IC
R1

RC

IC(sat) = VCC/(RC+RE)

R2

DC Load Line

IE
RE

IC
(mA)

VCE(off) = VCC
VCE

DC Load Line
The straight line is know as the DC load line

IC(sat) = VCC/(RC+RE)

Its significance is that regardless of the behavior of

the transistor, the collector current IC and the I
collector-emitter voltage VCE must always lie on the(mA)
load line, depends ONLY on the VCC, RC and RE

DC Load Line

VCE(off) = VCC
VCE

(i.e. The dc load line is a graph that represents all

the possible combinations of IC and VCE for a
given amplifier. For every possible value of IC, and
amplifier will have a corresponding value of VCE.)
It must be true at the same time as the transistor
characteristic.
Solve two condition using
simultaneous equation
graphically Q-point !!

What is IC(sat) and VCE(off) ?

Q-Point (Static Operation Point)

When a transistor does not have an ac input, it wil
l have specific dc values of IC and VCE.
These values correspond to a specific point on the
dc load line. This point is called the Q-point.
The letter Q corresponds to the word (Latent) quie
scent, meaning at rest.
A quiescent amplifier is one that has no ac signal a
pplied and therefore has constant dc values of IC a
nd VCE.

Q-Point (Static Operation Point)

The intersection of the dc bias valu
e of IB with the dc load line determ
ines the Q-point.
It is desirable to have the Q-point c
entered on the load line. Why?
When a circuit is designed to have
a centered Q-point, the amplifier is
said to be midpoint biased.
Midpoint biasing allows optimum
ac operation of the amplifier.

DC Biasing + AC signal
When an ac signal is applied to the base of
the transistor, IC and VCE will both vary aro
und their Q-point values.
When the Q-point is centered, IC and VCE c
an both make the maximum possible transi
tions above and below their initial dc value
s.
When the Q-point is above the center on th
e load line, the input signal may cause the t
ransistor to saturate. When this happens, a
part of the output signal will be clipped off.
When the Q-point is below midpoint on th
e load line, the input signal may cause the t
ransistor to cutoff. This can also cause a p
ortion of the output signal to be clipped.

DC Biasing + AC signal

DC and AC Equivalent Circuits

+VCC

+VCC

R1

IC

RC

R1

RC

RL
vin
R2

R2
RE

vce

vin
R1//R2

IE
RE

rC = RC//RL

Bias Circuit

DC equivalent
circuit

AC equivalent
circuit

rC

AC Load Line
The ac load line of a given a
mplifier will not follow the p
lot of the dc load line.
This is due to the dc load of a
n amplifier is different from t
he ac load.
IC(sat) = ICQ + (VCEQ/rC)

IC

ac load line

ac load line

IC

Q - point
dc load line

VCE(off) = VCEQ + ICQrC

VCE

VCE

AC Load Line
What does the ac load line tell you?
The ac load line is used to tell you the maximum possibl
e output voltage swing for a given common-emitter ampl
ifier.
In other words, the ac load line will tell you the maximu
m possible peak-to-peak output voltage (Vpp) from a give
n amplifier.
This maximum Vpp is referred to as the compliance of th
e amplifier.
(AC Saturation Current Ic(sat) , AC Cutoff Voltage VCE(off) )

AC Saturation Current and

AC Cutoff Voltage

IC(sat) = ICQ + (VCEQ/rC)

vce

vin
R1//R2

rC

IC

ac load line

VCE(off) = VCEQ + ICQrC

rC = RC//RL

VCE

Amplifier Compliance
The ac load line is used to tell the maximum possi
ble output voltage swing for a given common-emi
tter amplifier. In another words, the ac load line
will tell the maximum possible peak-to-peak outpu
t voltage (VPP) from a given amplifier. This maxi
mum VPP is referred to as the compliance of the a
mplifier.
The compliance of an amplifier is found by determ
ine the maximum possible of IC and VCE from their
respective values of ICQ and VCEQ.

Maximum Possible Compliance

Compliance
The maximum possible transition for VCE is equal to the dif
ference between VCE(off) and VCEQ. Since this transition is eq
ual to ICQrC, the maximum peak output voltage from the am
plifier is equal to ICQ rC. Two times this value will give the
maximum peak-to-peak transition of the output voltage:
VPP = 2ICQrC
(A)
VPP = the output compliance, in peak-to-peak voltage
ICQ = the quiescent value of IC
rC = the ac load resistance in the circuit

Compliance
When IC = IC(sat), VCE is ideally equal to 0V. When IC = ICQ, VCE is
at VCEQ. Note that when IC makes its maximum possible transitio
n (from ICQ to IC(sat)), the output voltage changes by an amount eq
ual to VCEQ. Thus the maximum peak-to-peak transition would be
equal to twice this value:
VPP = 2VCEQ
(B)
Equation (A) sets the limit in terms of VCE(off). If the value obtain
ed by this equation is exceed, the output voltage will try to excee
d VCE(off), which is not possible. This is called cutoff clipping, bec
ause the output voltage is clipped off at the value of VCE(off).
Equation (B) sets of the limit in terms of IC(sat). If the value obtai
ned by this equation is exceed, the output will experience saturati
on clipping.

Cutoff and Saturation Clipping

When determining the output compliance for a given amplifie
r, solve both equation (A) and (B). The lower of the two r
esults is the compliance of the amplifier.

Example
For the voltage-divider bias amplifier show
n in the figure, what is the ac and dc load li
ne. Determine the maximum output complia
+12V
nce.
R

33 k

R C
4.7k
R

= 200
R

10k

R
2.2k

10k

Transistor Bias Circuits

Objectives
Discuss the concept of dc biasing of a transistor
for linear operation
Analyze voltage-divider bias, base bias, and
collector-feedback bias circuits.
Basic troubleshooting for transistor bias
circuits

Introduction
For the transistor to properly operate it must be
biased. There are several methods to establish the
DC operating point. We will discuss some of the
methods used for biasing transistors as well as
troubleshooting methods used for transistor bias
circuits.

The DC Operating Point

The goal of amplification in most cases is to increase the
amplitude of an ac signal without altering it.

The DC Operating Point

For a transistor circuit to amplify it must be properly biased
with dc voltages. The dc operating point between saturation and
cutoff is called the Q-point. The goal is to set the Q-point such
that that it does not go into saturation or cutoff when an a ac
signal is applied.

The DC Operating Point

Recall that the collector characteristic curves graphically show the
relationship of collector current and VCE for different base currents. With
the dc load line superimposed across the collector curves for this
particular transistor we see that 30 mA of collector current is best for
maximum amplification, giving equal amount above and below the Qpoint. Note that this is three different scenarios of collector current being
viewed simultaneously.
VCC
1
I

(
)
V

c
CE
Slope of the dc load line?
Rc
RC

The DC Operating Point

With a good Q-point established, lets look at the effect a superimposed ac
voltage has on the circuit. Note the collector current swings do not exceed the
limits of operation(saturation and cutoff). However, as you might already
know, applying too much ac voltage to the base would result in driving the
collector current into saturation or cutoff resulting in a distorted or clipped
waveform. (Example 5-1)

Voltage-Divider Bias
Voltage-divider bias is the most widely used
type of bias circuit. Only one power supply
is needed and voltage-divider bias is more
stable( independent) than other bias types.
For this reason it will be the primary focus
for study.

Voltage-Divider Bias
Apply your knowledge of
voltage-dividers to understand
how R1 and R2 are used to
provide the needed voltage to
point A(base). The resistance to
ground from the base is not
significant enough to consider
in most cases. Remember, the
basic operation of the transistor
has not changed.

Voltage-Divider Bias
In the case where base to ground resistance(input resistance) is
low enough to consider, we can determine it by the simplified
equation RIN(base) = DCRE
We can view the voltage at point A of the circuit in two ways,
with or without the input resistance(point A to ground)
considered.

Voltage-Divider Bias
For this circuit we will not
take the input resistance into
consideration. Essentially we
are determining the voltage
across
R2(VB)
by
the
proportional method.

R 2 || DC RE
VCC
VB
R1 ( R2 || DC RE )

VB = (R2/R1 + R2)VCC

Voltage-Divider Bias
We now take the known base voltage and
subtract VBE to find out what is dropped
across RE. Knowing the voltage across RE we
can apply Ohms law to determine the
current in the collector-emitter side of the
circuit. Remember the current in the baseemitter circuit is much smaller, so much in
fact we can for all practical purposes we say
that IE approximately equals IC.
IE IC

Voltage-Divider Bias

Although we have used npn transistors for most of

this discussion, there is basically no difference in its
operation with exception to biasing polarities.
Analysis for each part of the circuit is no different
than npn transistors.

Base Bias
This type of circuit is very unstable since its changes with
temperature and collector current. Base biasing circuits are
mainly limited to switching applications.

VCC VBE
IC (
) DC
RB

Emitter Bias
This type of circuit is
independent of making it as
stable as the voltage-divider
type. The drawback is that it
requires two power supplies.
Two key equations for analysis
of this type of bias circuit are
shown below. With these two
currents known we can apply
Ohms law and Kirchhoff's law
to solve for the voltages.
IB IE/
IC IE ( -VEE-VBE)/(RE + RB/ DC)

Collector-Feedback Bias
Collector-feedback bias is kept
stable with
negative feedback,
although it is not as stable as
voltage-divider or emitter. With
increases of IC, less voltage is
applied to the base. With less IB ,IC
comes down as well. The two key
formulas are shown below.
IB = (VC - VBE)/RB
IC = (VCC - VBE)/(RC + RB/ DC)

Summary
The purpose of biasing is to establish a stable
operating point (Q-point).
The Q-point is the best point for operation of a
transistor for a given collector current.
The dc load line helps to establish the Q-point
for a given collector current.
The linear region of a transistor is the region of
operation within saturation and cutoff.

Stability Factor

Operating Regions
Region of
operation

EB
junction
Reverse
Biased

CB
junction
Reverse
Biased

Active

Forward
Biased

Reverse
Biased

Saturation

Forward
Biased

Forward
Biased

Cut off

Ic

Saturation
Region

Active Region
Ib = 60A

Ic = 10mA

Ib = 50A

Ic = 8mA

Ib = 40A

Ic = 6mA

Ib = 30A
Ic = 4mA

Ib = 20A

Ic = 2mA

Cut-off Region
0V

24 V

Vce

Typical junction voltages

Transistor
Si

Vce
Vbe
Vbe
Vbe
Vbe
sat
sat active cut-in cut-off
0.2 V 0.8 V 0.7 V 0.5 V 0 V

Ge

0.1 V 0.3 V 0.2 V 0.1 V -0.1 V

In the saturation region Ic > Ib

For active region Vce > Vce(sat)

Problem

Vcc = 10 V

Rb = 300 K
Calculate Ib, Ic & Vce if
= 100 for the Silicon
transistor. Find the region of
operation
Hint
Vbe = 0.7 V

Answer
Ib = 31 A
Vce = 3.8 V

Ic=3.1mA
Active

Rb

Rc

300 K

2K

Ic

Problem
Leakage current Io = 2 A at 250 C
Calculate Rb, if the Ge transistor
remains in cut-off at 750 C
Hints
Leakage current doubles for every
Io
100 C
Io = Io . 2i/10
i = t2 t1
Vbe(cut-off) = -0.1V

Answer
Rb = 76.6 K

Vcc
10 V

Vbb
-5 V

Rb
270 K

Rc
5.6 K

Problem
If Vbb = 1 V, Rb = 50 K, upto
what temperature, the transistor
will remain in cut-off ? (Room
temp. = 250 C
Io
Hints
Find Io
Io = Io . 2i/10
i = t2 t1
Find t2

Answer
t2 = 56.70 C

Vcc
10 V

Vbb
-1 V

Rb
50 K

Rc
5.6 K

Problem
Show that the transistor is in
saturation region
Hints
In saturation Ic is not equal to Ib
Vbe(sat) = 0.8 V
Ie = Ib + Ic
Find Ib & Ic

+Vcc
10 V

Ib
100K

2K

100

1K
Answer
Ib = 58.9 A
Ic = 3.24mA

Ic

Ie

Common Base Configuration

Ie
E

Input

Ic

-- ----- -- ---_

Vbe

-- -- --------------- - -- --

Ib

Output

Vcb

Here the input is applied at the Emitter & the output taken
from the Collector
In this arrangement Base is common to the input & output
This is called Common Base configuration

Common
Base Configuration
Vcc
Ie

Ic
Output

Input

Re
Rb1

Rc

Rc

output

Vee

Vcc

The circuit can be re-drawn as

shown, with input at Emitter &
output at Collector

input
Rb2

Ib

Re

Vb is obtained using Rb1 & Rb2

This is called potential divider
arrangement

Common Emitter Configuration

Ie

Vcc

Ic
E

Output

Rb1

B
Rc

Ib

Output

Vee
Input

Rb2

Input Vcc

The circuit has been re-configured with

input at Base & output at Collector
Re

The Emitter is common to input & output

This is called Common Emitter
configuration

Reverse Saturation current Ico

Ico

Vee

Vcc
+

When Emitter is open, the base & collector act as a reverse

biased diode
Since CB junction is reverse biased there will not be any I c
However, there will be a current due to the minority charge
carriers
This is called Reverse Saturation Current Ico

Reverse Collector Saturation current Icbo

Ie

Icbo

Vee

Vcc

Icbo is the leakage current that flows at the collector due to the
minority charge carriers, in the common base mode
Is the current gain in the CB mode

Reverse Collector Saturation current Iceo

Ie

Iceo

Vee

Vcc

Iceo is the leakage current that flows at the collector due to the
minority charge carriers, in the common emitter mode
Is the current gain in the CE mode

Ic = .Ie + Icbo
= (Ib + Ic) + Icbo
Ic (1- ) = Ib + Icbo
Ic =
Since =
1

1-

Ib +
1-

Icbo
1-

1-

= +1

Ic = I + (+1)I
cbo
b
i.e. Ic = Ib + Iceo

where Iceo = (+1) I

cbo

Stability
Temperature & Current gain variation may change
the Q point
Stability refers to the design that prevents any cha
nge in the Q point
Temperature effect
When the temperature increases it results in the pr
oduction of more charge carriers
This increases the forward bias of the transistor an
d Ib increases

Temperature effect
When the temperature increases it results in the production
of more charge carriers
This increases the minority charge carrier and hence the le
akage current as
Iceo = (+1) Icbo
Icbo doubles for every 100 C
As Ic = Ib + Icbo
The increase in the temperature increases Ic
This in turn increases the power dissipation and again mor
e heat is produced

Thermal Runaway

This increases the power dissipation

This results in more heat
Again the charge carrier increases
The whole process repeats
Ultimately Ic may become too large and burn the t
ransistor
This is called Thermal Runaway

Change in Vbe
Vbe changes @ 25 mV per degree Celcius
Ib depends on Vbe
Ic depends on Ib
Hence Ic changes with temperature
This shifts the operating point

Change in
The current gain also depends on temperature
As Ic = Ib, Ic varies with temperature
This shifts the Q point
Thermal stability should ensure that in spite of tem
perature change, the selected Vce, Ic & Power ma
x do not change

Techniques
Stabilization technique
Resistive biasing circuits change Ib suitably and k
eep Ic constant
Compensation technique
Temperature sensitive devices such as diodes, ther
mistors & transistors are used to provide suitable c
ompensation and retain the operating point withou
t shifting

Stability Factor
It indicates the degree of change in the operating p
oint due to variation in temperature
There are 3 stability factors corresponding to the 3
variables Ico, Vbe &

S =
S =
S =

Ic
Ico Vbe, constant
Ic
Vbe Ico, constant
Ic

Ico, Vbe constant

The stability factor should

be as minimum as possible

Ic = Ib + Iceo

Stability Factor S

= Ib + (I + ) Icbo

i.e. Ic = Ib + (I + ) Icbo
Ib
Icbo
+ (I + )
Ic
Ic
Icbo
= (I + )
Ic

i.e. 1 =
i.e. 1 -

Ib
Ic
Icbo
Ic

i.e.

S=

Ic
Icbo

1-
=

Ib
Ic

(I+)
(I+)
1-

Ib
Ic

Design of biasing system

Vcc

Fixed Bias Circuit

When Ib flows through
Rb, there will be a voltag
e drop across Rb
Vb = Vcc (Ib x Rb)
Ib = (Vcc Vb) / Rb
= Vcc / Rb (approx)
Supply voltage Vcc is fix
ed
Hence once Rb is chosen
Ib is also fixed
Hence the name Fixed bi
as circuit

Ib

Rb

Vbe

 When collector current Ic

flows through Collector lo
ad resistor Rc, there will b
e a voltage drop across Rc
Vc = Vcc (Ic x Rc)

Vcc

Ib

Rb

Rc

Ic

Or, Vc < Vcc

Or, Ic < Vcc / Rc
In case Ic > Vcc / Rc, the
n the operating point lies i
n the saturation region

Vce
Vbe

Problem
Design a fixed biased circuit using a silicon transis
tor having
= 100
Vcc = 10 V
Vce = 5 V
Ic = 5 mA
Answer: Rc = 1 K Rb = 186 K

Problem

A fixed bias circuit has

= 100 @ 250 C & = 125 @ 750 C
Vcc = 12 V
Rb = 100 K
Rc = 600
Determine % change in Q point values over the te
mperature range

Answer: %change in Ic = + 25%

%change in Vc = - 32.5%

Stability Factor S
For Fixed Bias Circuit

S =

Ic
Ico Vbe, constant
(I+)

Ib
1-
Ic

For the fixed Bias Circuit Ib = Vcc / Rb

. .
.

. .

Ib
Ic = 0
(I+)
S=

1 - (0)

. .

S=1+

Stability Factor S
For Fixed Bias Circuit
Ic = Ib + Iceo

S =

= Ib + ( + 1) Icbo
Vcc - Vbe
=
+ ( + 1) Icbo
Rb
Vcc
Vbe
+ ( + 1) Icbo
=
Rb
Rb
Ib

_
= 0
+ 0
. .
Vbe
Rb
.

. .

S = - / Rb

Ic
Vbe Ico, constant

Stability Factor S
For Fixed Bias Circuit
Ic = Ib + Iceo
S =
= Ib + (+1)Icbo

Ic

Vcc - Vbe
=
+ ( + 1) Icbo
Rb
Vcc
Vbe
+ ( + 1) Icbo
=
Rb
Rb
.

. .

Ic

Vcc
=
Rb

Vbe
Rb

= Ib + Icbo
= Ib (approx)
.

. .

= Ic /
S = Ic /

+ Icbo

Ico, Vbe constant

Vcc = 10 V

Problem
Rb = 100 K
Rc = 2 K
Vcc = 10 V
Vce = 4 V
For this emitter grounded
Fixed Bias circuit with Si
transistor, find the stability
factor S

Answer
S = 33.3

Rb
270 K

100 K

Rc
5.6 K

Ic

2K

4V

Advantages of fixed bias circuit

Simple circuit with minimum components
Operating point can be fixed conveniently in the a
ctive region, by selecting appropriate value for Rb
Hence fixed bias circuit provides flexibility in the
design

Disadvantages of fixed bias circuit

Ic increases with temperature & there is no control
over it
Hence there is poor thermal stability Ic = Ib
Hence Ic depends on
may change from transistor to transistor
This will shift the operating point
Hence stabilization is very poor in fixed bias circu
it

Vcc

Collector to Base Bias

Here Rb is connected bet
ween Base & Collector
So, Ic & Ib flow through
Rc

Rc
Ib

Rb

Ic+Ib

Ic
Vce

Vcc

Vc = Vcc (Ic + Ib) x Rc

Also, Vc = (Ib x Rb) + Vbe
Equating the two equations
Vcc (Ic + Ib)Rc

Rc

= (Ib Rb) + Vbe

Or, Ib(Rc + Rb) = Vcc IcRc - Vbe

.

. .

As Ic = Ib

Ic+Ib

Ib

Vcc IcRc - Vbe

Ib =

Rc + Rb
( Vcc IcRc Vbe)

Ic =

Rc + Rb

Rb

Ic
Vce

Vcc

Rb provides a feedback
between Collector & Base
If Ib or Ic tries to increase
either due to temperature
effect or due to variation in

Voltage drop across Rc

increases
This decreases Vce
This in turn reduces Ib,
stabilizing the circuit

Rc

Ib

Ic+Ib

Rb
Vce

+12 V

Problem
Calculate the values of Ic & Vce
for the given circuit
Hint
Vcc = Rc(Ic + Ib) + Vce
Ic = Ib
Vce = Rb Ib + Vbe
Vbe = 0.6

Answer
Ic = 1.018 mA
Vce = 1.72 V

10 K

100 K

100

Problem

Design a collector to base circuit for the

specified conditions:
Vcc = 15 V
Vce = 5 V
Ic = 5 mA
= 100
Hint
Vcc = Rc(Ic + Ib) + Vce
Ic = Ib
Vce = Rb Ib + Vbe

Answer
Rc = 1.98 mA

Rb = 86 K

Stability Factor S
For Collector-Base Bias

Vcc = (Ib + Ic)Rc + IbRb + Vbe

Ic
Ico Vbe, constant

=IcRc + Ib(Rc + Rb) + Vbe

0 = IcRc + Ib(Rc + Rb) + 0

after differentiation

or - IcRc = Ib(Rc + Rb)

.

. .

Ib
Ic

-Rc
Rc + Rb
(I + )

S=

1-

Ib
Ic

(I + )
=
1+

Rc
Rc + Rb

Stabilization with changes in

If we design our circuit such that Rc >>Rb
Then S becomes independent of
Hence variation from transistor to transistor has no
effect on the stability

(1 + )
S=
1+

Rc
Rc + Rb

S=

1+
1+

=1

Stability Factor S
For Collector-Base Bias
Vcc IcRc - Vbe
Ib =

Ic

Ic

Ic

Ic
Vbe Ico, constant

S =

Rc + Rb
Vcc IcRc - Vbe
Ic =

Rc + Rb
IcRc
Rc + Rb

Rc + Rb + Rc

(Rc + Rb)

Vcc - Vbe
Rc + Rb
Vcc - Vbe
Rc + Rb

S =

(Vcc Vbe)
Rb + ( + 1) Rc
Ic
Vbe

-
Rb + (

+ 1) Rc

Stability Factor S
For Collector-Base Bias

S =

Ic

Ico, Vbe constant

Vcc = (Ib + Ic)Rc + IbRb + Vbe

Vcc Vbe = (Ib + Ic)Rc + IbRb
= Ib [(1 + )Rc +Rb]
.

. .

. .

Ib =

Ic =

Vcc Vbe
(1 + ) Rc + Rb
( Vcc Vbe)
(1 + ) Rc + Rb

Ic

. .

=
.

. .

S =

[(1 + )Rc +Rb](Vcc Vbe) - (Vcc Vbe) Rc

[(1 + ) Rc + Rb]2
(Vcc Vbe)[(1 + )Rc +Rb] - Rc
[(1 + ) Rc + Rb]2
(Vcc Vbe)(Rc +Rb)
[(1 + ) Rc + Rb]2
Vcc Vbe
(1 + ) Rc + Rb

Rc + Rb
x

(1 + ) Rc + Rb

Ib(Rc + Rb)
(1 + ) Rc + Rb
Ic(Rc + Rb)
[(1 + ) Rc + Rb]

S =

Ic(Rc + Rb)
[(1 + ) Rc + Rb]
Ic 1+

(Rc + Rb)

1+

(1 + ) Rc + Rb

Ic

(1+ ) (Rc + Rb)

1+

(1 + ) Rc + Rb

Ic

1+

If S is small, S will also be small

Hence if we provide stability against Ico variations, it will take
care of variation as well

Vcc

Voltage Divider Bias

Ib1

Rb1
270 K

Rc

Ic

Vb = Vc Ib Rb

5.6 K

Thus Ib depends on Vb &

Vb depends on Ib

To avoid this anomaly, two

resistors Rb1 & Rb2 have
been used

Rb1 & Rb2 act as Voltage

Divider circuit giving Vb,
irrespective of Ib

Ib

Ib2

Ie
Rb2

Re

Usually Vb is obtained
using Rb & Ib

Vcc

Rb1 is called Base Bias

Resistor

Ib1

Rb1
270 K

Rc

Ic

5.6 K

Rb2 is called Base Bleeder

Resistor
Vb is obtained based on
the ratio of Rb1 and Rb2

Ib

Ib2

Ie
Rb2

Re

Rb2
Vb = Vcc
Rb1 + Rb2

Vcc

Ib1

Rb1
270 K

Rc

Ic

5.6 K

Rest of the equations remain

the same
Vc = Vcc Ic Rc
Vb = Ve + Vbe

Ib

Ve = Ie Re

Ib2

Ie
Rb2

Re

+10 V

Problem

Rb1
10 K

Rc
1K

For the Si transistor, if is

100, find
Vce & Ic
Hints
Find Vb, Ve, Ie, Ib

Rb 2
5K

Answer
Re 500

Ic = 5.2 mA
Vce = 2.16 V

Vcc

Vcc

We can draw the Thevenin

Equivalent Circuit for the
base circuit
Ib1

Rb1

Rc

270 K

5.6 K

Ic

VT = Vb

&

Rc

Ic

5.6 K

R = Rb1 II Rb2

R
Ib

Ib

Ib2

VT
Rb2

Re

Ie
Rb2

Re

Stability Factor S
For Voltage Divider Bias

S =

Vb = IbRb +Vbe + IeRe

Ic
Ico Vbe, constant

where Rb = Rb1 ll Rb2

= IbRb +Vbe + (Ib + Ic)Re

Differentiating,
0 = IbRb + 0 + IbRe + IcRe
i.e. Ib(Rb + Re) = - IcRe
.

. .

Ib
Ic

-Re
Rb + Re

(I + )
S=

Ib
1-
Ic

(I + )
=
1+

Re
Re + Rb

(I + )

S=
1+

Re
Re + Rb

In the above equation, if Rb << Re, then S become

s1
Rb = Rb1 ll Rb2
Hence either Rb1 or Rb2 must be << Re
Since Vb << Vcc, Rb2 is kept small wrt Rb1

(I + )

S=
1+

Re
Re + Rb

(I + )

S=
1+

S = (I + )

1 + Rb/Re

Re cannot be increased beyond a limit, as it will affec

t Ic and hence the Q point
If Rb-Re ratio is fixed, and if Rb >> Re, S increases
with
Thus stability decreases with increasing

(I + )

S=
1+

Re
Re + Rb

(I + )

S=
1+

S= I

1 + Rb/Re

If Rb << Re, then S becomes independent of

Stability factor S for Voltage Divider circuit is less co
mpared to other circuits
Hence it is preferred over other circuits

+20 V

Rb1
100 K

Problem
For the Ge transistor, if
is 50, find
Vce & Ic
Find Ib,Vce, Ic & S

Rc
2K

Hint Vbe = 0.2 V

Rb2
5K
Re
100

Answer
Ib = 76.3 uA
Vce = 11.98 V
Ic = 3.81 mA
S = 25.14

+20 V

Problem

Rb1
50 K

Rc
2K

For the Si transistor, if is

100 & Ic = 2 mA find
Re,Vce, & S

Answer

Rb2
5K
Re

Re = 149

Vce = 7.7 V

S = 24.25

Problem
Design a voltage divider bias circuit for the given spe
cifications:
Vcc = 12 V, Vce = 6 V, Ic = 1 mA, S = 20, = 100 &
Ve = 1 V
Answer:
Rb1= 150 K , Rb2 = 27 K, Rc = 4.7 K , Re = 1 K

Stability Factor S
For Voltage Divider Bias

Vb = IbRb +Vbe + IeRe

= IbRb + Vbe + (Ib + Ic)Re

S =

Ic
Vbe Ico, constant

= Ib(Rb + Re) + Vbe + IcRe

= Ic / (Rb +Re) + Vbe + IcRe
Or, Vb = Ic(Rb +Re) + Vbe + IcRe
= Ic[Rb +( + 1)Re] + Vbe
0 = Ic[Rb +( + 1)Re] + Vbe
Or, Vbe = - Ic [Rb +( + 1)Re]
S = Ic =
Vbe

-
Rb + (

+ 1) Re

Differentiating,

Stability Factor S
For Voltage Divider Bias

Vb = IbRb +Vbe + IeRe

S =

= Ib(Rb + Re) + Vbe + IcRe

Ic

Ico, Vbe constant

= Ic / (Rb +Re) + Vbe + IcRe

Or, Vb = Ic(Rb +Re) + Vbe + IcRe
Or, (Vb Vbe) = Ic(Rb +Re) + IcRe
Differentiating,
(Vb Vbe) = Ic(Rb +Re) + IcRe + Ic Re
(Vb Vbe IcRe) = Ic[Rb + Re+ Re]
.

. . S =

Ic

Vb Vbe - IcRe
Rb + Re(1+ )

S =

Ic

Vb Vbe - IcRe
Rb + Re(1+ )
Vb Vbe - IeRe
Rb + Re(1+ )

As Ie = Ic

Ib Rb
Rb + Re(1+ )
Ib
1 +(Re/Rb)(1+ )

Hence Rb / Re must be small to make S smaller

Vcc

Self Bias
In this circuit Re provides Self

bias
Ib1

Rb1

Rc

270 K

5.6 K

Ic

When Ib or Ic tries to increase,

Ie increases
This produces more drop across
Re & increases Ve
This reduces Vbe which is
Vb Ve

Ib

This in turn reduces Ib and

hence Ic

Ib2
Rb2

Re

Thus Re provides a negative

feed back and improves the
stability

Bias Compensation
The biasing circuits seen so far provide stability of
operating point for any change in Ico, Vbe or
The collector- base bias & emitter bias circuits pro
vide negative feedback & make the circuit stable,
but the gain falls down
In such cases it is necessary to use compensation t
echniques

 Diode Compensation
Technique

Vcc

Here diode D has been connected

as shown
It is given forward bias through
Vdd

Rb

Rc

270 K

5.6 K

The diode D is identical to the BE

junction of the transistor
The charge carriers will increase
in the BE jn. due to temperature or
other variations

Rd

Vdd

Re
D

Vcc
Since diode D has similar
properties, its charge carrier
also increases, for any change
in the parameters

Rb

Rc

270 K

5.6 K

Thus the increase in current in

the BE junction is compensated
by the current flow through the
diode in the reverse direction.
Rd

Vdd

Re
D

Vcc

Another technique
Here the diode D has been
connected in the bleeder path
When there is increase in
current in the BE junction due
to parameter changes, current
through D also increases by the
same amount

Ib1

Rb1
270 K

Ib2

Rc
5.6 K

Rb2

Re

Vcc
This increases Ib1, produces more
drop across Rb1& reduces Vb
As Vb decreases, Ib falls down
Thus the transistor currents are
arrested and not allowed to
increase
Thus diode D provides suitable
compensation

Rb1

Rc

270 K

5.6 K

Rb2

Re

Thermistor Compensation
Here a Negative Temperature
Coefficient Resistor has been used

Ib1

Vcc

Rb1

Rc

270 K

5.6 K

As temperature increases, its

resistance decreases
This increases Ib1 & voltage drop
across Rb1
This decreases Vb and hence Ib &
Ic, thus keeping the circuit stable.

Ib

Ib2
NTC

Re

Sensitor Compensation
Here a Positive Temperature
Coefficient Resistor has been used
As temperature increases, its
resistance increases
This increases the voltage drop
across Rb1(PTC)
This reduces Vb and Ib, thus
keeping the circuit stable.

Vcc

Rb1
270 K

5.6 K

Rc

PTC

Ib

Rb2
Re

Vcc

Rb1

Rc

Constant Current circuit

Re provides self bias

Vb is fixed depending on
the ratio of Rb1 & Rb2 &
the value of Vcc

Ve = Vb - Vbe

Vbe is fixed for a transistor

Hence Ve is fixed &

Ie = Ve / Re is also fixed

Hence it acts as a constant

current circuit

5.6 K

Rb2
Re

Problem
For the given Si transistor
find the constant current I

Rb1

270 K

5.6 K

Answer
I = 4.22 mA

Rb2
4K7
Re
2K2

-20 V

FET Biasing

Introduction
For the JFET, the relationship between input and out
put quantities is nonlinear due to the squared term in
Shockleys equation.
Nonlinear functions results in curves as obtained for
transfer characteristic of a JFET.
Graphical approach will be used to examine the dc a
nalysis for FET because it is most popularly used rat
her than mathematical approach
The input of BJT and FET controlling variables are t
he current and the voltage levels respectively

Introduction
JFETs differ from BJTs:
Nonlinear relationship between input (VGS) and ou
tput (ID)
JFETs are voltage controlled devices, whereas BJT
s are current controlled

Introduction
Common FET Biasing Circuits
JFET
Fixed Bias
Self-Bias
Voltage-Divider Bias
Depletion-Type MOSFET
Self-Bias
Voltage-Divider Bias
Enhancement-Type MOSFET
Feedback Configuration
Voltage-Divider Bias

General Relationships
For all FETs:
IG 0A
ID IS

For JFETs and Depletion-Type MOSFETs:

VGS 2
ID IDSS(1
)
VP

For Enhancement-Type MOSFETs:

I D k (VGS VT ) 2

Fixed-Bias Configuration
The configuration includes the ac levels Vi and Vo and the cou
pling capacitors.
The resistor is present to ensure that Vi appears at the input to
the FET amplifier for the AC analysis.

Fixed-Bias Configuration
For the DC analysis,
Capacitors are open circuits and
The zero-volt drop across RG permits replacing RG by a short-circuit
IG 0A

V RG I G RG (0 A) RG 0V

Fixed-Bias Configuration
Investigating the input loop
IG=0A, therefore
VRG=IGRG=0V
Applying KVL for the input loop,
-VGG-VGS=0
VGG= -VGS
It is called fixed-bias configuration due to VGG is a fixe
d power supply so VGS is fixed
The resulting current,

VGS 2
ID IDSS(1
)
VP

 Investigating the graphical approach.

Using below tables, we can draw the graph
VGS

ID

IDSS

0.3VP

IDSS/2

0.5

IDSS/4

VP

0mA

 The fixed level of VGS has been superimposed as a verti

cal line at

VGS VGG

At any point on the vertical line, the level of VG is -VG

G

--- the level of ID must simply be determined on this ve

rtical line.
The point where the two curves intersect is the common
solution to the configuration commonly referrers to as
the quiescent or operating point.
The quiescent level of ID is determine by drawing a hori
zontal line from the Q-point to the vertical ID axis.

 Output loop
VDS VDD I D RD
VS 0V
V DS VD VS
V D V DS VS

VS 0

VD V DS
VGS VG VS
VG VGS VS
VG VGS

VS 0

Example
Determine VGSQ, IDQ, VDS, VD, VG, VS

Exercise
Determine IDQ, VGSQ, VDS, VD, VG and VS

Self Bias Configuration

The self-bias configuration eliminates the need for two dc sup
plies.
The controlling VGS is now determined by the voltage across th
e resistor RS

 For the indicated input loop:

VGS I D RS
Mathematical approach:
ID
ID

VGS

I DSS 1
VP

I D RS
I DSS 1
VP

rearrange and solve.

 Graphical approach
Draw the device transfer characteristic
Draw the network load line

VGSto draw
I D Rstraight
Use
S
line.
I D 0, VGS 0
First point,
Second point, any point from ID = 0 to ID = IDSS. Choose
I DSS
then
2
I R
DSS S
2

ID
VGS

the quiescent point obtained at the intersection of the straight lin

e plot and the device characteristic curve.
The quiescent value for ID and VGS can then be determined and u
sed to find the other quantities of interest.

 For output loop

Apply KVL of output loop
Use ID = IS

V DS V DD I D ( RS R D )
VS I D RS
V D V DS VS V DD V RD

Example
Determine VGSQ, IDQ,VDS,VS,VG and VD.

Example
Determine VGSQ, IDQ, VD,VG,VS and VDS.

Voltage-Divider Bias
The arrangement is the same as BJT but the DC analysi
s is different
In BJT, IB provide link to input and output circuit, in F
ET VGS does the same

Voltage-Divider Bias
The source VDD was separated into two equivalent sources to per
mit a further separation of the input and output regions of the net
work.
IG = 0A ,Kirchoffs current law requires that IR1= IR2 and the series
equivalent circuit appearing to the left of the figure can be used to
find the level of VG.

Voltage-Divider Bias
VG can be found using the voltage divider rule :
R2VDD
VG
R1 R2

Using Kirchoffs Law on the input loop:

RearrangingVGand
VGSusing
VRS ID
0 =IS:
VGS VG I D RS

Again the Q point needs to be established by plo

tting a line that intersects the transfer curve.

Procedures for plotting

1. Plot the line: By plotting two points: VGS = VG, ID =0 and VGS = 0,
ID = VG/RS
2. Plot the transfer curve by plotting IDSS, VP and calculated values of ID.
3. Where the line intersects the transfer curve is the Q point for the
circuit.

 Once the quiescent values of IDQ and VGSQ are dete

rmined, the remaining network analysis can be fou
nd.
I R1 I R 2

Output loop:

V DD

R1 R2

VDS VDD I D ( RD I D RS )
V D VDD I D RD

VS I D RS

Effect of increasing values of RS

Example
Determine IDQ, VGSQ, VD, VS, VDS and VDG.

Example
Determine IDQ, VGSQ, VDS, VD and VS

Depletion-Type MOSFETs
Depletion-type MOSFET bias circuits are similar to JFETs. The
only difference is that the depletion-Type MOSFETs can operate
with positive values of VGS and with ID values that exceed IDSS.

Depletion-Type MOSFETs
The DC Analysis

Same as the FET calculations

Plotting the transfer characteristics of the device
Plotting the at a point that VGS exceeds the 0V or more
positive values
Plotting point when VGS=0V and ID=0A
The intersection between Shockley characteristics and linear
characteristics defined the Q-point of the MOSFET
The problem is that how long does the transfer
characteristics have to be draw?
We have to analyze the input loop parameter relationship.
As RS become smaller, the linear characteristics will be in
narrow slope therefore needs to consider the extend ofVG VGS VRS 0
transfer characteristics for example of voltage divider V V I R
GS
G
D S
MOSFET,
The bigger values of VP the more positive values we should

 Analyzing the MOSFET circuit for DC

analysis
How to analyze dc analysis
for the shown network?
It

is a . Type network
Find VG or VGS
Draw

the linear
characteristics
Draw the transfer
characteristics
Obtain VGSQ and IDQ from
the graph intersection

1.Plot line for VGS = VG, ID = 0 and ID = VG/RS, VGS = 0

2. Plot the transfer curve by plotting IDSS, VP and calculated values
of ID.
3. Where the line intersects the transfer curve is the Q-point.
Use the ID at the Q-point to solve for the other variables in the
voltage-divider bias circuit. These are the same calculations as used
by a JFET circuit.

 When RS changethe linear characteristics will change..

1.Plot line for VGS = VG, ID = 0 and ID = VG/RS, VGS = 0
2. Plot the transfer curve by plotting IDSS, VP and calculated values
of ID.
3. Where the line intersects the transfer curve is the Q-point.
Use the ID at the Q-point to solve for the other variables in the
voltage-divider bias circuit. These are the same calculations as used
by a JFET circuit.

Enhancement-Type MOSFET
The transfer characteristic for the enhancement-type MOSFET is
very different from that of a simple JFET or the depletion-type
MOSFET.

 Transfer characteristic for E-MOSFET

I D k (VGS VGS (Th ) )

and
k

I D ( on )
(VGS ( on ) VGS (Th ) ) 2

Feedback Biasing Arrangement

IG =0A, therefore VRG = 0V

Therefore: VDS = VGS
Which makes VGS V DD I D R D

Feedback Biasing Q-Point

1. Plot the line using VGS = VDD, ID = 0 and ID = VDD / RD and VGS =
0
2. Plot the transfer curve using VGSTh , ID = 0 and VGS(on), ID(on); all
given in the specification sheet.
3. Where the line and the transfer curve intersect is the Q-Point.
4. Using the value of ID at the Q-point, solve for the other variables
in the bias circuit.

DC analysis step for Feedback Biasing

Enhancement type MOSFET
Find

k using the datasheet or specification given;

ex: VGS(ON),VGS(TH)

Plot

transfer characteristics using the formula

ID=k(VGS VT)2. Three point already defined that is
ID(ON), VGS(ON) and VGS(TH)

Plot
Plot

a point that is slightly greater than VGS

the linear characteristics (network bias line)

The intersection defines the Q-point

Example
Determine IDQ and VDSQ for network below

Voltage-Divider Biasing

Again plot the line and the transfer curve to find the Q-point.
Using the following equations: VG R2VDD
R1 R2
Input loop : VGS VG I D RS
Output loop: VDS VDD I D ( RS RD )

Voltage-Divider Bias Q-Point

1. Plot the line using VGS = VG = (R2VDD)/(R1 + R2), ID = 0 and ID =
VG/RS and VGS = 0
2. Find k
3. Plot the transfer curve using VGSTh, ID = 0 and VGS(on), ID(on); all
given in the specification sheet.
4. Where the line and the transfer curve intersect is the Q-Point.
5. Using the value of ID at the Q-point, solve for the other variables
in the bias circuit.

Example
Determine IDQ and VGSQ and VDS for network
below

 = = -

= = - ( + )

=
+
= = - ( + )

= = + - ( + )

=
=

 ==
=
= = = =
= + = - ( + )
=
= =
+
= -

Troubleshooting
N-channel

VGSQ will be 0V or negative if

properly checked
Level of VDS is ranging from 25%~75% of VDD.
If 0V indicated, theres problem
Check with the calculation between each
terminal and ground. There must be a reading, R G
will be excluded

P-Channel FETs
For p-channel FETs the same calculations and graphs are used,
except that the voltage polarities and current directions are the
opposite. The graphs will be mirrors of the n-channel graphs.

Practical Applications
VoltageControlledResistor
JFETVoltmeter
TimerNetwork
FiberOpticCircuitry
MOSFETRelayDriver

Thanking You