Electronic Devices and Circuits

JFET Biasing Techniques

Dr. Junaid Ahmed

Contents
JFET Biasing
 Bias Battery
 Biasing Circuit
JFET Biasing by Bias Battery
Numerical problems
Self-Biasing for JFET
 Operating Point
 Midpoint Bias
Numerical problems
JFET with Voltage-Divider Bias
Numerical problems
JFET Connections
Variation of transconductance (gm or gfs) of JFET
Practical JFET Amplifier
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Contents
JFET Applications
 Buffer Amplifier
 Phase-shift Oscillator
 RF Amplifier

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JFET Biasing:
Biasing is very important in amplifier circuits in order to achieve
faithful amplification.

For n-channel JFET, gate must be negative w.r.t. source.

This can be achieved either by inserting a battery in the gate

circuit or by a circuit known as biasing circuit.

The insertion of biasing circuit method is mostly preferred because

batteries are costly and require frequent replacement.

1. Bias battery:
“In this method, JFET is biased by a bias battery VGG. This
battery ensures that gate is always negative w.r.t. source during all
parts of the signal.”
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JFET Biasing: (cont.)
2. Biasing circuit:
“The biasing circuit uses supply voltage VDD to
provide the necessary bias. Two most commonly used
methods are:
I. Self-bias
II. Potential divider method

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JFET Biasing by Bias Battery:
Figure-1 shows the biasing of a
n-channel JFET by a bias
battery —VGG, this method is
also called gate bias.

The battery voltage -VGG

ensures that gate-source
junction remains reverse biased.

Since there is no gate current,

there will be no voltage drop
across RG.

VGS = VGG Figure-1

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JFET Biasing by Bias Battery: (cont.)
The value of drain current ID from the following
relation :

The value of VDS is given by:

VDS = VDD – ID RD

Thus the d.c. values of ID and VDS are the operating

points of circuit and stand determined.
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Numerical problems:
Problem-1:
Fig: 2

Solution:

Fig: 2

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Self-Biasing for JFET:
Figure-3 shows the self-bias
method for n-channel JFET.

The resistor RS is the bias

resistor.

The d.c. component of drain

current flowing through RS
produces the desired bias
voltage.

Voltage across RS, VS = IDRS Figure-3

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Self-Biasing for JFET: (cont.)
Since gate current is negligibly small, the
gate terminal is at d.c. ground i.e., VG = 0.
VGS = VG - VS = 0 — IDRS
or
VGS = -*IDRS

Thus bias voltage VGS keeps gate negative

w.r.t. source.
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Self-Biasing for JFET: (cont.)
Operating point:
 The operating point (zero signal ID and VDS) can be easily determined.

 The parameters of the JFET are usually known, zero signal ID can be
calculated from the following relations:

 Thus d.c. conditions of JFET amplifier are fully specified i.e. operating
point for the circuit is VDS, ID:

Also,

 Note that gate resistor *RG does not affect bias because voltage across it is
zero. 11
Self-Biasing for JFET: (cont.)
Midpoint Bias:
It is often desirable to bias a JFET near the midpoint of its transfer
characteristic curve where ID = IDSS/2.

When signal is applied, the midpoint bias allows a maximum

amount of drain current swing between IDSS and 0.

It can be proved that when VGS = VGS(off)/3.4, midpoint bias

conditions are obtained for ID.

To set the drain voltage at midpoint (VD = VDD/2), select a value of
RD to produce the desired voltage drop.
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Numerical problems:
Problem-2:
Fig:4

Solution:

Fig:4

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Numerical problems: (cont.)
Problem-3:

Solution:

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Numerical problems: (cont.)
Problem-4:

Solution:

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Numerical problems: (cont.)
Problem-5: Fig:5

Figure-5

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Numerical problems: (cont.)
Solution:

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JFET with Voltage-Divider Bias:
Figure-6 shows potential
divider method of biasing a
JFET.

This circuit is identical to that

used for a transistor.

The resistors R1 and R2 form a

voltage divider across drain
supply VDD.

The voltage V2 (= VG) across R2 Figure-6

provides the necessary bias.
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JFET with Voltage-Divider Bias:(cont.)

The circuit is so designed that IDRS is larger than I2

so that VGS is negative, this provides correct bias
voltage.

The operating point are given as:

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JFET with Voltage-Divider Bias: :(cont.)
Although the circuit of voltage-divider bias is a bit complex,
yet the advantage of this method of biasing is that it provides
good stability of the operating point.

The input impedance Z1 of this circuit is given by:

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Numerical problems:
Problem-6:
Fig: 7

Figure-7

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Numerical problems: (cont.)
Solution:

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JFET Connections: (cont.)
There are three leads in a JFET (source, gate and drain) terminals.

To connect JFET in a circuit, four terminals ; two for the input and
two for the output.

This difficulty is overcome by making one terminal of the JFET

common to both input and output terminals.

Accordingly, a JFET can be connected in a circuit in the following

three ways:

1. Common source connection

2. Common gate connection
3. Common drain connection
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JFET Connections: (cont.)
The common source connection is the most widely used
arrangement.

Common source connection provides high input

impedance, good voltage gain and a moderate output
impedance.

However, the circuit produces a phase reversal i.e.,

output signal is 180° out of phase with the input signal.

Figure-8 shows a common source n-channel JFET

amplifier. Note that source terminal is common to both
input and output.
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JFET Connections: (cont.)

Figure-8: Common Source Connection

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JFET Connections: (cont.)
 A common source JFET amplifier is the JFET equivalent of
common emitter amplifier.

Both amplifiers have a 180° phase shift from input to output.

Both amplifiers (JFET & BJT) serve the same basic purpose,
the means by which they operate are quite different.

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Variation of transconductance of JFET:
The transconductance gm of a JFET is the ratio of a change in
drain current (∆ID) to a change in gate-source voltage (∆VGS) at
constant VDS i.e.

The transconductance gm of a JFET is an important parameter

because it is a major factor in determining the voltage gain of
JFET amplifiers.

The transfer characteristic curve for a JFET is nonlinear so that

the value of gm depends upon the location on the curve.
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Variation of transconductance of JFET: (cont.)
The value of gm at point
A in Figure-9 will be
different from that at
point B.

The following equation to

determine the value of gm
at a specified value of VGS.

Figure-9:
Transfer characteristic

curve
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Variation of transconductance of JFET: (cont.)
Where:
 gm= value of transconductance at any point on the transfer
characteristic curve
 gmo= value of transconductance (maximum) at VGS = 0

Normally, the data sheet provides the value of gmo.

When the value of gmo is not available, it can approximately

be calculated using the following relation :

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Practical JFET Amplifier:
 It is important to note that a JFET can accomplish faithful amplification
only if proper associated circuitry is used.

 Figure-8 shows the practical circuit of a JFET.

 The gate resistor RG serves two purposes: It keeps the gate at

approximately 0 V dc ( gate current is nearly zero) and its large value
(usually several mega-ohms) prevents loading of the a.c. signal source.

 The bias voltage is created by the drop across RS.

 The bypass capacitor CS bypasses the a.c. signal and thus keeps the
source of the JFET effectively at a.c. ground.

 The coupling capacitor Cin couples the signal to the input of JFET
amplifier.
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JFET Applications:
The high input impedance, low output
impedance and low noise level make JFET far
superior to the bipolar transistor.

Some of the circuit applications of JFET are:

 Buffer Amplifier
 Phase-shift Oscillator
 RF Amplifier

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JFET Applications: (cont.)
1. As a buffer amplifier:
A buffer amplifier is a stage of amplification that isolates the
preceding stage from the following stage.

Because of the high input impedance and low output

impedance, a JFET can act as an excellent buffer amplifier as
given in Figure-10.

Figure-10 32
JFET Applications: (cont.)
1. As a buffer amplifier: (cont.)
The high input impedance of JFET means light
loading of the preceding stage.

This permits almost the entire output from first stage

to appear at the buffer input.

The low output impedance of JFET can drive heavy

loads (or small load resistances).

This ensures that all the output from the buffer

reaches the input of the second stage.
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JFET Applications: (cont.)
2. Phase-shift oscillators:
The oscillators also work with JFETs. However, the high
input impedance of JFET is especially valuable in phase-
shift oscillators to minimize the loading effect.

3. As RF amplifier:
In communication electronics, we have to use JFET RF
amplifier in a receiver instead of BJT amplifier for the
following reasons:

a. The noise level of JFET is very low. The JFET will

not generate significant amount of noise and is
thus useful as an RF amplifier.
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JFET Applications: (cont.)
b. The antenna of the receiver receives a very weak signal
that has an extremely low amount of current. Since
JFET is a voltage controlled device, it will well respond
to low current signal provided by the antenna.

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Any Questions ????????

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