Quad Precision, High

Speed Operational Amplifier

OP467
FEATURES PIN CONFIGURATIONS
High slew rate: 170 V/μs
OUT A 1 14 OUT D
Wide bandwidth: 28 MHz –IN A 2 + + 13 –IN D
Fast settling time: <200 ns to 0.01% +IN A 3 12 +IN D

Low offset voltage: <500 μV V+ 4 OP467 11 V–

Unity-gain stable +IN B 5 10 +IN C

+ +
–IN B 6 9 –IN C
Low voltage operation: ±5 V to ±15 V

00302-001
OUT B 7 8 OUT C
Low supply current: <10 mA
Drives capacitive loads Figure 1. 14-Lead CERDIP (Y Suffix) and 14-Lead PDIP (P Suffix)

OUT A

OUT D
APPLICATIONS

–IN A

–IN D
NC
High speed image display drivers 3 2 1 20 19

High frequency active filters

+IN A 4 18 +IN D
Fast instrumentation amplifiers OUT A 1 16 OUT D
NC 5 17 NC
–IN A 2 15 –IN D
OP467
High speed detectors V+ 6 16 V–
+IN A 3 14 +IN D (TOP VIEW)
Integrators NC 7 15 NC
V+ 4 OP467 13 V–
Photo diode preamps +IN B 8 14 +IN C

00302-003
+IN B 5 12 +IN C

–IN B 6 11 –IN C
GENERAL DESCRIPTION OUT B 7 10 OUT C
9 10 11 12 13

OUT C
NC

–IN C
OUT B
–IN B
00302-002
The OP467 is a quad, high speed, precision operational NC 8 9 NC

amplifier. It offers the performance of a high speed op amp NC = NO CONNECT NC = NO CONNECT

combined with the advantages of a precision op amp in a single Figure 2. 16-Lead SOIC (S Suffix) Figure 3. 20-Terminal LCC (RC Suffix)
package. The OP467 is an ideal choice for applications where,
traditionally, more than one op amp was used to achieve this V+
level of speed and precision.
The internal compensation of the OP467 ensures stable unity-
gain operation, and it can drive large capacitive loads without
oscillation. With a gain bandwidth product of 28 MHz driving a
30 pF load, output slew rate is 170 V/μs, and settling time to
0.01% in less than 200 ns, the OP467 provides excellent
+IN OUT
dynamic accuracy in high speed data acquisition systems. The –IN

channel-to-channel separation is typically 60 dB at 10 MHz.

The dc performance of the OP467 includes less than 0.5 mV of
offset, a voltage noise density below 6 nV/√Hz, and a total
supply current under 10 mA. The common-mode rejection
ratio (CMRR) is typically 85 dB. The power supply rejection V– 00302-004

ratio (PSRR) is typically 107 dB. PSRR is maintained to better than

40 dB with input frequencies as high as 1 MHz. The low offset and Figure 4. Simplified Schematic
drift plus high speed and low noise make the OP467 usable in
applications such as high speed detectors and instrumentation.
The OP467 is specified for operation from ±5 V to ±15 V over
the extended industrial temperature range (−40°C to +85°C)
and is available in a 14-lead PDIP, a 14-lead CERDIP, a 16-lead
SOIC, and a 20-terminal LCC.
Contact your local sales office for the MIL-STD-883 data sheet
and availability.
Rev. *
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 www.analog.com
Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 ©3–20 Analog Devices, Inc. All rights reserved.
OP467

TABLE OF CONTENTS
Features .............................................................................................. 1  Output Short-Circuit Performance .......................................... 13 
Applications ....................................................................................... 1  Unused Amplifiers ..................................................................... 13 
General Description ......................................................................... 1  PCB Layout Considerations ...................................................... 13 
Pin Configurations ........................................................................... 1  Grounding ................................................................................... 13 
Revision History ............................................................................... 2  Power Supply Considerations ................................................... 13 
Specifications..................................................................................... 3  Signal Considerations ................................................................ 13 
Electrical Characteristics ............................................................. 3  Phase Reversal ............................................................................ 14 
Wafer Test Limits .......................................................................... 5  Saturation Recovery Time ......................................................... 14 
Absolute Maximum Ratings............................................................ 6  High Speed Instrumentation Amplifier .................................. 14 
Thermal Resistance ...................................................................... 6  2 MHz Biquad Band-Pass Filter ............................................... 15 
Dice Characteristics ..................................................................... 6  Fast I-to-V Converter ................................................................ 16 
ESD Caution .................................................................................. 6  OP467 SPICE Marco-Model ..................................................... 17 
Typical Performance Characteristics ............................................. 7  Outline Dimensions ....................................................................... 19 
Applications Information .............................................................. 13  Ordering Guide .......................................................................... 20 

REVISION HISTORY
4/10—Rev. H to Rev. I 3/04—Rev. D to Rev. E
Deleted Endnote 2 From Table 1 .................................................... 3 Changes to TPC 1 ..............................................................................5
Changes to Ordering Guide .............................................................4
8/09—Rev. G to Rev. H Updated Outline Dimensions ....................................................... 16
Changes to Table 4 ............................................................................ 6
4/01—Rev. C to Rev. D
4/09—Rev. F to Rev. G Footnote added to Power Supply.....................................................2
Changes to Power Supply Considerations Section..................... 13 Footnote added to Max Ratings ......................................................4
Edits to Power Supply Considerations Section........................... 11
5/07—Rev. E to Rev. F
Updated Format .................................................................. Universal
Changes to General Description .................................................... 1
Changes to Table 1 ............................................................................ 3
Changes to Table 2 ............................................................................ 4
Changes to Table 3 ............................................................................ 5
Updated Outline Dimensions ....................................................... 19
Changes to Ordering Guide .......................................................... 20

Rev. I | Page 2 of 20
 OP467

SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
@ VS = ±15.0 V, TA = 25°C, unless otherwise noted.

Table 1.
Parameter Symbol Conditions Min Typ Max Unit
INPUT CHARACTERISTICS
Offset Voltage VOS 0.2 0.5 mV
−40°C ≤ TA ≤ +85°C 1 mV
Input Bias Current IB VCM = 0 V 150 600 nA
VCM = 0 V, −40°C ≤ TA ≤ +85°C 150 700 nA
Input Offset Current IOS VCM = 0 V 10 100 nA
VCM = 0 V, −40°C ≤ TA ≤ +85°C 10 150 nA
Common-Mode Rejection CMR VCM = ±12 V 80 90 dB
CMR VCM = ±12 V, −40°C ≤ TA ≤ +85°C 80 88 dB
Large Signal Voltage Gain AVO RL = 2 kΩ 83 86 dB
RL = 2 kΩ, −40°C ≤ TA ≤ +85°C 77.5 dB
Offset Voltage Drift ΔVOS/ΔT 3.5 μV/°C
Bias Current Drift ΔIB/ΔT 0.2 pA/°C
Long-Term Offset Voltage Drift1 ΔVOS/ΔT 750 μV
OUTPUT CHARACTERISTICS
Output Voltage Swing VO RL = 2 kΩ ±13.0 ±13.5 V
RL = 2 kΩ, −40°C ≤ TA ≤ +85°C ±12.9 ±13.12 V
POWER SUPPLY
Power Supply Rejection Ratio PSRR ±4.5 V ≤ VS ≤ ±18 V 96 120 dB
−40°C ≤ TA ≤ +85°C 86 115 dB
Supply Current ISY VO = 0 V 8 10 mA
VO = 0 V, −40°C ≤ TA ≤ +85°C 13 mA
Supply Voltage Range VS ±4.5 ±18 V
DYNAMIC PERFORMANCE
Gain Bandwidth Product GBP AV = +1, CL = 30 pF 28 MHz
Slew Rate SR VIN = 10 V step, RL = 2 kΩ, CL = 30 pF
AV = +1 125 170 V/μs
AV = −1 350 V/μs
Full-Power Bandwidth BWρ VIN = 10 V step 2.7 MHz
Settling Time tS To 0.01%, VIN = 10 V step 200 ns
Phase Margin θ0 45 Degrees
Input Capacitance
Common Mode 2.0 pF
Differential 1.0 pF
NOISE PERFORMANCE
Voltage Noise eN p-p f = 0.1 Hz to 10 Hz 0.15 μV p-p
Voltage Noise Density eN f = 1 kHz 6 nV/√Hz
Current Noise Density iN f = 1 kHz 0.8 pA/√Hz
1
Long-term offset voltage drift is guaranteed by 1000 hrs. Life test performed on three independent wafer lots at 125°C, with an LTPD of 1.3.

Rev. I | Page 3 of 20
OP467
@ VS = ±5.0 V, TA = 25°C, unless otherwise noted.

Table 2.
Parameter Symbol Conditions Min Typ Max Unit
INPUT CHARACTERISTICS
Offset Voltage VOS 0.3 0.5 mV
−40°C ≤ TA ≤ +85°C 1 mV
Input Bias Current IB VCM = 0 V 125 600 nA
VCM = 0 V, −40°C ≤ TA ≤ +85°C 150 700 nA
Input Offset Current IOS VCM = 0 V 20 100 nA
VCM = 0 V, −40°C ≤ TA ≤ +85°C 150 nA
Common-Mode Rejection CMR VCM = ±2.0 V 76 85 dB
CMR VCM = ±2.0 V, −40°C ≤ TA ≤ +85°C 76 80 dB
Large Signal Voltage Gain AVO RL = 2 kΩ 80 83 dB
RL = 2 kΩ, −40°C ≤ TA ≤ +85°C 74 dB
Offset Voltage Drift ΔVOS/ΔT 3.5 μV/°C
Bias Current Drift ΔIB/ΔT 0.2 pA/°C
OUTPUT CHARACTERISTICS
Output Voltage Swing VO RL = 2 kΩ ±3.0 ±3.5 V
RL = 2 kΩ, −40°C ≤ TA ≤ +85°C ±3.0 ±3.20 V
POWER SUPPLY
Power Supply Rejection Ratio PSRR ±4.5 V ≤ VS ≤ ±5.5 V 92 107 dB
−40°C ≤ TA ≤ +85°C 83 105 dB
Supply Current ISY VO = 0 V 8 10 mA
VO = 0 V, −40°C ≤ TA ≤ +85°C 12 mA
DYNAMIC PERFORMANCE
Gain Bandwidth Product GBP AV = +1 22 MHz
Slew Rate SR VIN = 5 V step, RL = 2 kΩ, CL = 39 pF
AV = +1 90 V/μs
AV = −1 90 V/μs
Full-Power Bandwidth BWρ VIN = 5 V step 2.5 MHz
Settling Time tS To 0.01%, VIN = 5 V step 280 ns
Phase Margin θ0 45 Degrees
NOISE PERFORMANCE
Voltage Noise eN p-p f = 0.1 Hz to 10 Hz 0.15 μV p-p
Voltage Noise Density eN f = 1 kHz 7 nV/√Hz
Current Noise Density iN f = 1 kHz 0.8 pA/√Hz

Rev. * | Page 4 of 20
 OP467
WAFER TEST LIMITS 1
@ VS = ±15.0 V, TA = 25°C, unless otherwise noted.

Table 3.
Parameter Symbol Conditions Limit Unit
Offset Voltage VOS ±0.5 mV max
Input Bias Current IB VCM = 0 V 600 nA max
Input Offset Current IOS VCM = 0 V 100 nA max
Input Voltage Range 2 ±12 V min/max
Common-Mode Rejection Ratio CMRR VCM = ±12 V 80 dB min
Power Supply Rejection Ratio PSRR V = ±4.5 V to ±18 V 96 dB min
Large Signal Voltage Gain AVO RL = 2 kΩ 83 dB min
Output Voltage Range VO RL = 2 kΩ ±13.0 V min
Supply Current ISY VO = 0 V, RL = ∞ 10 mA max
1
Electrical tests and wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for standard
product dice. Consult sales to negotiate specifications based on dice lot qualifications through sample lot assembly and testing.
2
Guaranteed by CMR test.

Rev. * | Page 5 of 20
OP467

ABSOLUTE MAXIMUM RATINGS

Table 4.
Parameter 1 Rating Stresses above those listed under Absolute Maximum Ratings
Supply Voltage ±18 V may cause permanent damage to the device. This is a stress
Input Voltage 2 ±18 V rating only; functional operation of the device at these or any
Differential Input Voltage2 ±26 V other conditions above those indicated in the operational
Output Short-Circuit Duration Limited section of this specification is not implied. Exposure to absolute
Storage Temperature Range maximum rating conditions for extended periods may affect
14-Lead CERDIP and 20-Terminal LCC −65°C to +175°C device reliability.
14-Lead PDIP and 16-Lead SOIC −65°C to +150°C THERMAL RESISTANCE
Operating Temperature Range
θJA is specified for the worst-case conditions, that is, a device
OP467A −55°C to +125°C
soldered in a circuit board for surface-mount packages.
OP467G −40°C to +85°C
Junction Temperature Range Table 5.
14-Lead CERDIP and 20-Terminal LCC −65°C to +175°C Package Type θJA1 θJC Unit
14-Lead PDIP and 16-Lead SOIC −65°C to +150°C 14-Lead CERDIP (Y) 94 10 °C/W
Lead Temperature (Soldering, 60 sec) 300°C 14-Lead PDIP (P) 76 33 °C/W
1
Absolute maximum ratings apply to both DICE and packaged parts, unless 16-Lead SOIC (S) 88 23 °C/W
otherwise noted. 20-Terminal LCC (RC) 78 33 °C/W
2
For supply voltages less than ±18 V, the absolute maximum input voltage is
1
equal to the supply voltage. θJA is specified for the worst-case conditions, that is, θJA is specified for device
in socket for CERDIP, PDIP, and LCC packages, and θJA is specified for device
soldered in circuit board for the SOIC package.

DICE CHARACTERISTICS

OUT A

OUT D
–IN A 2 1 14 13 –IN D

+IN A 3 12 +IN D

V+ 4
11 V–

+IN B 5 10 +IN C

00302-005

–IN B 6 7 8 9 –IN C
OUT B

OUT C

Figure 5. 0.111 Inch × 0.100 Inch DIE Size, 11,100 sq. mils,
Substrate Connected to V+, 165 Transistors

ESD CAUTION

Rev. * | Page 6 o f 20
 OP467

TYPICAL PERFORMANCE CHARACTERISTICS

100
80
VS = ±15V
VS = ±15V TA = 25°C
70 RL = 1MΩ
CL = 30pF 80
60

AVCL = +100

PHASE SHIFT (Degrees)

50
OPEN-LOOP GAIN (dB)

IMPEDANCE (Ω)
GAIN
60
40

30
40
20 –90
PHASE AVCL = +10
10 –135
20
0 –180

00302-009
AVCL = +1

00302-006
–10
0
–20 100 1k 10k 100k 1M
1k 10k 100k 1M 10M 100M
FREQUENCY (Hz)
FREQUENCY (Hz)

Figure 6. Open-Loop Gain, Phase vs. Frequency Figure 9. Closed-Loop Output Impedance vs. Frequency

80

VS = ±15V
TA = 25°C
0.3
60
VS = ±5V
CLOSED-LOOP GAIN (dB)

GAIN ERROR (dB) 0.2

0.1
40
0.0
VS = ±15V
–0.1
20
–0.2

0 –0.3

00302-010
00302-007

0
–20 3.4 5.8
100k 1M 10M
10k 100k 1M 10M 100M
FREQUENCY (Hz)
FREQUENCY (Hz)

Figure 7. Closed-Loop Gain vs. Frequency Figure 10. Gain Error vs. Frequency

25 30

AVCL = –1

25
20
MAXIMUM OUTPUT SWING (V)

TA = +125°C AVCL = +1
OPEN-LOOP GAIN (V/mV)

20
15

15
TA = +25°C
10
TA = –55°C 10

5 VS = ±15V
5
TA = 25°C
00302-011
00302-008

RL = 2kΩ

0 0
0 ±5 ±10 ±15 ±20 1k 10k 100k 1M 10M
SUPPLY VOLTAGE (V) FREQUENCY (Hz)

Figure 8. Open-Loop Gain vs. Supply Voltage Figure 11. Maximum VOUT Swing vs. Frequency

Rev. * | Page 7 of 20
OP467

12 60
VS = ±5V VS = ±15V
AVCL = +1
TA = 25°C RL = 2kΩ
10 RL = 2kΩ 50 VVIN = 100mV p-p
AVCL = +1
MAXIMUM OUTPUT SWING (V)

AVCL = –1

8 40

OVERSHOOT (%)
AVCL = –1
6 30

4 20

2 10

00302-012

00302-015
0 0
1k 10k 100k 1M 10M 0 200 400 600 800 1000 1200 1400 1600
FREQUENCY (Hz) LOAD CAPACITANCE (pF)

Figure 12. Maximum VOUT Swing vs. Frequency Figure 15. Small Signal Overshoot vs. Load Capacitance

120 60
VS = ±15V VS = ±15V
TA = 25°C AVCL = +1
RL = 2kΩ
100 50 VVIN = 100mV p-p
COMMON-MODE REJECTION (V)

AVCL = –1

80 40
OVERSHOOT (%)

60 30

40 20

20 10
00302-013

00302-016
0 0
1k 10k 100k 1M 10M 0 200 400 600 800 1000 1200 1400 1600
FREQUENCY (Hz) LOAD CAPACITANCE (pF)

Figure 13. Common-Mode Rejection vs. Frequency Figure 16. Small Signal Overshoot vs. Load Capacitance

120 60
VS = ±15V VS = ±15V
TA = 25°C 50
100
POWER SUPPLY REJECTION (dB)

40

30
80 1000pF 500pF
20
GAIN (dB)

200pF
60 10 10000pF

0
40
–10
CIN = NETWORK
–20 ANALYZER
20
00302-014

00302-017

–30

0 –40
100 1k 10k 100k 1M 10k 100k 1M 10M 100M
FREQUENCY (Hz) FREQUENCY (Hz)

Figure 14. Power-Supply Rejection vs. Frequency Figure 17. Noninverting Gain vs. Capacitive Loads

Rev. * | Page 8 of 20
 OP467
0 4
VS = ±15V VS = ±15V
–10 3 VIN = ±5V
CL = 50pF
–20
CHANNEL SEPARATION (dB)

2
–30

VOUT ERROR (mV)

1
–40

–50 0

–60
–1
–70
–2
–80
–3

00302-021
00302-018
–90

–100 –4
100 1k 10k 100k 1M 10M 100M 0 100 200 300 400 500
FREQUENCY (Hz) TIME (ns)

Figure 18. Channel Separation vs. Frequency Figure 21. Settling Time, Negative Edge

12 4

±5V ≤ VS ≤ 15V VS = ±15V

INPUT CURRENT NOISE DENSITY (pA/√Hz)

3 VIN = ±5V
10 CL = 50pF
2

8
VOUT ERROR (mV)
1

6 0

–1
4
–2

2
–3

00302-022
00302-019

0 –4
1 10 100 1k 0 100 200 300 400 500
FREQUENCY (Hz) TIME (ns)

Figure 19. Input Current Noise Density vs. Frequency Figure 22. Settling Time, Positive Edge

100 20
TA = 25°C
15
VOLTAGE NOISE DENSITY (nV/√Hz)

INPUT VOLTAGE RANGE (V)

10

10 0

–5

–10

–15
00302-020

00302-023

1.0 –20
0.1 1 10 100 1k 10k 0 ±5 ±10 ±15 ±20
FREQUENCY (Hz) SUPPLY VOLTAGE (V)

Figure 20. Voltage Noise Density vs. Frequency Figure 23. Input Voltage Range vs. Supply Voltage

Rev. * | Page 9 of 20
OP467

50 500
VS1 = ±15V VS = ±15V
40 TA = 25°C
VS2 = ±5V
1252 × OP AMPS
RL = 10kΩ 400
30
CL = 50pF
20
VS1 = ±15V
10 300
GAIN (dB)

UNITS
0

–10 200
VS2 = ±5V
–20

–30 100

00302-027
00302-024
–40

–50 0
100k 1M 10M 100M –100 –50 0 50 100 150 200 250 300 350 400
10k
FREQUENCY (Hz) INPUT OFFSET VOLTAGE (VOS µV)

Figure 24. Noninverting Gain vs. Supply Voltage Figure 27. Input Offset Voltage Distribution

14 500
VS = ±15V VS = ±5V
TA = 25°C TA = 25°C
12 1252 × OP AMPS
400

10
OUTPUT SWING (V)

POSITIVE
SWING 300
8
UNITS

6 200
NEGATIVE
SWING
4
100
2

00302-028
00302-025

0 0
–100 –50 0 50 100 150 200 250 300 350 400
10 100 1k 10k
LOAD RESISTANCE (Ω) INPUT OFFSET VOLTAGE (VOS µV)

Figure 25. Output Swing vs. Load Resistance Figure 28. Input Offset Voltage Distribution

5 500
VS = ±15V VS = ±15V
TA = 25°C TA = 25°C
1252 × OP AMPS
4 400
POSITIVE
SWING
OUTPUT SWING (V)

3 300
UNITS

NEGATIVE
SWING
2 200

1 100
00302-026

00302-029

0 0
10 100 1k 10k 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
LOAD RESISTANCE (Ω) TC VOS (µV/°C)

Figure 26. Output Swing vs. Load Resistance Figure 29. TC VOS Distribution

Rev. * | Page 10 of 20
 OP467

500 400
VS = ±5V
VS = ±5V
TA = 25°C
350 RL = 2kΩ
1252 × OP AMPS AVCL = +1
400
300

SLEW RATE (V/µs)

300 250
UNITS

200

200 +SR
150

100
100 –SR

50

00302-030

00302-033
0 0
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 –75 –50 –25 0 25 50 75 100 125
TC VOS (µV/°C) TEMPERATURE (°C)

Figure 30. TC VOS Distribution Figure 33. Slew Rate vs. Temperature

60 29.0 650
VS = ±15V
600 RL = 2kΩ
GBW AVCL = –1
GAIN BANDWIDTH PRODUCT (MHz)

–SR
55 28.5 550
PHASE MARGIN (Degrees)

VS = ±5V
SLEW RATE (V/µs)

RL = 2kΩ 500
+SR
50 28.0 450

ФM 400

45 27.5 350

300
00302-031

00302-034
40 27.0 250
–75 –50 –25 0 25 50 75 100 125 –75 –50 –25 0 25 50 75 100 125
TEMPERATURE (°C) TEMPERATURE (°C)

Figure 31. Phase Margin and Gain Bandwidth vs. Temperature Figure 34. Slew Rate vs. Temperature

400 400
VS = ±5V VS = ±15V
RL = 2kΩ RL = 2kΩ
350 350 AVCL = +1
AVCL = –1

300 300
+SR
SLEW RATE (V/µs )

SLEW RATE (V/µs)

250 250
–SR

200 200
+SR
–SR
150 150

100 100

50 50
00302-032

00302-035

0 0
–75 –50 –25 0 25 50 75 100 125 –75 –50 –25 0 25 50 75 100 125
TEMPERATURE (°C) TEMPERATURE (°C)

Figure 32. Slew Rate vs. Temperature Figure 35. Slew Rate vs. Temperature

Rev. * | Page 11 of 20
OP467
10 5 200
RF = 5kΩ VS = ±15V
8 TA = 25°C 4
0.1%
OUTPUT STEP FOR ±15V SUPPLY (V)

OUTPUT STEP FOR ±5V SUPPLY (V)

6 3 160

INPUT BIAS CURRENT (nA)

0.1%
4 2

2 1 120

0 0

–2 –5 90

–4 –4
0.1%
–6 –3 40
0.1%

00302-038
00302-036
–8 –2

–10 –1 0
0 100 200 300 400 –75 –50 –25 0 25 50 75 100 125
SETTLING TIME (ns) TEMPERATURE (°C)

Figure 36. Output Step vs. Settling Time Figure 38. Input Bias Current vs. Temperature

25

10 VS = ±15V

TA = +125°C 20
INPUT OFFSET CURRENT (nA)
8
TA = +25°C
SUPPLY CURRENT (mA)

15

6
TA = –55°C
10

00302-039
00302-037

0
–75 –50 –25 0 25 50 75 100 125
0
0 ±5 ±10 ±15 ±20 TEMPERATURE (°C)

SUPPLY VOLTAGE (V)

Figure 37. Supply Current vs. Supply Voltage Figure 39. Input Offset Current vs. Temperature

Rev. * | Page 12 of 20
 OP467

APPLICATIONS INFORMATION
OUTPUT SHORT-CIRCUIT PERFORMANCE On the other hand, ceramic chip capacitors have excellent ESR
To achieve a wide bandwidth and high slew rate, the OP467 and effective series inductance (ESL) performance at higher
output is not short-circuit protected. Shorting the output to frequencies, and because of their small size, they can be placed
ground or to the supplies may destroy the device. very close to the device pin, further reducing the stray inductance.
Best results are achieved by using a combination of these two
For safe operation, the output load current should be limited so capacitors. A 5 μF to 10 μF tantalum parallel capacitor with a
that the junction temperature does not exceed the absolute 0.1 μF ceramic chip capacitor is recommended. If additional
maximum junction temperature. isolation from high frequency resonances of the power supply is
The maximum internal power dissipation can be calculated by needed, a ferrite bead should be placed in series with the supply
TJ max − TA lines between the bypass capacitors and the power supply. Note
PD = that addition of the ferrite bead introduces a new pole and zero
θ JA
to the frequency response of the circuit and could cause unstable
where: operation if it is not selected properly.
TJ and TA are junction and ambient temperatures, respectively. +VS

PD is device internal power dissipation. + 10µF TANTALUM

θJA is the packaged device thermal resistance given in the data sheet.
0.1µF CERAMIC CHIP
UNUSED AMPLIFIERS
It is recommended that any unused amplifiers in the quad
package be connected as a unity-gain follower with a 1 kΩ
0.1µF CERAMIC CHIP
feedback resistor with noninverting input tied to the ground plain.
10µF TANTALUM
PCB LAYOUT CONSIDERATIONS

00302-040
–VS
Satisfactory performance of a high speed op amp largely
depends on a good PCB layout. To achieve the best dynamic Figure 40. Recommended Power Supply Bypass
performance, follow the high frequency layout technique. SIGNAL CONSIDERATIONS
GROUNDING Input and output traces need special attention to assure a
A good ground plain is essential to achieve the optimum minimum stray capacitance. Input nodes are very sensitive to
performance in high speed applications. It can significantly capacitive reactance, particularly when connected to a high
reduce the undesirable effects of ground loops and IR drops by impedance circuit. Stray capacitance can inject undesirable
providing a low impedance reference point. Best results are signals from a noisy line into a high impedance input. Protect
obtained with a multilayer board design with one layer assigned high impedance input traces by providing guard traces around
to the ground plain. To maintain a continuous and low impedance them, which also improves the channel separation significantly.
ground, avoid running any traces on this layer. Additionally, any stray capacitance in parallel with the input
POWER SUPPLY CONSIDERATIONS capacitance of the op amp generates a pole in the frequency
response of the circuit. The additional phase shift caused by this
In high frequency circuits, device lead length introduces an
pole reduces the gain margin of the circuit. If this pole is within
inductance in series with the circuit. This inductance, combined
the gain range of the op amp, it causes unstable performance. To
with stray capacitance, forms a high frequency resonance circuit.
reduce these undesirable effects, use the lowest impedance
Poles generated by these circuits cause gain peaking and additional
where possible. Lowering the impedance at this node places the
phase shift, reducing the phase margin of the op amp and leading
poles at a higher frequency, far above the gain range of the
to an unstable operation.
amplifier. Stray capacitance on the PCB can be reduced by making
A practical solution to this problem is to reduce the resonance the traces narrow and as short as possible. Further reduction
frequency low enough to take advantage of the power supply can be realized by choosing a smaller pad size, increasing the
rejection of the amplifier. This is easily done by placing capacitors spacing between the traces, and using PCB material with a low
across the supply line and the ground plane as close as possible dielectric constant insulator (dielectric constant of some common
to the device pin. Because capacitors also have internal parasitic insulators: air = 1, Teflon® = 2.2, and FR4 = 4.7, with air being
components, such as stray inductance, selecting the right capacitor an ideal insulator).
is important. To be effective, they should have low impedance
Removing segments of the ground plane directly under the
over the frequency range of interest. Tantalum capacitors are an
input and output pads is recommended.
excellent choice for their high capacitance/size ratio, but their
effective series resistance (ESR) increases with frequency
making them less effective.
Rev. * | Page 13 of 20
OP467
Outputs of high speed amplifiers are very sensitive to capacitive
DLY 9.824µs
loads. A capacitive load introduces a pair of pole and zero to the
100
frequency response of the circuit, reducing the phase margin,
90
leading to unstable operation or oscillation.
Generally, it is good design practice to isolate the output of the
amplifier from any capacitive load by placing a resistor between
the output of the amplifier and the rest of the circuits. A series
resistor of 10 Ω to 100 Ω is normally sufficient to isolate the
output from a capacitive load. 10
0%
The OP467 is internally compensated to provide stable

00302-042
operation and is capable of driving large capacitive loads 5V 5V 20ns
without oscillation.
Figure 42. Saturation Recovery Time, Positive Rail
Sockets are not recommended because they increase the lead
inductance/capacitance and reduce the power dissipation of the DLY 4.806µs
package by increasing the thermal resistance of the leads. If
100
sockets must be used, use Teflon or pin sockets with the shortest 90
possible leads.
PHASE REVERSAL
The OP467 is immune to phase reversal; its inputs can exceed
the supply rails by a diode drop without any phase reversal.
10
ΔV1 15.8V
0%
100

00302-043
OUTPUT 90 5V 5V 20ns

Figure 43. Saturation Recovery Time, Negative Rail

HIGH SPEED INSTRUMENTATION AMPLIFIER

The OP467 performance lends itself to a variety of high speed
applications, including high speed precision instrumentation
10
INTPUT 0%
amplifiers. Figure 44 represents a circuit commonly used for
data acquisition, CCD imaging, and other high speed
00302-041

10V 10V 200µs applications.

Figure 41. No Phase Reversal (AV = +1) The circuit gain is set by RG. A 2 kΩ resistor sets the circuit gain
to 2; for unity gain, remove RG. For any other gain settings, use
SATURATION RECOVERY TIME the following formula
The OP467 has a fast and symmetrical recovery time from G = 2/RG (Resistor Value is in kΩ)
either rail. This feature is very useful in applications such as
high speed instrumentation and measurement circuits, where RC is used for adjusting the dc common-mode rejection, and CC
the amplifier is frequently exposed to large signals that overload is used for ac common-mode rejection adjustments.
the amplifier. –VIN
CC

2kΩ
1kΩ 2kΩ
RG 10kΩ 2kΩ
OUTPUT
1kΩ
1.9kΩ
5pF RC
10kΩ
200Ω
00302-044

10T
+VIN

Figure 44. A High Speed Instrumentation Amplifier

Rev. * | Page 14 of 20
 OP467
0.01% 10V STEP 2 MHz BIQUAD BAND-PASS FILTER
VS = ±15V
NEG SLOPE The circuit in Figure 48 is commonly used in medical imaging
ultrasound receivers. The 30 MHz bandwidth is sufficient to
accurately produce the 2 MHz center frequency, as the measured
response shows in Figure 49. When the bandwidth of the op
2.5mV
–2.5mV
amp is too close to the center frequency of the filter, the internal
phase shift of the amplifier causes excess phase shift at 2 MHz,
which alters the response of the filter. In fact, if the chosen op
amp has a bandwidth close to 2 MHz, the combined phase shift
of the three op amps causes the loop to oscillate.

00302-045
Careful consideration must be given to the layout of this circuit
Figure 45. Instrumentation Amplifier Settling Time to 0.01% for a
as with any other high speed circuit.
10 V Step Input (Negative Slope) If the phase shift introduced by the layout is large enough, it can
0.01% 10V STEP
alter the circuit performance, or worse, cause oscillation.
VS = ±15V R6
POS SLOPE 1kΩ

C1
50pF

2.5mV R2
2kΩ R4 C2
–2.5mV R1 2kΩ 50pF
3kΩ
R3
1/4 2kΩ
R5
OP467 2kΩ
2kΩ 1/4
OP467
1/4
1/4 OP467
OP467
00302-046

VOUT

00302-048
Figure 46. Instrumentation Amplifier Settling Time to 0.01% for a VIN
10 V Step Input (Positive Slope)
Figure 48. 2 MHz Biquad Filter
+VS
+
0
2kΩ +
TO
INPUT
AD9617 –10
1kΩ ERROR
TO 2kΩ TO SCOPE
GAIN (dB)

IN-AMP
OUTPUT
–20

–VS
–30
549Ω
00302-047

61.9Ω

00302-049
–40
Figure 47. Settling Time Measurement Circuit

10k 100k 1M 10M 100M

FREQUENCY (Hz)

Figure 49. Biquad Filter Response

Rev. * | Page 15 of 20
OP467
+5V
+10V
1 VDD DGND 28
+10V DAC8408
2 VREF A VREF C 27

C1 3 RFBA RFBC 26 C3
10pF 10pF
2 4 IOUT 1A IOUT 1C 25 13
OUT A 1 OP467 IOUT 2A/ IOUT 2C/ OP467 14 OUT D
3
5
IOUT 2B IOUT 2D 24 12

+15V 6 IOUT 1B IOUT 1D 23

0.1µF 7 RFBB RFBD 22

9
4 8 VREF B VREF D 21
6
C4 OP467 8 OUT C
OUT B 7 OP467 C2 +10V +10V 10pF 10
10pF 9 DB0 (LSB) DS2 20
11 5
10 DB1 DS1 19 DIGITAL
0.1µF CONTROL
–15V 11 DB2 R/W 18 SIGNALS

12 DB3 A/B 17

13 DB4 (MSB) DB7 16

00302-050
14 DB5 DB6 15

Figure 50. Quad DAC Unipolar Operation

FAST I-TO-V CONVERTER 251.0ns

The fast slew rate and fast settling time of the OP467 are well 100
suited to the fast buffers and I-to-V converters used in a variety 90
of applications. The circuit in Figure 50 is a unipolar quad DAC
consisting of only two ICs. The current output of the DAC8408
is converted to a voltage by the OP467 configured as an I-to-V
converter. This circuit is capable of settling to 0.1% within 200 ns.
Figure 51 and Figure 52 show the full-scale settling time of the
outputs. To obtain reliable circuit performance, keep the traces 10

from the IOUT of the DAC to the inverting inputs of the OP467 0%

short to minimize parasitic capacitance.

00302-052
2V 50mV 100ns

260.0ns Figure 52. Rising Edge Output Settling Time

100 DAC8408
DC OFFSET
RFB
90
3pF
2kΩ
IOUT I-V
2kΩ
OP467
1kΩ 50kΩ
AD847

604Ω
00302-053

10 60.4kΩ
0%
00302-051

Figure 53. DAC VOUT Settling Time Circuit

2V 50mV 100ns

Figure 51. Falling Edge Output Settling Time

Rev. * | Page 16 of 20
 OP467
OP467 SPICE MARCO-MODEL
* Node assignments *
noninverting input * COMMON-MODE STAGE WITH ZERO AT 1.26 kHz
inverting input *
positive supply ECM 13 98 POLY (2) (1, 20) (2,20) 0 0. 5 0 . 5
negative supply R8 13 14 1E6
output R9 14 98 25 . 119
* C3 13 14 126 . 721E–12
. SUBCKT OP467 1 2 99 50 27 *
* *POLE AT 400E6
* INPUT STAGE *
* R10 15 98 1E6
I1 4 5 10E–3 C4 15 98 0 . 398E–15
0 G2 98 15 (10,20) 1E–6
CIN 1 2 1E–12 *
IOS 1 2 5E–9 * OUTPUT STAGE
Q1 5 2 8 QN *
Q2 6 7 9 QN ISY 99 50 –8 . 183E–3
R3 99 5 185 . 681 RMP1 99 20 96 . 429E3
R4 99 6 185 . 681 RMP2 20 50 96 . 429E3
R5 8 4 180 . 508 RO1 99 26 200
R6 9 4 180 . 508 RO2 26 50 200
EOS 7 1 POLY (1) (14,20) 50E–6 1 L1 26 27 1E–7
EREF 98 0 (20,0) 1 GO1 26 99 (99,15) 5E–3
* GO2 50 26 (15,50) 5E–3
* GAIN STAGE AND DOMINANT POLE AT 1.5 kHz G4 23 50 (15,26) 5E–3
* G5 24 50 (26,15) 5E–3
R7 10 98 3 . 714E6 V3 21 26 50
C2 10 98 28 . 571E–12 V4 26 22 50
G1 98 10 (5,6) 5 . 386E–3 D3 15 21 DX
V1 99 11 1.6 D4 22 15 DX
V2 12 50 1.6 D5 99 23 DX
D1 10 11 DX D6 99 24 DX
D2 12 10 DX D7 50 23 DY
RC 10 28 1 . 4E3 D8 50 24 DY
CC 28 27 12E–12 *
* MODELS USED
*
. MODEL QN NPN (BF=33.333E3)
. MODEL DX D
. MODEL DY D (BV=50)
. ENDS OP467

Rev. * | Page 17 of 20
OP467
99 99
99 99
+
V1 –
D5 R3 R4
RMP1 D6 G01 11
ISY V3
5 6 D1 RC CC 27
+– R01 28
D3 21 2
20 10
15 L1 27 N– Q1 Q2 7
15 C3
26 IOS
R10 D4 V4 8 9
22 13 14
–+ CIN G1 R7 C2
G2 C4 R5 R6 R8
4 ECM +
RMP2 23 – R9
98 24 1
R02
EREF + N+ –+
– EOS 98
G4 D7 D8 G5 G02 + D2
EREF
– 12

00302-054
I1
V2 +

00302-055
50 50 50 – 50

Figure 54. SPICE Macro-Model Output Stage Figure 55. SPICE Macro-Model Input and Gain Stage

Rev. * | Page 18 of 20
 OP467

OUTLINE DIMENSIONS
0.775 (19.69)
0.750 (19.05)
0.735 (18.67)

14 8 0.280 (7.11)
0.250 (6.35)
1 0.240 (6.10)
7
0.325 (8.26)
0.310 (7.87)
0.100 (2.54) 0.300 (7.62)
BSC
0.060 (1.52) 0.195 (4.95)
0.210 (5.33) MAX 0.130 (3.30)
MAX 0.115 (2.92)
0.015
0.150 (3.81) (0.38) 0.015 (0.38)
0.130 (3.30) MIN GAUGE
0.110 (2.79) PLANE 0.014 (0.36)
SEATING
PLANE 0.010 (0.25)
0.022 (0.56) 0.008 (0.20)
0.005 (0.13) 0.430 (10.92)
0.018 (0.46) MIN MAX
0.014 (0.36)
0.070 (1.78)
0.050 (1.27)
0.045 (1.14)

COMPLIANT TO JEDEC STANDARDS MS-001

CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR

070606-A
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.

Figure 56. 14-Lead Plastic Dual In-Line Package [PDIP]

(N-14)
P-Suffix
Dimensions shown in inches and (millimeters)

0.005 (0.13) MIN 0.098 (2.49) MAX

14 8
0.310 (7.87)
1
0.220 (5.59)
7

PIN 1
0.100 (2.54) BSC
0.320 (8.13)
0.290 (7.37)
0.785 (19.94) MAX
0.060 (1.52)
0.200 (5.08) 0.015 (0.38)
MAX
0.150
0.200 (5.08) (3.81)
0.125 (3.18) MIN
SEATING 0.015 (0.38)
0.023 (0.58) 0.070 (1.78) PLANE 15°
0.008 (0.20)
0.014 (0.36) 0.030 (0.76) 0°

CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS

(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

Figure 57. 14-Lead Ceramic Dual In-Line Package [CERDIP]

(Q-14)
Y-Suffix
Dimensions shown in inches and (millimeters)

Rev. I | Page 19 of 20
OP467
10.50 (0.4134)
10.10 (0.3976)

16 9
7.60 (0.2992)
7.40 (0.2913)

1 10.65 (0.4193)
8
10.00 (0.3937)

1.27 (0.0500) 0.75 (0.0295)

BSC 45°
2.65 (0.1043) 0.25 (0.0098)
0.30 (0.0118) 2.35 (0.0925)
8°
0.10 (0.0039) 0°
COPLANARITY
0.10 0.51 (0.0201) SEATING 1.27 (0.0500)
PLANE 0.33 (0.0130)
0.31 (0.0122) 0.20 (0.0079) 0.40 (0.0157)

COMPLIANT TO JEDEC STANDARDS MS-013- AA

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS

032707-B
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

Figure 58. 16-Lead Standard Small Outline Package [SOIC_W]

Wide Body (RW-16)
S-Suffix
Dimensions shown in millimeters and (inches)

0.200 (5.08)
0.075 (1.91) REF
0.100 (2.54) REF
0.100 (2.54) REF
0.064 (1.63) 0.095 (2.41) 0.015 (0.38)
0.075 (1.90) MIN
19 3
18 20 4
0.028 (0.71)
0.358 (9.09) 0.358 1
(9.09) 0.011 (0.28) 0.022 (0.56)
0.342 (8.69) BOTTOM
MAX 0.007 (0.18) VIEW
SQ SQ R TYP 0.050 (1.27)
14 8 BSC
0.075 (1.91) 13 9
REF
45° TYP
0.088 (2.24) 0.055 (1.40) 0.150 (3.81)
0.054 (1.37) 0.045 (1.14) BSC

CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS

022106-A

(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR

REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 59. 20-Terminal Ceramic Leadless Chip Carrier [LCC]
(E-20-1) RC-Suffix
Dimensions shown in inches and (millimeters)

ORDERING GUIDE
Model1 Temperature Range Package Description Package Option
OP467GP −40°C to +85°C 14-Lead PDIP N-14
OP467GPZ −40°C to +85°C 14-Lead PDIP N-14
OP467GS −40°C to +85°C 16-Lead SOIC_W RW-16
OP467GS-REEL −40°C to +85°C 16-Lead SOIC_W RW-16
OP467GSZ −40°C to +85°C 16-Lead SOIC_W RW-16
OP467GSZ-REEL −40°C to +85°C 16-Lead SOIC_W RW-16
OP467ARC/883C −55°C to +125°C 20-Terminal LCC E-20-1
OP467AY/883C −55°C to +125°C 14-Lead CERDIP Q-14
OP467GBC Die
1
Z = RoHS Compliant Part.

©1993–2010 Analog Devices, Inc. All rights reserved. Trademarks and

registered trademarks are the property of their respective owners.
D00302-0-4/10(I)

Rev. I | Page 20 of 20