ASIP Architecture Implementation of Channel Equalization Algorithms For MIMO Systems in WCDMA Downlink
ASIP Architecture Implementation of Channel Equalization Algorithms For MIMO Systems in WCDMA Downlink
Abstract— This paper presents a customized and flexible hard- While computationally efficient and low power solution, ASIC
ware implementation of linear iterative channel equalization processors are not flexible enough to support the necessary
algorithms for WCDMA downlink transmission in 3G wireless variations of implemented wireless applications. On the other
system with multiple transmit and receive antennas (MIMO
system). Optimized (in terms of area and execution time) and hand, DSP processors, although fully programmable, cannot
power efficient Application Specific Instruction set Processors achieve high performance with low power dissipation in highly
(ASIPs) based on Transport Triggered Architecture (TTA) are parallel 3G applications. The drawback of DSP architecture
designed that can operate efficiently in slow and fast fading high solutions is limited level of instruction and data parallelism
scattering environments. The instruction set of TTA processors is that is necessary for future 3G/4G wireless applications. These
extended with several user-defined operations specific for channel
equalization algorithms that dramatically optimize the architec- are the reasons for the recent interest in new reconfigurable
ture solution for the physical layer of the mobile handset. The architectures with some level of programmability [3] and, at
final results of presented design-space exploration method are the same time, possibility for customization that is targeted
the ASIP processors with low cost/performance ratio. Automatic to a class of wireless applications with high levels of data
software-hardware co-design flow for conversion of C application and instruction parallelism. These architectures are called
code into gate-level hardware design of ASIP architectures is
also described. Implemented ASIP solutions achieve real time Application Specific Instruction set Processors (ASIPs) and
requirements for 3GPP wireless standard (1xEV-DV standard, in can replace multiple chip designs implemented as an ASIC
particular) with reasonable clock speed and power dissipation. architecture [4].
In this work we propose the implementation of iterative
I. I NTRODUCTION chip level channel equalization algorithms on ASIP proces-
Efficiency and flexibility are crucial features of processors sors based on Transport Triggered Architecture (TTA) [5] in
in the next generation of wireless cellular systems. Processors WCDMA MIMO downlink transmission. Channel equaliza-
need to be efficient in order to achieve real-time require- tion restores the orthogonality of the spreading waveforms
ments with low power consumption for computationally very destroyed by channel multipaths and suppresses strong Multi-
demanding algorithms in new emerging wireless standards ple Access Interference (MAI) and Inter-Symbol Interference
(3GPP, 4G, 802.11x, DVB-S2, DAB, just to name a few). (ISI). We show that the application specific processor design
Flexibility, on the other hand, allows design modifications in based on TTA is programmable and configurable enough to
order to respond to: different channel environments, changes handle different variations of channel equalization. The de-
of user requirements depending of the quality of service signed ASIP architecture operates efficiently in a broad range
(QoS), different workloads, different kinds of data, etc. Often, of channel environments defined by 3GPP standard (from two-
efficiency and flexibility goals are conflicting. paths Pedestrian A to five-paths Vehicular A channels, speed
In this work we propose both flexible and application of mobile subscriber varies from 3km/h to 120 km/h) [1].
specific (customized) hardware solutions for implementation In order to achieve real-time requirements in high data rate
of channel equalization algorithms at the physical layer of the downlink applications, parallel architectures are developed for
3G mobile handset. Processors for mobile handsets in cellular low power dissipation with the clock frequency limited to
systems that support the 3GPP standard ([1] and [2]) require approximately 150 MHz.
at the same time both high speed and low power dissipation. This paper is organized as follows. The principles of channel
In addition, computationally very demanding algorithms are equalization at the receiver side as well as the equalization-
needed to remove high levels of multiuser interference es- specific operations are introduced in section II. Customized
pecially in the presence of multiple antennas on the base- ASIP architectures for channel equalization algorithm in
station and mobile handset (MIMO wireless system). Tradi- MIMO downlink are proposed in section III. Simulation esti-
tional architecture solutions are ASIC and DSP processors. mates (clock speed, power dissipation, and area) obtained with
In this section we present two hardware architectures for CG Environment Tex [cycles] P [mW] fclk [MHz]
equalization: i) single processor for full equalization referred PedA2x2 251,305 39 76
to in Table I as ’1’, and ii) a second solution with two parallel PedB2x2 446,490 72 135
co-processors: one for channel estimation/covariance matrix VehA2x2 503,964 90 152
computation/filter update referred to as ’2a’, and the other
co-processor for filtering+despreading/descrambling referred Simulation statistics (for processing one block of 4096 data
to as ’2b’. Both solutions are evaluated with and without samples) on the single TTA processor implementation with
implementation of SFUs. The presented ASIP processors are SFUs for full CG equalization algorithm in pedestrian and
obtained by using MOVE software tools [10] (compiler and vehicular environments [11] is presented in Table II. After the
processor explorer) that have been modified in order to be able design exploration phases (described in the next section for