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    VLSI Assign

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    Srideviasokan
    This document contains 5 assignments related to VLSI design. Assignment 1 covers topics like comparing nMOS and pMOS transistors, latch-up, design rules for layouts with 2 metal layers, stick diagrams for logic gates, transistor operating modes, non-ideal effects in MOS transistors, why pMOS transistors are wider than nMOS, RC ladder delay calculations, and logical effort and parasitic delay of gates. Assignment 2 covers topics like static CMOS circuits, skewed gates, pseudo-nMOS logic, inverters, domino logic, keeper circuits, power dissipation calculations. Assignment 3 covers topics like bistability, master-slave registers, dynamic and C2MOS registers, pipelining. Assignment 4 covers

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    VLSI Assign

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    Srideviasokan
    84 views5 pages
    This document contains 5 assignments related to VLSI design. Assignment 1 covers topics like comparing nMOS and pMOS transistors, latch-up, design rules for layouts with 2 metal layers, stick diagrams for logic gates, transistor operating modes, non-ideal effects in MOS transistors, why pMOS transistors are wider than nMOS, RC ladder delay calculations, and logical effort and parasitic delay of gates. Assignment 2 covers topics like static CMOS circuits, skewed gates, pseudo-nMOS logic, inverters, domino logic, keeper circuits, power dissipation calculations. Assignment 3 covers topics like bistability, master-slave registers, dynamic and C2MOS registers, pipelining. Assignment 4 covers

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    This document contains 5 assignments related to VLSI design. Assignment 1 covers topics like comparing nMOS and pMOS transistors, latch-up, design rules for layouts with 2 metal layers, stick diagrams for logic gates, transistor operating modes, non-ideal effects in MOS transistors, why pMOS transistors are wider than nMOS, RC ladder delay calculations, and logical effort and parasitic delay of gates. Assignment 2 covers topics like static CMOS circuits, skewed gates, pseudo-nMOS logic, inverters, domino logic, keeper circuits, power dissipation calculations. Assignment 3 covers topics like bistability, master-slave registers, dynamic and C2MOS registers, pipelining. Assignment 4 covers

    Copyright:

    © All Rights Reserved
    Download as DOC, PDF, TXT or read online from Scribd
    Download as doc, pdf, or txt
    84 views5 pages

    VLSI Assign

    Uploaded by

    Srideviasokan
    This document contains 5 assignments related to VLSI design. Assignment 1 covers topics like comparing nMOS and pMOS transistors, latch-up, design rules for layouts with 2 metal layers, stick diagrams for logic gates, transistor operating modes, non-ideal effects in MOS transistors, why pMOS transistors are wider than nMOS, RC ladder delay calculations, and logical effort and parasitic delay of gates. Assignment 2 covers topics like static CMOS circuits, skewed gates, pseudo-nMOS logic, inverters, domino logic, keeper circuits, power dissipation calculations. Assignment 3 covers topics like bistability, master-slave registers, dynamic and C2MOS registers, pipelining. Assignment 4 covers

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    of 5

    SRI RAMANJAR ENGINEERING COLLEGE

    DEPARTMENT OF ECE

    EC 8095 VLSI DESIGN

    ASSIGNMENT 1 – UNIT 1

    1. Compare nMOS and pMOS transistor.


    2. What is Channel-length modulation?
    3. What is Latch – up? How it can be prevented
    4. Point out the set of design rules for layouts with two metal layers.
    5. What is stick diagram? Sketch the stick diagram for 3 input NAND and NOR.
    6. Name the different operating modes of transistor and give its condition and necessary expressions.
    7. Mention the Non ideal I-V effects of MOS transistor.
    8. Why pMOS transistors are wider than nMOS transistors.
    9. Design a RC ladder for Elmore delay with its propagation delay time, tpd.
    10. Describe the Logical effort of a gate. Analyze Parasitic delay of a gate.

    PART B

    11. Illustrate with necessary diagrams


    (i) Ideal I-V characteristics of MOS transistors,
    (ii) C-V characteristics of MOS transistors.
    12. Discuss in detail about Non ideal VI charecteristics of MOS transistor.
    13. Interpret the DC tr nsfer ch r cteristics of CMOS inverter. Design a CMOS inverter and formulate the beta
    ratio effects and noise margin.
    14. Discuss in detail about (i) RC Delay

    (ii) Elmore Delay

    (iii) Parasitic Delay

    (iv) Logic effort

    (v) Linear Delay

    15. (i)Describe in detail about Layout design rules.


    (ii) Define scaling. Explain the need of scaling, scaling principles, fundamental units of CMOS inverter

    ASSIGNMENT 2
    UNIT 2
    1. Write about static CMOS circuits. What is meant by bubble pushing?
    2. Generalize the skewed gates and calculate the logical effort for HI-skew inverter.
    3. Analyse the pseudo-nMOS logic gates.
    4. Draw the footed and unfooted Inverter, NAND2 and NOR2.
    5. Com are the static CMOS, Pseudo-nMOS and dynamic inverters
    6. Evaluate the Multiple Output Domino Logic (MODL).
    7. Design a circuit to compute F=AB+CD using NANDs and NORs.
    8. Define Keeper circuit. Discuss the Dual-rail Domino Logic.
    9. Estimate the power dissipation in CMOS circuits.
    10. Justify that CPL is an improvement of CVSL.

    PART B

    11. Describe in detail about the following.


    (i) Keepers,
    (ii) Multiple-Output Domino Logic (MODL),
    (iii) NP and Zipper Domino.
    12. Classify the types of power dissipation and manipulate each in detail
    13. Analyse the following static CMOS logic.
    (i) Bubble pushing,
    (ii) Compound gates,
    (iii) Skewed gates.
    (iv) Pseudo-nMOS
    (v) Ganged CMOS.
    14. Discuss the structure and working of CMOS transmission gates and pass transistor.
    15. Construct the various low-power reduction techniques.

    ASSIGNMENT 3

    UNIT 3
    PART A

    1. Define bistability principle.


    2. Name the approaches used to accomplish the bistable circuit.
    3. Summarize the timing properties of Mast r-slave registers.
    4. Analyse the working of dynamic positive edge-triggered register when clk=0.
    5. Describe the operation of C2MOS register. Draw the Multiplexer-based nMOS latch.
    6. What is the role of transistor sizing in TSPC Edge-Triggered Register?
    7. Mention the advant ges of pipelined operation.
    8. List out the timing parameters of the sequential circuit in synchronous design.
    9. Estimate the use of address transition detection (ATD) circuit.
    10. Develop the positive and negative clock skew scenarios.

    PART B

    11. Evaluate the Master-Slave Edge-Triggered register with its timing properties and Non-ideal clock signals.
    12. Summarize the following:
    (i) Dynamic transmission-gate edge-triggered registers,
    (ii) C2MOS-A clock-skew insensitive approach,
    (iii) True single-phase clocked register.
    13. Classify the various Pipeling techniques and explain in detail
    Summarize the following.
    (i) Latch versus Register based pipeline,
    (ii) NORA-CMOS logic style for pipelined structures.
    14. Examine the Monost ble Sequential circuits and astable circuits with neat example.
    15. Analyze the basics of synchronous timing, clock skew, clock jitter and combined impact of skew and jitter.
    Manipulate the various sources of skew and jitter.

    ASSIGNMENT 4
    UNIT 4
    PART A
    1. Obtain the critical path delay of 4 bit ripple carry adder and draw the circuit.
    2. Summarize about carry propagation delay. Mention its effect in circuits.
    3. Why is barrel Shifters very useful in the designing of arithmetic circuits?
    4. What is one time programmable memories?
    5. List the advantages and disadvantages of full adder design using static CMOS.
    6. Define Clock gating.
    7. Examine the need of VTCMOS.
    8. Classify Power o timiz tion techniques for latency and throghput constrained design.
    9. Write the charge-share equation for DRAM.
    10. Sketch a sense amplifiers CMOS circuit.

    PART B

    11. (i) Construct 4 X 4 array type multipli r and find its critical path delay.
    (ii) Implement a 4 input and 4 output barr l shift add r using NMOS logic.
    12. Design a multiplier for 5 bit by 3 bit. Explain its operation and summarize the number of transistors.
    Discuss multiplier.
    13. Explain a Modified Booth algorithm with a suitable example.
    14. Discuss detail about the DRAM sub array and open bitlines
    15. Examine the operation of :
    (i) Static CMOS adders.
    (ii) Mirror adder

    ASSIGNMENT 5
    UNIT 5
    PART A
    1. What is fault model?
    2. Point out the common techniques of ad hoc testing.
    3. List out the different approaches of Design for testability.
    4. Narrate about stuck-at faults and state their uses. Classify the types of stuck-at faults.
    5. Give a note on short circuit and open circuit faults.
    6. State the features of boundary scan method
    7. Differentiate between observability and controllability.
    8. Define Fuse based FPGA. Name the two different types of routing in FPGA.
    9. Give an example circuit for delay fault CMOS logic circuit.
    10. Illustrate the Test Access Port connection details. Outline the steps for CMOS circuit IDDQ test.

    PART B

    11. Draw and explain the building blocks of FPGA with different fusing technology.
    12. Discuss in detail about different types of scan design method and explain with neat diagram.
    13. Summarize the steps involved in design for manufacturability to increase the yield of optimized circuit.
    14. Describe the various types of ad hoc testing techniques with neat diagram.
    15. Elaborate the small finite state machine of TAP architecture

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