VALLIAMMAI ENGINEERING COLLEGE

SRM Nagar, Kattankulathur – 603 203.

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

QUESTION BANK
SUBJECT : EC6601 – VLSI Design
SEMESTER/YEAR : VI / III

UNIT I – MOS TRANSISTOR PRINCIPLE

NMOS and PMOS transistors, Process parameters for MOS and CMOS, Electrical properties of
CMOS circuits and device modelling, Scaling principles and fundamental limits, CMOS inverter
scaling, propagation delays, Stick diagram, Layout diagrams.

PART - A
Q. BT
Questions Competence
No Level
1. What is the need for demarcation line? BTL 1 Remembering
2. Compare NMOS and PMOS transistor. BTL 4 Analyzing
3. Define propagation delay of CMOS inverter. BTL 1 Remembering
4. Mention the different types of scaling technique. BTL 2 Understanding
5. Why NMOS transistor is selected as pull down transistor? BTL 3 Applying
6. Describe the lambda based design rules used for layout. BTL 2 Understanding
What is stick diagram? Sketch the stick diagram for 2 input NAND BTL 3 Applying
7.
gate.
8. Explain the hot carrier effect. BTL 4 Analyzing
9. Draw the DC transfer characteristics of CMOS inverter. BTL 3 Applying
10. Name the different operating modes of transistor? BTL 1 Remembering
11. Classify SPICE models for MOS transistor. BTL 4 Analyzing
12. What are the steps involved in IC fabrication? BTL 1 Remembering
13. Discuss the limitations of the constant voltage scaling. BTL 2 Understanding
14. Define body effect and write the threshold equation including the body BTL 1 Remembering
15. effect. a 3 input NAND gate.
Design BTL 6 Creating
16. List out second order effects of MOS transistor. BTL 1 Remembering
Determine whether an NMOS transistor with a threshold voltage of
17. BTL 5 Evaluating
0.7v is operating in the saturation region if GSV=2v and DSV=3v.
Summarize the equation for describing the channel length modulation
18. BTL 2 Understanding
effect in NMOS transistor.
Why the tunneling current is higher for NMOS transistors than PMOS
19. BTL 5 Evaluating
transistors with silica gate?
Consider the NMOS transistor in 180nm process with a nominal
20. threshold voltage of 0.4v and doping level of 8x1017cm-3. Propose the BTL 6 Creating
body voltage.

Page 2 of 12
 PART - B
1. Illustrate with necessary diagrams Electrical properties of MOS
BTL 4 Analyzing
transistor in detail. (13)
2. Describe the CMOS inverter and Derive the DC characteristics. (13) BTL 2 Understanding
3. Narrate in detail about ideal I-V characteristics and non-ideal I-V
BTL 3 Applying
characteristics of NMOS and PMOS devices. (13)
4. i) Derive the drain current of MOS device in different operating
regions. (8)
BTL 6 Creating
ii) With neat diagram formulate the n-well and channel formation in
CMOS process. (5)
5.
Mention in detail about second order effects in MOS transistor. (13) BTL 2 Understanding
6. Summarize the following:
i) CMOS process enhancements (8) BTL 2 Understanding
ii) Layout design rules. (5)
7. i) Examine the equation for threshold voltage of a MOS transistor in
terms of flat band voltage using necessary explanations and derivations.
(8) BTL 1 Remembering
ii) State the step by step derivation of threshold voltage equation of
NMOS transistor with and without body effect. (5)
8. i) An NMOS transistor has the following parameters: gate oxide
thickness=10nm, relative permittivity of gate oxide =3.9, electron
mobility=520cm2/v-sec, threshold voltage=0.7v, permittivity of free
BTL 5 Evaluating
space=8.85x10-14F/cm and W/L=8. Estimate the drain current when
VGS=2v and VDS=1.2v and also compute the gate oxide capacitance per
unit area. Note that W and L refer to the width and length of the
channel respectively. (8)
ii) Evaluate the principle of SOI technology with neat diagram and list
out its advantages and disadvantages. (5)
9. i) An NMOS transistor has a nominal threshold voltage of 0.16v.
Inspect the shift in threshold voltage caused by body effect using the
following data. The NMOS transistor is operating at a temperature of
300oK with the following parameters: gate oxide thickness tox=0.2x10-
6
cm, relative permittivity of gate oxide ε ox=3.9, relative permittivity of
silicon ε si=11.7, substrate bias voltage =2.5v, intrinsic electron
concentration Ni=1.5 x 1010 cm3, impurity concentration in substrate BTL 4 Analyzing
NA=3 x 1016 cm3. Given Boltzman’s constant =1.38x10-23J/oK, electron
charge =1.6x10-19 coulomb and permittivity of free space =8.85x10-
14
F/cm. (8)
ii) Examine a brief note on CMOS fabrication steps with necessary
diagram. (5)

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10. i) Draw the stick diagram and layout diagram using the function
Y  ( A  B  C ).D of CMOS compound gate. (8)
ii) Label the necessary stick diagram and layout for the design of NAD BTL 1 Remembering
and NOR gates. (5)
11. i) Analyze the different steps involved in n-well CMOS fabrication
process with neat diagrams. (8) BTL 4 Analyzing
ii) Explain the noise margin for a CMOS inverter. (5)
12. i) Construct the design rules for a CMOS inverter, in detail with a neat
layout. (8)
ii) Apply the mathematical equations that can be used to model the BTL 3 Applying
drain current and diffusion capacitance of MOS transistors. (5)
13. i) Express the Scaling Principles and its fundamental limits. (8)
ii) Recall the principles of constant field and lateral scaling. Write the BTL 1 Remembering
effects of the above scaling methods on device characteristics (5)
14. i) Define and derive the trans conductance of NMOS transistor. (8)
ii) Write down the equations of the small signal model of an NMOS BTL 1 Remembering
transistor. (5)
PART – C
1. With necessary illustrations explain the layout design rules and draw the
layout diagram for four input NAND and NOR gate. (15) BTL 5 Evaluating

2. Explain in detail about the need of scaling, scaling principles and effect
of scaling on MOSFET device parameters. (15) BTL 5 Evaluating
3.i. Derive an expression for Vin of a CMOS inverter to achieve the
condition Vin=Vout. What should be the relation for βn=βp. (10) BTL 6 Creating
ii. Explain the latch up conditions in CMOS circuits. (5)
4. Consider the NMOS transistor in a 180nm process with a nominal
threshold voltage of 0.4V and doping level of 8 X 1017 cm-3. The body
of the transistor is tied to ground with a substrate contact. How much BTL 6 Creating
the threshold change at room temperature if the source is at 1.1V
instead of 0V? ε si=11.7 X 8.85x10-14F/cm. (15)
UNIT II – COMBINATIONAL LOGIC CIRCUITS
Examples of Combinational Logic Design, Elmore’s constant, Pass transistor Logic,
Transmission gates, static and dynamic CMOS design, Power dissipation – Low power design
principles.
PART – A
Q. BT
Questions Competence
No Level
1. Describe path logical effort. BTL 1 Remembering
2. List the methods to reduce dynamic power dissipation. BTL 1 Remembering
3. Calculate logical effort and parasitic delay of n input NOR gate. BTL 3 Applying
4. Distinguish between static and dynamic CMOS design. BTL 2 Understanding
5. Explain pass transistor logic. BTL 4 Analyzing
6. Design an AND gate using pass transistor. BTL 6 Creating
7. Justify why the interconnect increase the circuit delay. BTL 4 Analyzing
8. Define critical path. BTL 1 Remembering

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9. What is Elmore constant? BTL 1 Remembering
10. State the advantages of transmission gates. BTL 4 Analyzing
11. Justify the reasons for the speed advantage of CVSL family. BTL 5 Evaluating
12. Implement a 2:1 MUX using pass transistor. BTL 6 Creating
13. Narrate about logical effort. BTL 1 Remembering
14. Summarize the expression for electrical effort of logic circuits. BTL 2 Understanding
15. Illustrate the method for reducing energy consumption of a logic
BTL 3 Applying
circuit.
16. Discuss the advantages of power reduction in CMOS circuits. BTL 2 Understanding
17. Point out the factors that cause static power dissipation in CMOS
BTL 2 Understanding
circuits.
18. Mention the sources of power dissipation. BTL 1 Remembering
19. Draw the pseudo NMOS logic gate. BTL 3 Applying
20. If load capacitance increases, What will happen to CMOS power
BTL 5 Evaluating
dissipation?
PART – B
1. Analyze the following combinational circuits using the CMOS logic:
i) Two input NOR gate. (3)
ii) Parity generator (3) BTL 4 Analyzing
iii) Two input NAND gate. (3)
iv) Multiplexers (4)
2. Describe in detail about
i) Delay estimation. (5)
ii) Logical effort. (4) BTL 2 Understanding
iii) Transistor sizing. (4)
3. With supporting diagrams, give notes on :
i) Static CMOS (4)
ii) Bubble pushing (4) BTL 1 Remembering
iii) Compound gates. (5)
4. i) Analyse the logical expression in the form of basic gates using CMOS
logic, F= AB + CD. (6)
ii) Estimate least delay and determine input capacitance of each stage
for the logic network shown in figure, which may output of the
network is loaded with a capacitance represent the critical path of a
BTL 4 Analyzing
more complex logic block. The output of the network is loaded with a
capacitance which is 5 times larger than the input capacitance of the
first gate, which is a minimum-sized inverter. (7) BTL 5 Evaluating

1 b c
a
5

5. i) Formulate the expression for minimum possible delay of multistage

logic networks. (6)
BTL 6 Creating
ii) Derive the Elmore constant for NAND and NOR gates. (7)

Page 5 of 12
6. Illustrate the expressions using Elmore’s RC delay:
i) Effective resistance (6) BTL 3 Applying
ii) Capacitance estimation. (7)
7. Discuss briefly the principle and operation of the following along with
its advantages.
BTL 2 Understanding
i) Pass Transistor logic (6)
ii) Complementary Pass Transistor Logic (7)
8. Write the principle of transmission gate using the design of multiplexer.
BTL 1 Remembering
(13)
9. i) Relate with Necessary Diagrams the principle of Zipper CMOS
Logic. (6) BTL 1 Remembering
ii) Implement AND/NAND gates using Dual-Rail Domino Logic. (7) BTL 3 Applying

10. i) Identify the design issues in dynamic CMOS (6)

BTL 3 Applying
ii) Recall the factors that should be considered while designing
BTL 1 Remembering
Dynamic CMOS. (7)
11. Explain the operation of the following along with necessary diagrams
i) Dynamic CMOS Domino (6) BTL 4 Analyzing
ii) NP Domino logic with necessary diagrams. (7)
12. i) Examine the characteristics of Pseudo-NMOS Circuits with the
BTL4
help of Inverter, NAND and NOR Gates. (6) Analyzing
ii) Evaluate the different methods of reducing static and dynamic
BTL 5
power dissipation in CMOS circuits and Explain in briefly. Evaluating
(7)
13. Write short notes on:
i)Ratioed Circuits (3)
ii)Dynamic CMOS Circuits (3)
BTL 1 Remembering
iii) Keepers (3)
iv) Multiple Ouput Dynamic Logic (4)
14. Examine with necessary diagrams and expressions:
i)Static power dissipation in CMOS circuits (6) BTL 2 Understanding
ii)Dynamic power dissipation in CMOS circuits (7)
PART – C
Q. BT
Questions Competence
No. Level
1. i) Implement an EXOR gate using CMOS logic. (7)
ii) Evaluate the delay of the fanout-of-4(FO4) inverter. Assume the
inverter is constructed in180nm process with τ=15ps. (8)

BTL 5 Evaluating

Page 6 of 12
2. i. Draw the static CMOS logic circuit for the following
expression
(a) Y= ( A.B.C.D) (5)
(b) Y= D(A+BC) (5) BTL 5 Evaluating
ii. Discuss in detail the characteristics of CMOS transmission
gate. (5)

3. i. Construct the CMOS logic circuit for the Boolean

expression Z= [A (B+C) +DE]’ and explain. (8) BTL 6 Creating
ii. Explain about DCVSL logic with suitable example. (7)
4. i) Write the expression for minimum possible delay of
multistage logic networks. (8)
ii) Design and estimate the frequency of n-stage ring oscillator BTL 6 Creating
and construct the ring oscillator from an odd number of
inverter. (7)

UNIT III – SEQUENTIAL LOGIC CIRCUITS

Static and Dynamic Latches and Registers, Timing issues, pipelines, clock strategies, Memory
architecture and memory control circuits, Low power memory circuits, Synchronous and
Asynchronous design.
PART – A
BT
Q. No Questions Competence
Level
1. List the advantages of differential flip flops. BTL 1 Remembering
2. Enumerate about NORA CMOS in brief? BTL 1 Remembering
3. Sketch the characteristic curve of meta stable state in static latch. BTL 3 Applying
4. Distinguish between a latches and flip flop. BTL 2 Understanding
5. Classify the sequential elements in reducing the overhead and skew. BTL 4 Analyzing
6. Define Clock Jitter. BTL 1 Remembering
7. Summarize the operation modes of NORA logic. BTL 2 Understanding
8. Determine the property of clock overlap in the registers. BTL 5 Evaluating
9. What is Klass semi dynamic flip flop? BTL 1 Remembering
10. Recall the methods of sequencing static circuit. BTL 1 Remembering
11. Write about pipelining? BTL 2 Understanding
12. Compare and Contrast Synchronous and Asynchronous Design? BTL 4 Analyzing
13. Explain simple synchronizer circuit. BTL 4 Analyzing
Formulate hold-time problem which would occur, If a data path
14. BTL 6 Creating
circuits uses pulsed latches in place of flip flops.
Justify the advantages and applications of self-time pipelined
15. BTL 5 Evaluating
circuits.
16. Design a 1-transistor DRAM cell. BTL 6 Creating
17. Illustrate the concept of clock skew in transparent latches. BTL 3 Applying
18. Give the properties of TSPC. BTL 2 Understanding
19. Why pipelining is need for of sequential circuits? BTL 1 Remembering
20. Draw the schematic of dynamic edge-triggered register. BTL 3 Applying

Page 7 of 12
 PART – B
1. Explain the sequencing methods of sequential static circuits. (13) BTL 4 Analyzing
2. Discuss in detail :
i) Synchronous pipelining in sequential circuits. (7) BTL 2 Understanding
ii) Asynchronous pipelining in sequential circuits. (6)
3. Write about the latches and flip-flops in design methodology of
BTL 1 Remembering
sequential circuit design (13)
4. i) State and explain the Klass semi dynamic flip flops and
BTL 1 Remembering
differential Flip flops. (7)
BTL 3 Applying
ii) Illustrate the enabled latches and flip flops. (6)
5. i) Design a D-latch using transmission gate. (7)
BTL 6 Creating
ii) Evaluate a 1-bit dynamic inverting and noninverting register
BTL 5 Evaluating
using pass transistor. (6)
6. i) Draw and explain the operation of conventional CMOS pulsed
BTL 3 Applying
and resettable latches. (7)
BTL 5 Evaluating
ii) Estimate about sequencing dynamic circuits. (6)
7. i) Compare the sequencing in traditional Domino and Skew tolerant
BTL 4 Analyzing
Domino circuit with neat diagrams. (7)
ii)Elucidate a floating gate transistor and its programming
BTL 3 Applying
methodology. (6)
8. Describe about the concept of timing issues and pipelining. (13) BTL 2 Understanding
9. Give a brief note on:
i) CMOS S-RAM cell and Dynamic RAM cell. (7) BTL 1 Remembering
ii) 4T and 6T SRAM cell structures (6)
10. i) Consider a flip flop built from a pair of transparent latches using
non overlapping clocks. Determine the set-up time, hold time and
clock-to-Q-delay of the flip flops in terms of the latch timing BTL 4 Analyzing
parameters and tnonoverlap. (7)
BTL 6 Creating
ii) Design a 2 input CVSL AND/NAND gate and a 3 input CVSL
OR/NOR gate. (6)
11. Write Short notes on :
i) True Single phase clocked register (7) BTL 1 Remembering
ii) NORA- CMOS pipelined latches (6)
12. Illustrate with necessary diagrams the design and organization of
BTL 2 Understanding
CAM. (13)
13. Explain in detail about:
i) Synchronizers (7) BTL 4 Analyzing
ii) Metastability. (6)
14. Demonstrate the maximum and minimum delay constraints needed
BTL 3 Applying
to design sequential circuits. (13)
PART – C
1. Discuss about the design of sequential dynamic circuits and its BTL 6 Creating
pipelining concept. (15)
2. Explain the timing basics and clock distribution techniques in BTL 5 Evaluate
synchronous design in detail. (15)
3. Elaborate about various static latches and registers. (15) BTL 6 Creating
4. Interpret the operation of Master Slave edge triggered register. (15) BTL 5 Evaluating

Page 8 of 12
 UNIT IV DESIGNING ARITHMETIC BUILDING BLOCKS

Data path circuits, Architectures for ripple carry adders, carry look ahead adders, High speed
adders, accumulators, Multipliers, dividers, Barrel shifters, speed and area trade-off.
PART – A
BT
Q. No Questions Competence
Level
1. Derive the expression for critical path of an array multiplier. BTL 6 Creating

2. Summarize the characteristics of Manchester carry chain adder. BTL 2 Understanding

3. List out the components of Datapath BTL 1 Remembering

Why is barrel Shifters very useful in the designing of arithmetic
4. BTL 2 Understanding
circuits?
Interpret a partial product selection table using modified 3-bit
5. BTL 5 Evaluating
booth’s recoding multiplication.
6. What is latency? BTL 1 Remembering
Compare constant throughput/latency and variable throughput
7. BTL 3 Applying
latency in active & leakage mode.
List the advantages and disadvantages of full adder design using
8. BTL 1 Remembering
static CMOS.
Analyze the concept of Dynamic voltage scaling and list its
9. BTL 4 Analyzing
advantages.
10. Define Clock gating. BTL 1 Remembering
Creating a schematic for Sleep transistors used on both supply
11. BTL 6 Creating
and ground.
12. Examine the need of VTCMOS BTL 4 Analyzing
13. Give the applications of high speed adder BTL 2 Understanding
14. Analyze the inverting property of full adder. BTL 4 Analyzing
15. How to design a high speed adder? BTL 3 Applying
16. Write about logical and architectural optimization? BTL 1 Remembering
Classify Power optimization techniques for latency and
17. BTL 3 Applying
throughput constrained design.
18. Write the principle of any one fast multiplier? BTL 1 Remembering
19. Sketch a Manchester carry gate. BTL 2 Understanding
20. Elaborate the Concept of Transmission gate full adder. BTL 5 Evaluating
PART – B
1. i) Describe ripple carry adder and derive the expression for
worst case delay. (10) BTL 1 Remembering
ii) Write a note on Carry Bypass adders (3)
2. Examine the concept of carry look ahead adder with neat
BTL 4 Analyzing
diagram. (13)

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3. Outline the operation of a basic 4 bit adder. Describe the
BTL 1 Remembering
different approaches of improving the speed of the adder. (13)
4. Illustrate the concepts of monolithic and logarithmic look ahead
BTL 3 Applying
adder. (13)
5. Define shifter and give a short note on
i) Barrel shifter (7) BTL 1 Remembering
ii) Logarithmic shifter. (6)
6. i) Demonstrate how to reduce the number of generated partial
products by half. (7)
BTL 3 Applying
ii) Identify and explain the concept of Dynamic Voltage Scaling.
(6)
7. Design the arithmetic logic unit (ALU) of 64 bit high end
BTL 6 Creating
microprocessor and arithmetic operators involved in design. (13)
8. Summarize the methods involved in run time power
BTL 2 Understanding
management. (13)
9. Determine the implementation of a
i)Look ahead adder in dynamic logic. (7) BTL 5 Evaluating
ii)Parallel Prefix adder (6)
10. Give a note on linear carry select adder. (13) BTL 2 Understanding
11. Examine the operation of :
i)Static CMOS adders. (7) BTL 4 Analyzing
ii)Mirror adder (6)
12. Analyze the operation of booth multiplication with suitable
examples. Justify how booth algorithm speed up the BTL 4 Analyzing
multiplication process. (13)
13. Discuss the data paths in digital processor architectures.
BTL 2 Understanding
(13)
14. Write short notes on:
i) Walllace multipliers (7)
BTL 1 Remembering
ii) Dadda multipliers (6)
PART – C
Assess the structure of ripple carry adder with a neat diagram
1. and explain its operation. How the drawback in ripple carry BTL 5 Evaluating
adder overcome by carry look ahead adder and discuss. (15)

Design a multiplier for 5 bit by 3 bit. Explain its operation and

2. summarize the number of adders. Discuss it over Wallace BTL 6 Creating
multiplier. (15)
Explain a Modified Booth algorithm with a suitable example.
3. BTL 5 Evaluating
(15)
4. Discuss the steps in designing restoring division circuit. (15) BTL 6 Creating

Page 10 of 12
 UNIT V IMPLEMENTATION STRATEGIES
Full custom and Semi-custom design, Standard cell design and cell libraries, FPGA building
block architectures, FPGA interconnect routing procedures.

PART – A
BT
Q. No Questions Competence
Level
1. 1. What is antifuse? State its merits and demerits. BTL 1 Remembering
Classify the implementation approaches for digital integrated
2. BTL 4 Analyzing
circuits.
List out the advantages and disadvantages of cell based design
3. BTL 1 Remembering
methodology.
4. Narrate about feed-through cells and state their uses. BTL 3 Remembering
5. Classify the types of Macro cells. BTL 3 Applying
6. Give a note on Tape out of chip. BTL 2 Understanding
7. State the features of full-custom design. BTL 1 Remembering
8. Compare semi-custom and full custom design. BTL 4 Analyzing
9. Describe about standard cell based ASIC design? BTL 1 Remembering
10. Define Fuse based FPGA. BTL 1 Remembering
11. Name the elements in a configuration logic Block. BTL 2 Understanding

12. Develop an array based architecture used in Altera MAX series. BTL 6 Creating
13. Design a primitive gate array cell. BTL 6 Creating
14. Explain configurable logic block. BTL 4 Analyzing
Summarize the functions of Programmable Interconnect Points
15. BTL 5 Evaluating
in FPGA.
Identify the issues in implementing Boolean functions on array
16. BTL 2 Understanding
of cells.
17. Summarize the design steps of Semicustom design flow. BTL 5 Applying
18. Illustrate Composition of generic digital processor. BTL 3 Evaluating
19. Outline the steps for ASIC design flow. BTL 2 Understand
20. Write the various ways of routing procedure BTL 1 Remembering
PART – B
1. (i) List and explain the components that makeup the cell based
design methodology. (8) BTL 1 Remembering
(ii) Give a short note on programming of PAL. (5)
2. (i)Describe the Steps involved in semicustom design flow. (7)
BTL 2 Understanding
(ii)Explain the concepts of programmable interconnect. (6)
3. (i)Describe the Blocks involved in digital processor. (8)
(ii)Define and explain the approaches of programmable wiring. BTL 1 Remembering
(5)
4. (i)Illustrate the concepts of Mask programmable arrays. (10)
(ii)Identify the components involved in constructing a voltage BTL 3 Applying
output macrocell. (3)

Page 11 of 12
 5. Explain the types of FPGA routing techniques. (13) BTL 4 Analyzing
6. Examine the interconnect architectures of
i) Altera Max series (7) BTL 4 Analyzing
ii) Xilinx XC40XX series (6)
7. (i)Identify and Explain the FPGA block structure along its
components. (7)
BTL 1 Remembering
(ii) Mention in detail the techniques involved in Switch box
programmable wiring. (6)
8. (i)Discuss the types of FPGA routing techniques. (7)
BTL 2 Understanding
(i)Demonstrate the types of ASICS. (6)
(i)9. Design an LUT-Based Logic Cell. (7)
BTL 6 Creating
(ii) Elaborate the Classification of prewired arrays. (6)
10. (i) Compare two types of macrocells. (6)
BTL 4 Analyzing
(ii) Inspect the datapaths in digital processor architectures. (7)
11. Discuss the different types of programming technology used in
BTL 2 Understanding
FPGA design. (13)
12.
Categorize the semi-custom ASIC with necessary diagrams. (13) BTL 3 Applying
13. Explain the classification of ASIC with necessary block diagram.
(i) Full Custom ASIC (7) BTL 5 Evaluating
(ii) Semi-Custom ASIC (6)
14. Write short notes on
(i) Xilinx LCA (6) BTL 1 Remembering
(ii) Altera Max (7)
PART – C

With neat sketch explain the CLB, IOB and programmable

1. BTL 5 Evaluating
interconnects of an FPGA device. (15)

Draw and explain the building blocks of FPGA with different

2. BTL 6 Creating
fusing technologies. (15)
(i) Explain about building block architecture of FPGA (10)
3. (ii) Write short notes on routing procedures involved in FPGA BTL 5 Evaluating
interconnect. (5)
Discuss in detail about different types of ASIC with neat
4. BTL 6 Creating
diagram. (15)

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