CLASS NOTES

BASIC ELECTRONICS
2nd SEMESTER

BY
SURAJ KUMAR SAMAL
ASST. PROF
&
JYOTISANKAR KALIA
ASST. PROF.
DEPT. OF ELECTRONICS & COMMUNICATION
ENGINEERING

GANDHI INSTITUTE FOR EDUCATION & TECHNOLOGY

 MODULE-I

INTRODUCTION TO ELECTRONICS:

Electronics is the branch of science and engineering dealing with the theoty and
use of a class of devices in which electrons are transported through a vacuum, gas or
semiconductor.

Signals:
It contains information about a variety of things and activities.
Example - Voice of the radio announcer, weather information
Analog Signal: The signal magnitude can be represented at any instant of time by a
sequence of numbers.

Discrete Signal: It is a sequence of numbers that represent the magnitudes of the

successive signal samples.

Digital Signal: Signal is in the form of 0 and 1.

Frequency Spectrum of Signal:

Any arbitrary signal is characterized by its frequency spectrum. The signal is
represented in frequency domain.

Fourier series: It is an expansion of periodic signal as a linear combination of sine and

cosine with different frequencies and amplitudes. It is applied to periodic signals.

Fourier transform: Fourier transform can be applied to aperiodic signals to find the
frequency spectrum.
Low Pass Filter:
· Filter that passes low frequency components of a signal but rejects the high
frequency components of a signal is called as low pass filter.
· Filters designed with passive components (Resistor, capacitor, inductor) are
called as passive filters.

Behaviour of capacitor to frequency can be described as follows

V 1
For f=0 (Low frequency) capacitive reactance of capacitor Xc= = =∞, So it
I 2pfC
acts as a open circuit
V 1
For f=∞ (High Frequency) capacitive reactance of capacitor Xc= = =0So it
I 2pfC
acts as a short circuit
Operation
For low frequency since capacitor is open circuited, current flowing in the
circuit is zero. So the output voltage vout= vin
For high frequency since capacitor is short circuited, the output voltage across a
short is zero So the output voltage vout= 0
The frequency response curve can be shown as below
 Calculation of cutoff frequency:

vout= XC v
in
R + XC
vout = XC vin
R 2 + XC 2
If R=Xc
Vout= 1 vin=0.707 vin
2
At the frequency of which R=Xc, the output will be 70.7% of the input.
1
Xc=R=
2pfC
1
Cutoff frequency fc=
2pRC
LPF as Integrator:
· Output voltage (current) is directly proportional to the integration of the input
voltage(current)
· The time constant RC of the circuit should be very large as compared to the time
period of the input wave.
· The value of R should be 10 or more times larger than Xc.

For high frequencies the capacitor has insufficient to charge up, its voltage is small. So
the voltage across the resistor is approximately equal to the input voltage.
vin=VR
VR vin
i= =
R R
The charge q on the capacitor at any instant is
q= ò idt
q ò idt 1
output voltage vout= vc=
C
=
C
=
RC
ò vindt
High Pass Filter:
· Filter that blocks low frequency components of a signal but passes the high
frequency components of a signal is called as high pass filter.
· Filters designed with passive components (resistor, capacitor, inductor) are called
as passive filters.
 Operation
For low frequency Since capacitor is open circuited, current flowing in the
circuit is zero. So the output voltage vout= VR=0
For high frequency since capacitor is short circuited, So the output voltage
vout= VR= vin
The frequency response curve can be shown as below

Calculation of cutoff frequency:

vout= R v
in
R + XC
vout = XC vin
R 2 + XC 2
If R=Xc
Vout= 1 vin=0.707 vin
2
At the frequency of which R=Xc, the output will be 70.7% of the input.
1
Xc=R=
2pfC
1
Cutoff frequency fc=
2pRC

HPF as Differentiator:
· Output voltage (current) is directly proportional to the differentiation of the input
voltage(current)
· The time constant RC of the circuit should be very small as compared to the time
period of the input wave.
· The value of R should be 10 or more times smaller than Xc.

For high frequencies the capacitor has enough time to charge up. So the voltage across
the capacitor is approximately equal to the input voltage.
vin= vc
The charge q on the capacitor at any instant is
q=C vc
dq dvC dvi
output voltage vout= iR= R=CR = CR
dt dt dt
Semiconductor:
· Conductivity lies between conductor and insulator.
· Forbidden energy gap 0.2-2.5eV.
· At 0K a pure semiconductor behaves as an insulator.
· Semiconductor materials show a reduction in resistance with increase in
temperature. So said to have a negative temperature coefficient.
Intrinsic Semiconductor:
· Semiconductor refined to reduce the number of impurities to a very low level.
e.g : Semiconductor in pure form
· Group-IV elements. Si, Ge,
Extrinsic Semiconductor:
· To increase the conductivity, impurities also called dopant (Group III or V) are
added to the pure semiconductor material and is called extrinsic Semiconductor
(n-type or p-type). The process is called doping.
· N-type Semiconductor- Pentavalent (As,Sb,P) atom is added to pure
semiconductor. Diffused impurities with five valence electrons are called donor
atoms.
· P-type Semiconductor- Trivalent (Al,B,Ga) atom is added to pure
semiconductor. Diffused impurities with three valence electrons are called
acceptor atoms.
· Holes are the majority carrier in p-type semiconductor and electrons are
minority carrier. In n-type semiconductor electrons are the majority carrier and
holes are the minority carrier.

Diode:

· Solid state device created by joining the p-type and n-type material is called as
semiconductor diode.

No Bias (V=0)

· Absence of external voltage across the p-n junction is called the unbiased diode.
Because of the density gradient electrons and holes diffuse and they combine
leaving the ions unneutralised and are called uncovered charges.
· The uncovered charges generate an electric field directed from n-side to p-side
called as barrier field which opposes the diffusion process further.
· Since the vicinity of the junction is depleted of mobile charges. Hence called a as
depletion region.
Reverse Bias (V D<0V)

· Positive polarity of the external bias V D is connected to n-type and

negative terminal is connected to p-type.
· The number of uncovered positive and negative ions will increase in the
depletion region causing widening the depletion region which creates a
great barrier for the majority carrier to overcome, effectively reducing
the majority carrier flow to zero and hence the current due to majority
carrier Imajority=0
· The minority carriers which travels down the potential barrier remain
unaffected and give a small current called the reverse saturation current
denoted as Is.

Forward Bias (V D>0V)

· Positive polarity of the external bias V D is connected to p-type and negative

terminal is connected to n-type.
· External bias V D exerts a force on the mobile carriers to move them towards the
junction. At the boundary they recombine with the ions and reduce the width of
the depletion region.
· The depletion region will continue to decrease in width as the voltage is increased
further and a heavy flood of electrons will move from n-side to p-side giving the
Imajority an exponential rise from p-side to n-side,
· The minority carrier flow will not be affected by this because the conduction level
is determined by the limited number of impurities in the material and the current is
 denoted by Is.
The total current is given by

ID =IForward+IReverse
=Imajority - Iminority (Direction opposite)

In terms of reverse saturation current, ID can be written as

eV
ID =Isexp( )-Is is called the Shockley’s equation.
hKT
Where
e- Charge of an electron
K-Blotzman’s Conatant
T-Temperature in Kelvin
η- Quality factor depends upon the diode material (η=2 for Si and 1 for Ge)
V- Supplied voltage across the junction

Breakdown Condition:
(a) Zener Breakdown
· Too much of reverse bias across a p-n junction exert a strong
force on a bound electron to tear it out from the covalent bond.
Thus a large number of electron and hole pair will be generated
through a direct rupture of the covalent bonds and they increase
the reverse current and gives sharp increase in the characteristics.
It is called zener breakdown. Diode employing the unique
portion of the characteristics of a p-n junction is called zener
diode.
· Maximum reverse voltage potential that can be applied before
entering the zener region is called the peak inverse voltage (PIV)
or peak reverse voltage (PRV).
 (b) Avalanche Breakdown:
· With increasing reverse bias voltage, the electric field across the
junction of a diode increases. At a certain value of the reverse
voltage, the electric field imparts a sufficiently high energy to a
thermally generated carrier. The carrier on colliding with an ion
on its way disrupts a covalent bond and gives a new hole electron
pair. This process is cumulative and gives an avalanche of
carriers in a very short time. It is called avalanche multiplication.

Diode equivalent Circuit:

· Equivalent circuit is a combination of element properly chosen to

best represent the actual terminal characteristics of a device or
system in a particular operating point.

Ideal diode in forward and reverse biased condition is as follows

Diode Resistance levels:
· According to the applied signal the resistance levels in a diode has
following type
1. DC or Static (DC signal)
2. AC or Dynamic(Small AC signal)
3. Average ac( Large AC signal)
CLIPPER
It controls the shape of the output waveform by removing or clipping a portion of the
applied wave. Half wave rectifier is the simplest example.It is also referred as
voltage limiters/ amplitude selectors/ slicers.
Applications:
· In radio receivers for communication circuits.
· In radars, digital computers and other electronic systems.
· Generation for different waveforms such as trapezoidal, or squarewaves.
Helps in processing the picture signals in television transmitters.
· In television receivers for separating the synchronizing signals from
composite picture signals

Types of Clipper Circuit

1. Series- Diode is in series with the source
2. Parallel- Diode is in parallel with the source.
· Clipper circuit which uses a DC battery is called a biased clipper.
SERIES CLIPPER:
Assumption- diode is ideal in characteristics
Analysis
+ve Half Cycle:
Diode is on because of forward biasing condition.
Since no voltage drop across the diode the output
voltage becomes
VO=VR=Vi
-ve Half Cycle:
Diode is off because of reverse biasing condition.
Since no current flows through the circuit the output
voltage VO=0.
Figure shows the output waveform of a simple series clipper with input as square and
triangular waveform. Since the negative half cycle is clipped off in the output it is called
as a negative clipper circuit.
Biased Series Clipper:
Assumption- diode is ideal in characteristics
Analysis
Since the diode is on because of the 5v battery
The transition of the diode from one state to
another can be found out to be atVi=-5v above
which the diode is ON and below which the
diode is OFF.
+ve Half Cycle:
Since the diode is on the output voltage will
be (Applying KVL)
Vi+5=VR
VO= Vi+5
-ve Half Cycle:
Since the diode is off VO=0.
Figure Shows the input and output waveform.

Example of Other Series Clipper Circuits:

PARALLEL CLIPPER:
Assumption- diode is ideal in characteristics
Analysis
+ve Half Cycle:
Diode is on because of forward biasing condition.
Since no voltage drop across the diode the output
voltage becomes
VO=Vd=0
-ve Half Cycle:
Diode is off because of reverse biasing condition.
Since no current flows through the circuit the output voltage VO=Vi.
Figure shows the output waveform of a simple parallel clipper with input as square and
triangular waveform. Since the positive half cycle is clipped off in the output it is called
as a positive clipper circuit.

Biased parallel Clipper:

Assumption- diode is ideal in characteristics
Analysis
The transition of the diode from one state to
another can be found out to be atVi=4v above
which the diode is OFFand below which the
diode is ON.
+ve Half Cycle:
Since the diode is OFF (above 4v) the output
voltage will be (Applying KVL)
Vi = VO
-ve Half Cycle:
Since the diode is ON (below 4v)
VO=4v.
Figure Shows the input and output waveform.
Example of Other Parallel Clipper Circuits:

CLAMPERS:

· A diode and capacitor can be combined to “clamp” an AC signal to a specific DC

level.
· It must have a capacitor, a diode and a resistive element.
· For additional shift an independent DC supply can be introduced in the circuit.
· The time constant τ=RC must be large enough to ensure that the voltage across
the capacitor does not discharge significantly during the diode is nonconducting.
Procedure to analyze a clamper circuit
1. Consider the part of the input signal that will forward bias the diode.
 2. During the On state assume that the capacitor will charge up instantaneously to a
voltage level determined by the network.
3. Assume that during the diode is in OFF sate the capacitor will hold on to its
established voltage level.
4. The polarity of Vo must be same throughout the analysis.
5. Total swing of the total output must match the swing of the input signal.

-ve clamper analysis:

-Diode is ON(Short Circuit) in the positive half cycle.
- Established voltage level on the capacitor
Vc=V
-During negative half cycle the diode is OFF and the
output voltage is
Vo=VR= -Vi-Vc = -2V
-Total swing of output is -2V which is same as the total
swing of the input.

Biased Clamper Circuit:

-ve half cycle:

Diode is ON (S.C). So applying KVL around the input
loop we have
-20+Vc=5=0
Vc=25v and Vo=5v

During +ve half cycle diode is OFF. Applying KVL

around the outside loop we have
10+25-Vo=0
Vo=35v
Summary of the Clamper Circuit:

RECTIFIERS
An important application of “regular” diodes is in rectification circuits. These
circuits are used to convert AC signals to DC in power supplies.

A block diagram of this process in a DC power supply is shown below.

Half-Wave Rectifier:

The above circuit is called as a Half-wave rectifier since it will generate a waveform
vothat will have an average value of particular use in the ac-to-dc conversion process.

During 0- (Positive Half Cycle) the diode is ON. Assuming an ideal diode with no
voltage drop across it the output voltage vo will be
vo= VR=V m

During -T(Negative Half Cycle) the diode is OFF(Open Circuit). So the current flowing
through the circuit will be 0. The output voltage vo will be

vo= VR=i x R = 0

Figure shows the input and output waveform with output

Vdc=0.318V m.
Disadvantage:
1. The ac supply delivers power only half the time.
2. Pulsating current frequency is equal to the supply frequency.

Full wave Rectifier:

The full wave rectifier utilizes both the positive and negative portions of the input
waveform. Types of full wave rectifier are

(a) Centre tapped configuration

(b) Bridge configuration

Centre tapped configuration:

· Current flows through the load resistance in the same direction during the full
cycle of the input signal.
· Centre tap transformer is used with the secondary winding.

+ve Half Cycle:

· Diode D1 is short circuited and D2 is open circuited. Current flows through the
upper half of the secondary winding.
 -ve Half Cycle:
· Diode D2 is short circuited and D1 is open circuited. Current flows through
the lower half of the secondary winding.

Complete input and output waveform can be shown as

While this full-cycle rectifier is a big improvement over the half-cycle, there
are some disadvantages.

Disadvantages:
· It is difficult to locate the centre tap on the secondary winging.
· The diodes must have high PIV.

BridgeRectifier:

The bridge rectifier uses four diodes connected in bridge pattern.

The operation ofthe bridge rectifier can be summarized as:
+ve Half Cycle:
· Diode D1 and D3 are short circuited and D2 and D4 are open circuited.
Current flows through D1 and D3 to give the output voltage across the
resistor.

-ve Half Cycle:

· Diode D1 and D3 are open circuited and D2 and D4 are short circuited.
Current flows through D2 and D4 to give the output voltage across the
resistor.

Complete input and output waveform can be shown as

Advantages:
· No centre tapped transformer is required.
· PIV is less.
Disadvantages:
· It requires four diode and the power loss in the rectifier element is more.
 MODULE-II

TRANSISTOR:

1. Bipolar Junction Transistor (BJT)

2. Field Effect Transistor (FET)
Bipolar Junction Transistor (BJT):

· pnp-- n-type semiconductor is sandwiched between two p-type semiconductor.

· npn-- p-type semiconductor is sandwiched between two n-type semiconductor.
· It has three terminal naming E-Emitter, B-Base and C-Collector.
· Both electron and hole responsible for the current conduction. So called bipolar junction
transistor.
· Doping wise-Emitter>Collector>Base
· Two Junctions- JEB (Junction emitter base) and JCB (Junction collector base).

Transistor Operation:

· JEB is forward biased by the battery VEE by which the depletion region will decrease and a
majority carrier flow will occur from emitter to base giving current Imajority or IE.
· JCB is reverse biased by the battery VCC by which the depletion region will increase and a
minority carrier flow will occur from base to collector giving current Iminority.
· When both the battery supplies are given simultaneously the holes in the base region due
to the battery VEE will act as minority carrier. They will cross the base region to reach the
collector giving the current IC.

So the current equations of BJT can be written as

IE= IC+ IB
IC= Imajority+ Iminority
IC =α IE+ ICO
Where α is defined as the fraction of the total emitter current that represents holes which
have travelled from emitter across the base to the collector and ICO is called as leakage
current.
 · Depending upon the common terminal between input and output circuit of a transistor it
may be operated in 3 modes of a BJT
(a) Common Base
(b) Common Emitter
(c) Common Collector
Common Base:

· Depending upon the biasing of the JEB and JCB, transistor has three region of operation.
JEB JCB Region of Application
operation
Forward Bias Forward Bias Saturation ON Switch

Forward Bias Reverse Bias Active Amplifier

Input Reverse Bias Reverse Bias Cutoff OFF Switch

Characterist
ics: The plot of the input current against the input voltage with the
output voltage as a parameter for a particular region of operation
(Active).

· Graph is plotted between input voltage VBE and current IE

keeping output voltage VCB as a parameter.
· The current variation with the emitter to base voltage is
similar to the forward characteristics of a p-n junction diode. However an increase in the
magnitude of the collector to base voltage causes the emitter current to increase for a
fixed VBE because of the early effect or base width modulation.

Output Characteristics: The plot of the output current against the output voltage with the input
current as a parameter.

· Graph is plotted between output voltage VCB and

output current IC keeping input current IE as a
parameter.
 · Active Region:
In this region JEB is forward biased and JCB is reverse biased. The collector current is
independent of VCB. It depends only on the emitter current IE.
IC= Imajority+ Iminority
IC =α IE+ ICBO
Where ICBO (also noted as ICO) is the leakage current called as collector to base leakage
current when emitter is open. Since this current is very small in magnitude IC≈ IE.
· Cut off Region:
Here both the junctions are reverse biased. The region below IE=0 characteristic is
called as cut off region. In this region IC= ICBO and in the range of nano amperes.
· Saturation Region:
Here both the junctions are forward biased. The region is to the left of the graph where
VCB is slightly positive and IE=0.It gives an exponential variation in the collector
current.JCB is forward biased means collector is positive with respect to base. It gives rise
to a hole current flowing from collector to base and is opposite to the original flow due to
the transistor action. Output resistance of CB is very high because a very large change in
collector voltage cases a very small change in collector current.

CB Current Amplification Factor:

It is the ratio of output collector current to the input emitter current.

IC
DC current gain adc = α≈1 (Practically 0.9 to 0.998)
IE
DIC
AC current gain aac = with VCB constant
DIE
Common Emitter:
Here emitter terminal is common between the base and the collector.
Input Characteristics:

· Graph is plotted between input voltage VBE and input

current IB keeping output voltage VCE as a parameter.
· Characteristics are similar to that of a forward biased
diode. For a constant VBE the magnitude of the base
current decreases. With increasing VCE. This is because
increasing VCE the effective base width and hence the
recombination base current decreases.

Output Characteristics:

· Graph is plotted between output voltage VCE and

output current IC keeping input current IB as a
parameter.
· Active Region:
In this region JEB is forward biased and JCB is
reverse biased. Output characteristics in the active
region are not horizontal lines because for a fixed
value of IB the magnitude of collector current
increases with VCE due to early effect.
IC =α IE+ ICBO (CB)
= α( IE+ IE)+ ICBO
IC= α/(1- α) IB + ICBO/(1- α)
IC= βIB + ICEO
Since the leakage current ICEO is very small IC ≈ βIB
· Cut off Region:
Here both the junctions are reverse biased. The region below IB=0 characteristic is
called as cut off region. In this region IC= ICEO (Collector to emitter leakage current with
base open)
· Saturation Region:
Here both the junctions are forward biased by at least the cutin voltage. The current IC
is independent of IB.

CE Current Amplification Factor:

It is the ratio of output collector current to the input baser current.
IC
DC current gain b dc = practically 50-400
IB
DIC
AC current gain b ac = with VCE constant
DIB
Relation between α and :

IC IC
IE = IC + IB a= and b =
IE IB
IC IC b a
= IC + a= b=
a b 1+ b 1-a
DC Biasing:

Biasing is the application of external dc supply to establish a fixed level of current and
voltage. Transistor operates only at a particular point of the characteristics called operating point
or Q-point/ Quiescent point.

Types of Biasing

1. Fixed Bias Configuration

2. Fixed bias with emitter resistor
3. Voltage divider bias configuration
4. Collector feedback configuration

Fixed Bias Configuration:

It is the simplest transistor DC bias configuration using npn transistor. In the DC analysis
capacitors are open circuited as shown in the figure.
Base Emitter Loop:

Applying KVL wehave

VCC-IBRB-VBE=0

VCC - VBE
I B=
RB
Since VBE and VCC are constant, the selection of a base resistor RB
sets the level of base current for the operating point.

Collector Emitter Loop:

I C= b I B

VCC-ICRC-VCE=0

VCE= VCC-ICRC

So RB controls IB and IC, and the level of RC determines the

magnitude of VCE.

VCE= VC- VE VBE= VB- VE

Fixed Bias with emitter resistor Configuration:

It contains an emitter resistor to improve the stability level over fixed bias.

Base Emitter Loop:

Applying KVL wehave

VCC-IBRB-VBE- IERE =0
 VCC - VBE
IB =
RB + ( b + 1) RE

Collector Emitter Loop:

I C= b I B

VCC-ICRC-VCE- IERE =0

VCE= VCC-IC (RC+RE)

Voltage divider bias Configuration:

In the previous bias configurations the Q-points were dependent on β which is temperature
sensitive. Voltage divide bias arrangement reduces the dependency ob β.

Exact Analysis:

The input side can be solved by Thevenin equivalent circuit.

For thevenin equivalent resistance the input dc source is short

circuited.

R1R 2
RTH=
R1 + R 2

For thevenin equivalent voltage the source VCC is returned to

the circuit and the voltage is given by
 VCCR 2
VTH=VR2=
R1 + R 2

The Thevenin equivalent circuit is redrawn and the IBQ can

be found by applying KVL

VTH-IBRTH-VBE-IERE=0

VTH - VBE
I B=
RTH + ( b + 1) RE

By solving the output collector emitter loop by KVL

VCE= VCC-IC (RC+RE)

Collector feedback configuration:

An improved level of stability can be obtained by providing a feedback path.

Base Emitter Loop:

Applying KVL and solving we have

VCC - VBE
I B=
RF + b ( RC + RE )

Collector Emitter Loop:

Applying KVL and solving we have

VCE=VCC-IC (RC+RE)
 MODULE-2
Field-Effect Transistors
INTRODUCTION

The field-effect transistor (FET) is a three-terminal device used for a variety of applications that
match, to a large extent, those of the BJT transistor. JFET transistor is a voltage-controlled
device. For the FET the current ID will be a function of the voltage VGS applied to the input
circuit. The FET is a unipolar device depending solely on either electron (n- channel) or hole ( p
-channel) conduction.
The term field effect in the name deserves some explanation. We are all familiar
with the ability of a permanent magnet to draw metal filings to itself without the need for actual
contact. The magnetic field of the permanent magnet envelopes the filings and attracts them to the
magnet along the shortest path provided by the magnetic flux lines. For the FET an electric field
is established by the charges present, which controls the conduction path of the output circuit
without the need for direct contact between the controlling and controlled quantities.

FIG. 1
voltage-controlled amplifiers.

Comparison of some of the general characteristics of BJT with FET:

One of the most important characteristics of the FET is its high input impedance.
The variation in output current is typically a great deal more for BJTs than for FETs for the same
change in the applied voltage.
FETs are more temperature stable than BJTs, and FETs are usually smaller than BJTs, making
them particularly useful in integrated-circuit (IC) chips.
The construction characteristics of some FETs, however, can make them more sensitive to
handling than BJTs.

Type of FET:
Three types of FETs : the junction field-effect transistor (JFET), the metal–oxide–
semiconductor field-effect transistor (MOSFET), and the metal– semiconductor field-effect
transistor (MESFET). The MOSFET category is further broken down into depletion and
enhancement types. The MOSFET transistor has become one of the most important devices
used in the design and construction of integrated circuits for digital computers. Its thermal
stability and other general characteristics make it extremely popular in computer circuit design.
CONSTRUCTION AND CHARACTERISTICS OF JFETs

JFET is a three-terminal device with one terminal capable of controlling the current between
the other two. The major part of the structure is the n-type material, which forms the channel
between the embedded layers of p-type material. In the absence of any applied potentials the
JFET has two p–n junctions under no-bias conditions. The result is a depletion region at each
junction, as shown in Fig. 2 that resembles the same region of a diode under no-bias conditions.

FIG. 2
Junction field-effect transistor (JFET).

VG = 0 V, VDS Some Positive Value

A positive voltage VDS is applied across the channel and the gate is connected directly to the
source to establish the condition VGS =0 V .Under the conditions the flow of charge is relatively
uninhibited and is limited solely by the resistance of the n-channel between drain and source.
The depletion region is wider near the top of both type materials. The current ID will establish
the voltage levels through the channel as indicated on the figure. The result is that the upper
region of the p-type material will be reverse-biased by about.

As the voltage VDS is increased from 0 V to a few volts, the current will increase as
determined by Ohm’s law and the plot of ID versus VDS. As VDS increases and approaches a
level referred to as VP , the depletion regions will widen, causing a noticeable reduction in the
channel width. The reduced path of conduction causes the resistance to increase. The more
horizontal the curve, the higher the resistance, suggesting that the resistance is approaching
“infinite” ohms in the horizontal region. If VDS is increased to a level where it appears that the
two depletion regions would touch” , a condition referred to as pinch-off will result.
 FIG 3 JFET at VGS = 0 V and VDS 7 0 V FIG 4 ID versus VDS for VGS = 0 V.

As VDS is increased beyond VP, the region of close encounter between the two depletion regions
increases in length long the channel, but the level of ID remains essentially the same. In essence,
therefore, once VDS 7 VP the JFET has the characteristics of a current source. As shown in Fig.
5, the current is fixed at ID = IDSS, but the voltage VDS (for levels 7 VP) is determined by the
applied load.

The choice of notation IDSS is derived from the fact that it is the drain-to-source current with a
short circuit connection from gate to source.IDSS is the maximum drain current for a JFET and is
defined by the conditions VGS =0 V and
VDS>| VP |.
VGS < 0 V
The voltage from gate to source, denoted VGS, is the controlling voltage of the JFET. Curves of
ID versus VDS for various levels of VGS can be developed for the JFET. For the n-channel
device the controlling voltage VGS is made more and more negative from its VGS= 0 V level.
The effect of the applied negative-bias VGS is to establish depletion regions similar to those
obtained with VGS 0 V, but at lower levels of VDS. Therefore, the result of applying a
negative bias to the gate is to reach the saturation level at a lower level of VDS, as shown in Fig.
6 for VGS = - 1 V. The resulting saturation level for ID has been reduced and in fact will
continue to decrease as VGS is made more and more negative. Eventually, VGS when VGS = -
VP will be sufficiently negative to establish a saturation level that is essentially 0 mA, and for all
practical purposes the device has been “turned off.” In summary:
The level of VGS that results in ID= 0 mA is defined by VGS =VP, with VP being a negative
voltage for n-channel devices and a positive voltage for p-channel JFETs.

FIG.5
FIG. 6
Application of a negative voltage to the gate of a JFET. n-

Channel JFET characteristics with IDSS = 8 mA and VP = -4 V.

TRANSFER CHARACTERISTICS
Derivation
For the BJT transistor the output I C current and the input controlling I B current are
related by beta, which was considered constant for the analysis to be performed. In equation
form
IC = f (IB) = βIB -(1)

The squared term in the equation results in a nonlinear relationship between ID and VGS,
producing a curve that grows exponentially with decreasing magnitude of VGS.
2
æ VGS ö
I D = I DSS çç 1 - ÷
è V P ÷ø -(2)

The squared term in the equation results in a nonlinear relationship between ID and VGS,
producing a curve that grows exponentially with decreasing magnitude of VGS.
The transfer characteristics defined by Shockley’s equation are unaffected by the network in
which the device is employed

FIG.7 Obtaining the transfer curve from the drain characteristics.

DEPLETION-TYPE MOSFET
MOSFETs are further broken down into depletion type and
enhancement type. The terms depletion and enhancement define
their basic mode of operation; the name MOSFET stands for
metal–oxide–semiconductor field-effect transistor

Basic Construction:
The basic construction of the n-channel depletion-type MOSFET
is provided in Fig. A slab of p-type material is formed from a
silicon base and is referred to as the substrate. It is the foundation
on which the device is constructed. In some cases the substrate is
internally connected to the source terminal. The gate is also
connected to a metal contact surface but remains insulated from
the n-channel by a very thin silicon dioxide (SiO2) layer. SiO2 is
a type of insulator referred to as a dielectric, which sets up
opposing (as indicated by the prefix di-) electric fields within the
dielectric when exposed to an externally applied field.
Basic Operation:
The gate-to-source voltage is set to 0 V by the direct connection from one terminal to the
other, and a voltage VDD is applied across the drain-to-source terminals. The result is an attraction
of the free electrons of the n-channel for the positive voltage at the drain. The result is a current
similar to that flowing in the channel of the JFET. In fact, the resulting current with VGS 0V
continues to be labeled IDSS.
VGS is set at a negative voltage such as -1 V. The negative potential at the gate will tend to pressure
electrons toward the p-type substrate (like charges repel) and attract holes from the p-type substrate
(opposite charges attract).
Depending on the magnitude of the negative bias established by VGS, a level of recombination
between electrons and holes will occur that will reduce the number of free electrons in the n-channel
available for conduction. The more negative the bias, the higher is the rate of recombination. The
resulting level of drain current is therefore reduced with increasing negative bias for VGS.

ENHANCEMENT-TYPE MOSFET
The characteristics of the enhancement-type MOSFET are quite different from depletion type
MOSFET.
Basic Construction:
A slab of p-type material is formed from a silicon
base and is again referred to as the substrate. As with
the depletion-type MOSFET, the substrate is
sometimes internally connected to the source terminal,
whereas in other cases a fourth lead (labeled SS) is
made available for external control of its potential
level. The source and drain terminals are again
connected through metallic contacts to n-doped
regions, but note in Fig. the absence of a channel
between the two n-doped regions. This is the primary
difference between the construction of depletion-type
and enhancement-type MOSFETs—the absence of a
channel as a constructed component of the device. In
summary, therefore, the construction of an
enhancement-type MOSFET is quite similar to that of
the depletion-type MOSFET, except for the absence of
a channel between the drain and source terminals.

Basic Operation:
If VGS is set at 0 V and a voltage applied between the drain and
the source of the device of Fig, the absence of an n-channel (with its generous number of free
carriers) will result in a current of effectively 0 A—quite different from the depletion-type
MOSFET and JFET, where ID = IDSS. It is not sufficient to have a large accumulation of
carriers (electrons) at the drain and the source (due to the n-doped regions) if a path fails to exist
between the two. With VDS some positive voltage, VGS at 0 V, and terminal SS directly
connected to the source, there are in fact two reverse-biased p–n junctions between the n-doped
regions and the p-substrate to oppose any significant flow between drain and source.
The level of VGS that results in the significant increase in drain
current is called the threshold voltage and is given the symbol VT. On specification sheets it is
referred to as VGS(Th), although VT is less unwieldy and will be used in the analysis to follow.
Since the channel is nonexistent with VGS 0 V and “enhanced” by the application of a
positive gate-to-source voltage, this type of MOSFET is called an enhancement-type MOSFET.
FET Biasing

For the field-effect transistor, the relationship between input and output quantities is nonlinear due
to the squared term in Shockley’s equation. Linear relationships result in straight lines when plotted
on a graph of one variable versus the other, whereas nonlinear functions result in curves as obtained
for the transfer characteristics of a JFET. The nonlinear relationship between ID and VGS can
complicate the mathematical approach to the dc analysis of FET configurations. A graphical
approach may limit solutions to tenths-place accuracy, but it is a quicker method for most FET
amplifiers. Since the graphical approach is in general the most popular, the analysis of this chapter
will have graphical solutions rather than mathematical solutions.

FIXED-BIAS CONFIGURATION:
The simplest of biasing arrangements for the n-channel JFET appears in Fig.1. Referred to as the
fixed-bias configuration,

FIG. 1
Fixed-bias configuration.

For the dc analysis, VRG = IG RG = (0 A)RG = 0 V, I G @ 0 A

The fact that the negative terminal of the battery is connected directly to the defined positive
potential of VGS clearly reveals that the polarity of VGS is directly opposite to that of VGG.
Applying Kirchhoff’s voltage law in the clockwise direction results in
- VGG - VGS = 0
VGS = - VGG
Since VGG is a fixed dc supply, the voltage VGS is fixed in magnitude, resulting in the
designation “fixed-bias configuration.”
The drain-to-source voltage of the output section can be determined by applying
Kirchhoff’s voltage law as follows:
VDS = VDD - ID RD
 = VDS + = VDS + 0 V,
V
VD =VDS,VG =VGS

SELF-BIAS CONFIGURATION

The self-bias configuration eliminates the need for

two dc supplies. The controlling gate-to-source
voltage is now determined by the voltage across a
resistor RS introduced in the source leg of the
configuration.
For the dc analysis, the capacitors can again be
replaced by “open circuits” and the resistor RG
replaced by a short-circuit equivalent since
IG = 0 A.
The current through RS is the source current IS,
but IS = ID and VRS = ID RS
VGS = - I D RS

that VGS is a function of the output current ID and not fixed in magnitude as occurred for the
fixed-bias configuration.

VOLTAGE-DIVIDER BIASING

The basic construction is exactly the same, but the dc analysis of each is quite different. IG =
0 A for FET amplifiers, but the magnitude
of IB for common-emitter BJT amplifiers
can affect the dc levels of current and
volt- age in both the input and output
circuits. Recall that IB provides the link
between input and output circuits for the
BJT voltage-divider configuration,
whereas VGS does the same for the FET
configuration.

Since IG = 0 A, Kirchhoff’s current law

requires that IR1 = IR2, and the series
equivalent circuit appearing to the left of
the figure can be used to find the level of
VG. The voltage VG, equal to the voltage
across R2, can be found using the voltage-
divider rule as follows:
R 2 V DD
VG =
R1 + R 2
Applying Kirchhoff’s voltage law

VGS = VG - IDRS
Feedback Amplifiers and Oscillators:
· Feedback implies the transfer of energy from the output of a system to its input. If a
portion or the whole of the output signal of an amplifier is fed back and superimposed on
the input signal, the performance of the amplifier changes significantly. Then the
amplifier is said to be a feedback amplifier.
· Negative/Inverse/Degenerative Feedback:- Feedback signal diminishes the magnitude of
the input signal.
· Positive/Direct/Regenerative Feedback:- Feedback signal enhances the magnitude of the
input signal.

Negative/Inverse/Degenerative Feedback

In the above circuit the input signal to the amplifier with gain A is the difference of the input
signal VS and feedback signal Vf . The feedback circuit can contain passive elements like
resistors, inductors, capacitors and active elements like transistors.

Transfer Gain of a feedback amplifier:

VO=AVi (A= VO/ Vi is the gain without feedback or open loop gain)

Vf = βVO (β= Vf/VO is known as the feedback fraction, the feedback ratio, the reverse
transfer ratio or the reverse transmission factor)
Vi=Vs- Vf (Positive sign for positive feedback)

Vs = Vi +Vf= VO/A+ βVO

Af=VO/Vs=A/(1+Aβ) is the gain with feedback called as closed loop gain.

The quantity Aβ is called as loop gain, the feedback factor, the return ratio or the loop
transmission.

The feedback introduced into an amplifier is usually expressed in decibles(dB) by the

relationship
F=dB of Feedback =20log10 =20log10

For negative feedback F is negative and for positive feedback F is positive.

Feedback amplifier topologies:

Depending up on the input mixer and output sampler configuration we have 4 feedback
topologies.
1. Voltage Series
2. Voltage Shunt
3. Current Series
4. Current Shunt

Effect of
Negative
Feedback:

A number of improvements are obtained in negative feedback

1. Better stabilised voltage gain

2. Higher input impedance and lower output impedance
3. Improved frequency response
4. Reduced noise
5. More linear operation

Positive/Direct/Regenerative Feedback:

In positive feedback input signal to the amplifier with gain A is the additione of the input signal
VS and feedback signal Vf .

VO=AVi
Vf = βVO
Vi=Vs+Vf

Vs = Vi -Vf= VO/A- βVO

Af=VO/Vs=A/(1-Aβ)

Oscillator Operation:

The use of positive feedback that results in a feedback amplifier having closed-loop gain Af
greater than 1 satisfies the phase conditions will result in operation as an oscillator.

When the switch at the amplifier input is open, no oscillation occurs. Considering fictitious
voltage Vi at the amplifier input VO=AVi. And Vf=AβVi.

If the circuits of the base amplifier and the feedback network provide Aβ of a correct
magnitude and phase, Vf can be made equal to Vi. Then, when the switch is closed and the
fictitious voltage Vi is removed, the circuit will continue operating since the feedback voltage is
sufficient to drive the amplifier, resulting in a proper input voltage to sustain the loop operation.
The output waveform will still exist after the switch is closed if the condition Aβ=1 is met. This
is known as Barkhausen criterion for oscillation.
 MODULE-3
Operational Amplifier
The Operational Amplifier is a direct-coupled , high gain , negative feedback amplifier. It is
nothing more than a differential amplifier which amplifies the difference between two inputs.

General circuit diagram of an op-amp

The terminal marked - is called the inverting terminal which means signal applied there will
appear phase inverted at the output while the terminal marked + is called the non inverting
terminal means that the signal applied here will appear in phase and applied at the output . Please
understand that the - and + do not denote any type of voltage it means that output voltage is
proportional to the difference of Non Inverting and inverting voltages which is Vo = V2 - V1 .
When there is no feedback , no voltage or capacitor between output and input the op-amp is said
to be in open loop condition .

Characteristics of an ideal op-amp

An Ideal Op-Amp has the following characteristics.
* An infinite voltage gain
* An infinite bandwidth
* An infinite input resistance: The resistance b/w V1 and V2 terminals is infinite .
* Zero output resistance: Vo remains constant no matter what resistance is applied across output .
* Perfect balance: When V1 is equal to V2 the Vo is 0 .
Single-Ended Input

Single-ended input operation results when the input signal is connected to one inputwith the
other input connected to ground.

FIG.2.Single ended input

Double-Ended Output

While the operation discussed so far had a single output, the op-amp can also be operated
with opposite outputs, as shown in Fig. 1. An input applied to either input will result in outputs
from both output terminals, these outputs always being opposite in polarity. Figure 3 shows a
single-ended input with a double-ended output. As shown, the signal applied to the plus input
results in two amplified outputs of opposite polarity. Figure 4 shows the same operation with a
single output measured.

FIG.3Double-ended output

FIG.4Double-ended output with single-ended input

Common-Mode Operation
When the same input signals are applied to both inputs, common-mode operation results, the two
inputs are equally amplified, and since they result in opposite polarity signals at the output, these
signals cancel, resulting in0-V output. Practically, a small output signal will result

FIG.5Common-modeoperation
Common-Mode Rejection

A significant feature of a differential connection is that the signals which are opposite at the
inputs are highly amplified, while those which are common to the two inputs are only slightly
amplified—the overall operation being to amplify the difference signal while rejecting the
common signal at the two inputs.
DIFFERENTIAL AND COMMONMODEOPERATION

One of the more important features of a differential circuit connection, as provided in an op-
amp, is the circuit’s ability to greatly amplify signals that are opposite at the two inputs, while
only slightly amplifying signals that are common to both inputs. An op-amp provides an output
component that is due to the amplification of the difference of the signals applied to the plus and
minus inputs and a component due to the signals common to both inputs. Since amplification of
the opposite input signals is much greater than that of the common input signals, the circuit
provides a common mode rejection as described by a numerical value called the common-mode
rejection ratio (CMRR).
Differential Inputs

When separate inputs are applied to the op-amp, the resulting difference signal is the difference
between the two inputs.

Common Inputs
When both input signals are the same, a common signal element due to the two inputscan be
defined as the average of the sum of the two signals.

Output Voltage

Since any signals applied to an op-amp in general have both in-phase and out-of phase
components, the resulting output can be expressed as

Where Vd = difference voltage given by Eq.

Vc = common voltage given by Eq.
Ad =differential gain of the amplifier
Ac = common-mode gain of the amplifier

Common-Mode Rejection Ratio

Having obtained Ad and Ac (as in the measurement procedure discussed above), wecan now
calculate a value for the common-mode rejection ratio (CMRR), which isdefined by the
following equation:
The value of CMRR can also be expressed in logarithmic terms as

We can express the output voltage in terms of the value of CMRR as follows:

Basic of Op-Amp

The circuit shown provides operation as a constant-gain multiplier. An input signal, V1, is
applied through resistor R1 to the minus input. The output is then connected back to the same
minus input through resistor Rf. The plus input is connected to ground. Since the signal V1 is
essentially applied to the minus input, the resulting output is opposite in phase to the input signal.
Figure 6a shows the op-amp replaced by its ac equivalent
circuit. If we use the ideal op-amp equivalent circuit, replacing Ri by an infinite resistance and
Ro by zero resistance, the ac equivalent circuit is that shown in Fig.6b. The circuit is then
redrawn, as shown in Fig. 6c, from which circuit analysis is carried out.
FIG.6.Operation of op-amp as constant-gain multiplier: (a) op-amp ac
equivalent circuit; (b) ideal op-amp equivalent circuit; (c) redrawn equivalent circuit.
PRACTICAL OP-AMP CIRCUITS

Inverting Amplifier
The most widely used constant-gain amplifier circuit is the
inverting amplifier, as shown. The output is obtained by
multiplying the input by a fixed or constant gain, set by the
input resistor (R1) and feedback resistor (Rf)—this output
also being inverted from the input. Using Eq. (14.8) we can
write

Noninverting Amplifier
The connection of Fig. 8shows an op-amp circuit that works as a noninverting amplifier or
constant-gain multiplier. It should be noted that the inverting amplifier connection is more
widely used because it has better frequency stability (discussed later). To determine the voltage
gain of the circuit, we can use the equivalent representation shown in Fig. 14.16b. Note that the
voltage across R1 is V1 since Vi =0 V. This must be equal to the output voltage, through a
voltage divider of R1 and Rf, so that

FIG.8.Noninverting constant-gain multiplier

Summing amplifier

The circuit shows a three-input summing amplifier circuit, which provides a means of
algebraically summing (adding) three voltages, each multiplied by a constant-gain factor. Using
the equivalent representation shown in Fig. 9, the output voltage can be expressed in terms of the
inputs as

In other words, each input adds a voltage to the output multiplied by its separate constant-gain
multiplier. If more inputs are used, they each add an additional component to the output.

FIG.9Summing amplifier; (b) virtual-ground equivalent circuit.

Subtractor:

FIG.10 Substractor
The aim of the subtractor is to provide an output which is equal to the difference of the two input
signals or proportional to their difference. For minimum offset error R1 || R2 = R3 || R4 .

Op-Amp as Integrator

The operational amplifier integrator is an electronic integration circuit. Based around the
operational amplifier (op-amp), it performs the mathematical operation of integration with
respect to time; that is, its output voltage is proportional to the input voltage integrated over time.

The input current is offset by a negative feedback current flowing in the capacitor, which is
generated by an increase in output voltage of the amplifier. The output voltage is therefore
dependent on the value of input current it has to offset and the inverse of the value of the
feedback capacitor. The greater the capacitor value, the less output voltage has to be generated to
produce a particular feedback current flow.

Ideal circuit

The circuit operates by passing a current that charges or discharges the capacitor Cf during
the time under consideration, which strives to retain the virtual ground condition at the input by
off-setting the effect of the input current. Referring to the above diagram, if the op-amp is
assumed to be ideal, nodes v1 and v2 are held equal, and so v2 is a virtual ground. The input
voltage passes a current vin/R1.through the resistor producing a compensating current flow
through the series capacitor to maintain the virtual ground. This charges or discharges the
capacitor over time. Because the resistor and capacitor are connected to a virtual ground, the
input current does not vary with capacitor charge and a linear integration of output is achieved.

The circuit can be analyzed by applying Kirchhoff's current law at the node v2, keeping ideal op-
amp behavior in mind.
 in an ideal op-amp, so:

Furthermore, the capacitor has a voltage-current relationship governed by the

equation:

Substituting the appropriate variables:

in an ideal op-amp, resulting in:

Integrating both sides with respect to time:

If the initial value of vo is assumed to be 0 V, this results in a DC error of:

The Op-amp Differentiator Amplifier

The basic Op-amp Differentiator circuit is the exact opposite to that of the Integrator Amplifier
circuit that we looked at in the previous tutorial. Here, the position of the capacitor and resistor
have been reversed and now the reactance, Xc is connected to the input terminal of the inverting
amplifier while the resistor, Rƒ forms the negative feedback element across the operational
amplifier as normal.
This Operational Amplifier circuit performs the mathematical operation of Differentiation that
is it “produces a voltage output which is directly proportional to the input voltage’s rate-of-
change with respect to time“. In other words the faster or larger the change to the input voltage
signal, the greater the input current, the greater will be the output voltage change in response,
becoming more of a “spike” in shape.

As with the integrator circuit, we have a resistor and capacitor forming an RC Network across
the operational amplifier and the reactance ( Xc ) of the capacitor plays a major role in the
performance of a Op-amp Differentiator.

Op-amp Differentiator Circuit

The input signal to the differentiator is applied to the capacitor. The capacitor blocks any DC
content so there is no current flow to the amplifier summing point, X resulting in zero output
voltage. The capacitor only allows AC type input voltage changes to pass through and whose
frequency is dependent on the rate of change of the input signal.

At low frequencies the reactance of the capacitor is “High” resulting in a low gain ( Rƒ/Xc ) and
low output voltage from the op-amp. At higher frequencies the reactance of the capacitor is much
lower resulting in a higher gain and higher output voltage from the differentiator amplifier.

However, at high frequencies an op-amp differentiator circuit becomes unstable and will start to
oscillate. This is due mainly to the first-order effect, which determines the frequency response of
the op-amp circuit causing a second-order response which, at high frequencies gives an output
voltage far higher than what would be expected. To avoid this high frequency gain of the circuit
needs to be reduced by adding an additional small value capacitor across the feedback resistor
Rƒ.
The charge on the capacitor equals Capacitance x Voltage across the capacitor

The rate of change of this charge is

but dQ/dt is the capacitor current i

from which we have an ideal voltage output for the op-amp differentiator is given as:

Therefore, the output voltage Vout is a constant -Rƒ.C times the derivative of the input voltage
Vin with respect to time. The minus sign indicates a 180o phase shift because the input signal is
connected to the inverting input terminal of the operational amplifier.
 Module-I4
One’s Complement: Complement all the bits .i.e. makes all 1s as 0s and all 0s as 1s

Two’s Complement: One’s complement+1

SIGNED BINARY NUMBERS

Positive integers (including zero) can be represented as unsigned numbers. However, to
represent negative integers, we need a notation for negative values. There are three different
format to represent a negative (signed) number. For example:
Three different ways to represent -9 with eight bits:
Signed magnitude representation: 10001001
signed‐1’s‐complement representation: 11110110
signed‐2’s‐complement representation: 11110111

Two’s Complement as -ve Number

Two’s complement is -ve number because binary addition of a n-bit number with it’s
complement gives n bit result with all bits = 0s

Highest Two’s Complement format +ve Number: A highest positive arithmetic number
is when at msb there is 0 and all remaining bits are 1s
Lowest Two’s Complement format -ve Number : A lowest negative arithmetic number
is when at msb there is 1 and all remaining bits are 0s
Therefore for 8-bits
• Maximum 8-bit number = 0111 1111( +127)
• Minimum 8-bit number = 1000 0000 ( −128)
Subtraction using ′ and ′ complements
Example: Calculate the following binary Subtraction: 11101.101 – 1011.11,
then verify the result in decimal System.

Important Note:

When using the complement methods in subtraction and having no additional 1 in the
extreme left cell, then, this means a negative result.

In this case, the solution is the negative of 1’s complement of the result (if using 1’s
complement initially), or the negative of 2’s complement of the result (if using 2’s
complement initially).

It is shown in the following examples, where the results are –ve.

BINARY CODES
In the coding, when numbers, letters or words are represented by a specific group of symbols,
it is said that the number, letter or word is being encoded. The group of symbols is called as a
code. The digital data is represented, stored and transmitted as group of binary bits. This
group is also called as binary code. The binary code is represented by the number as well as
alphanumeric letter.

Binary-Coded Decimal Code

Binary Coded Decimal (BCD) as the name implies is a way of representing Decimal
numbers in a 4 bit binary code. BCD numbers are useful when sending data to display
devices for example. The numbers 0 through 9 are the only valid BCD values. Notice in the
table that the binary and BCD values are the same for the numbers 0 to 9. When we exceed
the value of 9 in BCD each digit in the BCD number is now represented by a 4 bit binary
value.

In this code each decimal dig it is represented by a 4-bit binary number. BCD is a way to
express each of the decimal digits with a binary code. In the BCD, with four bits we can
represent sixteen numbers (0000 to 1111). But in BCD code only first ten of these are used
(0000 to 1001). The remaining six code combinations i.e. 1010 to 1111 are invalid in BCD.

BCD Addition

Consider the addition of two decimal digits in BCD, together with a possible carry from a
previous less significant pair of digits. Since each digit does not exceed 9, the sum cannot be
greater than 9 + 9 + 1 = 19, with the 1 being a previous carry. Suppose we add the BCD digits
as if they were binary numbers. Then the binary sum will produce a result in the range from 0
to 19. In binary, this range will be from 0000 to 10011, but in BCD, it is from 0000 to 1
1001, with the first (i.e., leftmost) 1 being a carry and the next four bits being the BCD sum.
When the binary sum is equal to or less than 1001 (without a carry), the corresponding BCD
digit is correct. However, when the binary sum is greater than or equal to 1010, the result is
an invalid BCD digit. The addition of 6 = (0110)2 to the binary sum converts it to the correct
digit and also produces a carry as required. This is because a carry in the most significant bit
position of the binary sum and a decimal carry differ by 16 - 10 = 6. Consider the
following three BCD additions:

In each case, the two BCD digits are added as if they were two binary numbers. If the binary
sum is greater than or equal to 1010, we add 0110 to obtain the correct BCD sum and a carry.
In the first example, the sum is equal to 9 and is the correct BCD sum. In the second example,
the binary sum produces an invalid BCD digit. The addition of 0110 produces the correct
BCD sum, 0010 (i.e., the number 2), and a carry. In the third example, the binary sum
produces a carry. This condition occurs when the sum is greater than or equal to 16. Although
the other four bits are less than 1001, the binary sum requires a correction because of the
carry. Adding 0110, we obtain the required BCD sum 0111 (i.e., the number 7) and a BCD
carry.
The addition of two n‐digit unsigned BCD numbers follows the same procedure.
Consider the addition of 184 + 576 = 760 in BCD:

The first, least significant pair of BCD digits produces a BCD digit sum of 0000 and a carry
for the next pair of digits. The second pair of BCD digits plus a previous carry produces a
digit sum of 0110 and a carry for the next pair of digits. The third pair of digits plus a carry
produces a binary sum of 0111 and does not require a correction.
Advantages of BCD Codes: It is very similar to decimal system. We need to remember binary
equivalent of decimal numbers 0 to 9 only.

Disadvantages of BCD Codes: The addition and subtraction of BCD have different rules. The
BCD arithmetic is little more complicated. BCD needs more number of bits than binary to
represent the decimal number. So BCD is less efficient than binary.
Gray Codes
It is the non-weighted code and it is not arithmetic codes. That means there are no specific weights
assigned to the bit position. It has a very special feature that has only one bit will chang e, eachtime
the decimal number is incremented as shown in the table . As only one bit chang es at a time, the g ray
code is called as a unit distance code. The g ray code is a cyclic code. Gray code cannot be used for
arithmetic operation

Decimal BCD Code Gray Code

0 0000 0000
1 0001 0001
2 0010 0011
3 0011 0010
4 0100 0110
5 0101 0111
6 0110 0101
7 0111 0100
8 1000 1100
9 1001 1101

Binary to Gray Conversion:

Follow the below Steps to convert Binary number to gray code.
Lets Consider the Binary number B1 B2 B3 B4 ... Bn and the Gray code is G1 G2 G3 G4 ... Gn

1. Most significant bit (B1) is same as the most significant bit in Gray Code (B1 = G1)
2. To find next bit perform Ex-OR (Exclusive OR) between the Current binary bit and
previous bit.
Gn = Bn (Ex-OR) Bn-1
3. Look the below Image for Binary to Gray code Conversion

Gary to Binary Conversion

Follow the below steps to convert Gray Code to Binary

1. Most significant bit (G1) is same as the most significant bit in Binary Code (G1 = B1)
2. The next number can be obtain by taking Exclusive OR operation between the
previous binary bit, and the current gray code bit and write down the value.
 Repeat the Above Step until you find Bn
Look at the below example for Converting Binary to Gray Code.

Application of Gray code: Gray code is popularly used in the shaft position encoders. A shaft
position encoder produces a code word which represents the angular position of the shaft.

Excess-3 code
The Excess-3 code is also called as XS-3 code. It is non-weighted code used to express decimal
numbers. The Excess-3 code words are derived from the 8421 BCD code words adding (0011)2 or
(3)10 to each code word in8421. The excess-3 codes are obtained as follows

Decimal Number BCD Code Exess-3 Code

Decimal BCD Code Excess-3(BCD+0011)

0 0000 0011
1 0001 0100
2 0010 0101
3 0011 0110
4 0100 0111
5 0101 1000
6 0110 1001
7 0111 1010
8 1000 1011
9 1001 1100
ASCII Code

(American Standard Code for Information Interchange)

ASCII code is a 7-bit code whereas. ASCII code is more commonly used worldwide. This
standard binary code for the alphanumeric characters is the American Standard Code for
Information Interchange (ASCII), which uses seven bits to code 128 characters, as shown in
Table given below. The seven bits of the code are designated by b1 through b7, with b7 the
most significant bit. The letter A, for example, is represented in ASCII as 1000001 (column
100, row 0001). The ASCII code also contains 94 graphic characters that can be printed and
34 nonprinting characters used for various control functions.

The graphic characters consist of the 26 uppercase letters (A through Z), the 26 lowercase
letters (a through z), the 10 numerals (0 through 9), and 32 special printable characters,
such as %, *, and $.

The 34 control characters are designated in the following ASCII table with abbreviated
names
BOOLEAN FUNCTIONS
Boolean algebra is an algebra that deals with binary variables and logic operations. A
Boolean function described by an algebraic expression consists of binary variables, the
constants 0 and 1, and the logic operation symbols. For a given value of the binary variables,
the function can be equal to either 1 or 0. As an example, consider the Boolean function

F1 = x +  z
A Boolean function can be transformed from an algebraic expression into a circuit diagram
composed of logic gates connected in a particular structure. The logic‐circuit diagram (also
called a schematic) for F1 is shown in Figure using different logic gates.

CANONICAL AND STANDARD FORMS

Minterms and Maxterms

A binary variable may appear either in its normal form (x) or in its complement form ( ′ )
Now consider two binary variables x and y combined with an AND operation. Since each
variable may appear in either form, there are four possible combinations: ′  ′ , ′ , ′ and
xy. Each of these four AND terms is called a minterm, or a standard product. In a similar
manner, n variables can be combined to form 2n minterms. The 2n different minterms may be
determined by a method similar to the one shown in Table given below for three variables.
Each minterm is obtained from an AND term of the n variables, with each variable being
primed if the corresponding bit of the binary number is a 0 and unprimed if a 1. A symbol for
each minterm is also shown in the table and is of the form mj, where the subscript j denotes
the decimal equivalent of the binary number of the minterm designated.
In a similar fashion, n variables forming an OR term, with each variable being primed or
unprimed, provide 2n possible combinations, called maxterms, or standard sums. The eight
maxterms for three variables, together with their symbolic designations, are listed in Table
2.3 . Any 2n maxterms for n variables may be determined similarly. It is important to note
that (1) each maxterm is obtained from an OR term of the n variables, with each variable
being unprimed if the corresponding bit is a 0 and primed if a 1, and (2) each maxterm is the
complement of its corresponding minterm and vice versa.
A Boolean function can be expressed algebraically from a given truth table by forming
a minterm for each combination of the variables that produces a 1 in the function
and then taking the OR of all those terms. For example, the function f1 in Table 2.4 is
determined by expressing the combinations 001, 100, and 111 as x_y_z, xy_z_, and xyz,
respectively. Since each one of these minterms results in f1 = 1, we have
f1 =  ′  ′  +  ′  ′ +  = m1 + m4 + m7 =
(1,4,7)

Minterms and Maxterms for Three Binary Variables

Standard Forms
Another way to express Boolean functions is in standard form.
-SOP (sum of products)
-POS (product of sums)
The sum of products is a Boolean expression containing AND terms, called product terms,
with one or more literals each. The sum denotes the ORing of these terms. An example of a
function expressed as a sum of products is
F1 =   + xy +   y 
The expression has three product terms, with one, two, and three literals. Their sum is, in
effect, an OR operation. The logic diagram of a sum‐of‐products expression consists of a
group of AND gates followed by a single OR gate. This configuration pattern is shown in
Fig. 2.3 (a). Each product term requires an AND gate, except for a term with a single literal.
The logic sum is formed with an OR gate whose inputs are the outputs of the AND gates and
the single literal. It is assumed that the input variables are directly available in their
complements, so inverters are not included in the diagram. This circuit configuration is
referred to as a two-level implementation.
A product of sums is a Boolean expression containing OR terms, called sum terms. Each term
may have any number of literals. The product denotes the ANDing of these terms. An
example of a function expressed as a product of sums is

F2 = x (  + z) (  +y+  )

This expression has three sum terms, with one, two, and three literals. The product is an AND
operation. The use of the words product and sum stems from the similarity of the AND
operation to the arithmetic product (multiplication) and the similarity of the OR operation to
the arithmetic sum (addition). The gate structure of the product‐of‐sums expression consists
of a group of OR gates for the sum terms (except for a single literal), followed by an AND
gate. This standard type of expression results in a two-level structure of gates.
Gate-Level Minimization
Gate-level minimization is the design task of finding an optimal gate-level implementation of
the Boolean functions describing a digital circuit. The map method presented here provides a
simple, straightforward procedure for minimizing Boolean functions. This method may be
regarded as a pictorial form of a truth table. The map method is also known as the Karnaugh
map or K-map. A K-map is a diagram made up of squares, with each square representing one
minterm of the function that is to be minimized.

Two-Variable K-Map
There are four minterms for two variables; hence, the map consists of four squares, one
for each minterm.. The 0 and 1 marked in each row and column designate the values of
variables. Variable x appears primed in row 0 and unprimed in row 1. Similarly, y appears
primed in column 0 and unprimed in column 1. If we mark the squares whose minterms
belong to a given function, the two-variable map becomes another useful way to represent
any one of the 16 Boolean functions of two variables. As an example, the function xy is
shown in Figure (a). Since xy is equal to m3, a 1 is placed inside the square that belongs to
m3. Similarly, the function x + y is represented in the map of Figure (b) by three squares
marked with 1’s. These squares are found from the minterms of the function:

The three squares could also have been determined from the intersection of variable x in the
second row and variable y in the second column, which encloses the area belonging to x or y .
In each example, the minterms at which the function is asserted are marked with a 1.
Three-Variable K-Map

Example: Simplify the Boolean function

F (x,y,z) =
(2,3,4,5)

The simplified function is: F (x,y,z) = x’y+yx’

Example
For the Boolean function
F =  C +  B +   C + BC

(a) Express this function as a sum of minterms.

(b) Find the minimal sum-of-products expression.

Note that F is a sum of products. Three product terms in the expression have two literals and
are represented in a three-variable map by two squares each. The two squares corresponding
to the first term,  C, are found in Fig-a from the coincidence of  (first row) and C (two
middle columns) to give squares 001 and 011. Note that, in marking 1’s in the squares, it is
possible to find a 1 already placed there from a preceding term.
This happens with the second term,  B, which has 1’s in squares 011 and 010. Square 011 is
common with the first term,  C, though, so only one 1 is marked in it. Continuing in this
fashion, we determine that the term AB’C belongs in square 101, corresponding to minterm 5,
and the term BC has two 1’s in squares 011 and 111. The function has a total of five
minterms, as indicated by the five 1’s in the map of Figure . The minterms are read directly
from the map to be 1, 2, 3, 5, and 7. The function can be expressed in sum-of-minterms form
as F (x,y,z)=
(1,2,3,5,7)
The sum-of-products expression, as originally given, has too many terms. It can be
simplified, as shown in the map, to an expression with only two terms:

Fig-a
The simplified function is: F = C +  B
FOUR-VARIABLE K-MAP
Here for four variables we have 16 minterms. So a map of 16 squares is required.
Lets say 4 variables are w,x,y,z

Example
Simplify the Boolean function: F (x,y,z)=
(0,1,2,4,5,6, ,9,12,13,14)

Eight adjacent squares marked with 1’s can be combined to form the one literal term   . The
remaining three 1’s on the right cannot be combined to give a simplified term; they must be
combined as two or four adjacent squares. The larger the number of squares combined, the
smaller is the number of literals in the term. In this example, the top two 1’s on the right are
combined with the top two 1’s on the left to give the term     . Note that it is permissible to
use the same square more than once. We are now left with a square marked by 1 in the third
row and fourth column (square 1110). Instead of taking this square alone (which will give a
term with four literals), we combine it with squares already used to form an area of four
adjacent squares. These squares make up the two middle rows and the two end columns,
giving the term x  .

The simplified function is: F =  + w’  +x 

Example
Simplify the Boolean function: F = A’B’C’+ B’CD’ + A’BCD’ + AB’C’

The simplified function is: F = B’D’ + A’CD’ + B’C’

Five-Variable Map
A five-variable map needs 32 squares and a six-variable map needs 64 squares. It can be
explained in the class.

PRODUCT-OF-SUMS SIMPLIFICATION
By using K-map the simplified function is in SOP format.
So if we want to get Final answer in POS format, we need to simplified for the F’ and at the
end take complement of F’ to get F in POS form. It can be easily explained in the following
example

Example
Simplify the following Boolean function into (a) sum-of-products form and (b) product-of-
sums form:

F (A,B,C,D)=
(0,1, 2, 5, 8, 9,10)
The 1’s marked in the map of Figure represent all the minterms of the function. The squares
marked with 0’s represent the minterms not included in F and therefore denote the
complement of F. Combining the squares with 1’s gives the simplified function in sum-of-
products form:
(a) F =     +     + A’  D
If the squares marked with 0’s are combined, as shown in the diagram, we obtain the
simplified complemented function:
F_ = AB + CD + B 
Applying DeMorgan’s theorem, we obtain the simplified function in productof-sums form:

(b) F = ( +   ) (  +   ) (  + D)

The gate-level implementation of the simplified expressions obtained in Example 3.7 is

shown in Fig. 3.13 . The sum-of-products expression is implemented in (a) with a group of
AND gates, one for each AND term. The outputs of the AND gates are connected to the
inputs of a single OR gate. The same function is implemented in (b) in its product-of-sums

F (A, B, C, D) =
(, , , , , , )=     +     +    D =
( +   )(  +   )(  + D)

DON’T-CARE CONDITIONS

The logical sum of the minterms associated with a Boolean function specifies the
conditions under which the function is equal to 1. The function is equal to 0 for the rest of the
minterms. In practice, in some applications the function is not specified for certain
combinations of the variables. As an example, the four-bit binary code for the decimal digits
has six combinations that are not used and consequently are considered to be unspecified.
Functions that have unspecified outputs for some input combinations are called incompletely
specified functions . these unspecified minterms are don’t-care conditions and can be used on
a map to provide further simplification of the Boolean expression.
A don’t-care minterm is a combination of variables whose logical value is not specified. To
distinguish the don’t-care condition from 1’s and 0’s, an X is used. Thus, an X inside a square
in the map indicates that we don’t care whether the value of 0 or 1 is assigned to F for the
particular minterm.
In choosing adjacent squares to simplify the function in a map, the don’t-care minterms may
be assumed to be either 0 or 1. When simplifying the function, we can choose to include each
don’t-care minterm with either the 1’s or the 0’s, depending on which combination gives the
simplest expression.

Example
Simplify the Boolean function: F (w,x,y,z)=
(1,3,7,11,15)
which has the don’t-care conditions: d (w,x,y,z)=
(0, 2, 5)

The minterms of F are the variable combinations that make the function equal to 1. The
minterms of d are the don’t-care minterms that may be assigned either 0 or 1(marked by X’s)
and the remaining squares are filled with 0’s. To get the simplified expression in sum-of-
products form, we must include all five 1’s in the map, but we may or may not include any of
the X’s, depending on the way the function is simplified. The term yz covers the four
minterms in the third column. The remaining minterm, m1, can be combined

with minterm m3 to give the three-literal term w’x’z. However, by including one or two
adjacent X’s we can combine four adjacent squares to give a two-literal term. In Figure (a),
don’t-care minterms 0 and 2 are included with the 1’s, resulting in the simplified function
F = yz + w’x’
In Figure (b), don’t-care minterm 5 is included with the 1’s, and the simplified function is
now F = yz + w’z
Either one of the preceding two expressions satisfies the conditions stated for this example.

More examples will be done in the Class.

NAND AND NOR IMPLEMENTATION
Digital circuits are frequently constructed with NAND or NOR gates rather than with AND
and OR gates. NAND and NOR gates are easier to fabricate with electronic components and
are the basic gates used in all IC digital logic families. Rules and procedures have been
developed for the conversion from Boolean functions given in terms of AND, OR, and NOT
into equivalent NAND and NOR logic diagrams.

NAND Circuits
The NAND gate is said to be a universal gate because any logic circuit can be implemented
with it. To show that any Boolean function can be implemented with NAND gates, we need
only show that the logical operations of AND, OR, and complement can be obtained with
NAND gates alone. This is indeed shown in Figure.

A convenient way to implement a Boolean function with NAND gates is to obtain the
simplified Boolean function in terms of Boolean operators and then convert the function
to NAND logic. The conversion of an algebraic expression from AND, OR, and complement
to NAND can be done by simple circuit manipulation techniques that change AND–OR
diagrams to NAND diagrams.
Two equivalent graphic symbols for the NAND gate are shown in Figure . The AND-invert
symbol has been defined previously and consists

The general procedure for converting a multilevel AND–OR diagram into an all-NAND
diagram using mixed notation is as follows:
1. Convert all AND gates to NAND gates with AND-invert graphic symbols.
2. Convert all OR gates to NAND gates with invert-OR graphic symbols.
3. Check all the bubbles in the diagram. For every bubble that is not compensated by another
small circle along the same line, insert an inverter (a one-input NAND gate) or complement
the input literal.

Two-Level Implementation
Example: The implementation of Boolean functions with NAND gates requires that the
functions be in sum-of-products form.
F = AB + CD
The function is implemented in Figure(a) with AND and OR gates.
In Figure(b), the AND gates are replaced by NAND gates and the OR gate is replaced by a
NAND gate with an OR-invert graphic symbol. Remember that a bubble denotes
complementation and two bubbles along the same line represent double complementation, so
both can be removed. Removing the bubbles on the gates of (b) produces the circuit of (a).
Multilevel NAND Circuits

Implement : F = A (CD + B) + B 
NOR Implementation

Two equivalent graphic symbols for the NOR gate are shown in Figure .

NOR implementation of a function expressed as a product of sums. Then the OR-AND pattern can be
easily converted to NOR gates.For example:

F = (A + B)(C + D)E

Ex.The Boolean function for this circuit is:F = (AB_ + A_B)(C + D_)

THER TWO-LEVEL IMPLEMENTATIONS

The eight nondegenerate forms are as follows:

AND–OR OR–AND
NAND–NAND NOR–NOR
NOR–OR NAND–AND
OR–NAND AND–NOR

AND–OR–INVERT Implementation

The two forms, NAND–AND and AND–NOR, are equivalent and can be treated together.
Both perform the AND–OR–INVERT function, as shown in Figure given below . The AND–
NOR form resembles the AND–OR form, but with an inversion done by the bubble in the
output of the NOR gate. It implements the function
F = (AB + CD + E)_
By using the alternative graphic symbol for the NOR gate, we obtain the diagram of Figure
(b). Note that the single variable E is not complemented, because the only
change made is in the graphic symbol of the NOR gate. Now we move the bubble from
the input terminal of the second-level gate to the output terminals of the first-level gates.
An inverter is needed for the single variable in order to compensate for the bubble.
Alternatively, the inverter can be removed, provided that input E is complemented. The
circuit of Fig. 3.27 (c) is a NAND–AND form and was shown in Fig. 3.26 to implement
the AND–OR–INVERT function.
An AND–OR implementation requires an expression in sum-of-products form. The
AND–OR–INVERT implementation is similar, except for the inversion. Therefore, if the
complement of the function is simplified into sum-of-products form (by combining the 0’s
in the map), it will be possible to implement F_ with the AND–OR part of the function.
When F_ passes through the always present output inversion (the INVERT part), it will

OR–AND–INVERT Implementation
The OR–NAND and NOR–OR forms perform the OR–AND–INVERT function, as shown in
Fig. 3.28 . The OR–NAND form resembles the OR–AND form, except for the inversion done
by the bubble in the NAND gate. It implements the function
F = 3(A + B)(C + D)! 
By using the alternative graphic symbol for the NAND gate, we obtain the diagram of Figure
(b). The circuit in Figure(c) is obtained by moving the small circles from the inputs of the
second-level gate to the outputs of the first-level gates. The circuit of Fig. (c) is a NOR–OR
form and was shown in Fig. 3.26 to implement the OR–AND–INVERT function.
The OR–AND–INVERT implementation requires an expression in product-of-sums form. If
the complement of the function is simplified into that form, we can implement "  with the
OR–AND part of the function. When F_ passes through the INVERT part, we obtain the
complement of "  ,or F , in the output.
EXCLUSIVE-OR FUNCTION

The exclusive-OR (XOR), denoted by the symbol⊕, is a logical operation that performs the
following Boolean operation:
x ⊕y = xy  + x  y
The exclusive-OR is equal to 1 if only x is equal to 1 or if only y is equal to 1 (i.e., x and y
differ in value), but not when both are equal to 1 or when both are equal to 0. The exclusive-
NOR, also known as equivalence performs the following Boolean operation:
(⊕) = xy + x  y 
The exclusive-NOR is equal to 1 if both x and y are equal to 1 or if both are equal to 0.
The exclusive-NOR can be shown to be the complement of the exclusive-OR by means
of a truth table or by algebraic manipulation:
(⊕) = (xy  +x  y ) = (x  + y)(x + y  ) = xy + x  y 
The following identities apply to the exclusive-OR operation:
x⊕0=x
x ⊕ 1 = x
x⊕x = 0
x⊕x  = 1
x ⊕ y  = x  ⊕ y =(⊕)
Any of these identities can be proven with a truth table or by replacing the ⊕ operation
by its equivalent Boolean expression. Also, it can be shown that the exclusive-OR operation
is both commutative and associative; that is,
A⊕B=B⊕A
and
(A ⊕ B) ⊕ C = A⊕ (B ⊕ C) = A⊕B ⊕ C
This means that the two inputs to an exclusive-OR gate can be interchanged without affecting
the operation. It also means that we can evaluate a three-variable exclusive-OR operation in
any order, and for this reason, three or more variables can be expressed without parentheses.
This would imply the possibility of using exclusive-OR gates with three or more inputs.
However, multiple-input exclusive-OR gates are difficult to fabricate with hardware. In fact,
even a two-input function is usually constructed with other types of gates. A two-input
exclusive-OR function is constructed with conventional gates using two inverters, two AND
gates, and an OR gate, as shown in Fig (a). Figure (b) shows the implementation of the
exclusive-OR with four NAND gates. The first NAND gate performs the operation(xy) =
(x  + y  ). The other two-level NAND circuit
produces the sum of products of its inputs:
(x  + y  ) + (x  + y  ) = xy  + x  y = x ⊕ y

Odd Function
The exclusive-OR operation with three or more variables can be converted into an ordinary
Boolean function by replacing the ⊕ symbol with its equivalent Boolean expression. In
particular, the three-variable case can be converted to a Boolean expression
as follows:
A⊕ B ⊕ C = (A  +  B)  + (AB +    )C
= A    +  B  + ABC +   C
=
(1, 2, 4, 7)
The Boolean expression clearly indicates that the three-variable exclusive-OR function is
equal to 1 if only one variable is equal to 1 or if all three variables are equal to 1. Contrary to
the two-variable case, in which only one variable must be equal to 1, in the case of three or
more variables the requirement is that an odd number of variables be equal to 1. As a
consequence, the multiple-variable exclusive-OR operation is defined as an odd function.

Parity Generation and Checking

Exclusive-OR functions are very useful in systems requiring error detection and correction
codes. A parity bit is used for the purpose of detecting errors during the transmission of inary
information. A parity bit is an extra bit included with a binary message to make the number
of 1’s either odd or even. The message, including the parity bit, is transmitted and then
checked at the receiving end for errors. An error is detected if the checked parity does not
correspond with the one transmitted. The circuit that generates the parity bit in the transmitter
is called a parity generator. The circuit that checks the parity in the receiver is called a parity
checker.
As an example, consider a three-bit message to be transmitted together with an even-parity
bit. Table shows the truth table for the parity generator. The three bits x, y, and z constitute
the message and are the inputs to the circuit. The parity bit P is the output. For even parity,
the bit P must be generated to make the total number of 1’s (including P ) even. From the
truth table, we see that P constitutes an

odd function because it is equal to 1 for those minterms whose numerical values have
an odd number of 1’s. Therefore, P can be expressed as a three-variable exclusive-OR
function:
P=x⊕y⊕z
The logic diagram for the parity generator can be drawn using XOR gates. The three bits in
the message, together with the parity bit, are transmitted to their destination, where they are
applied to a parity-checker circuit to check for possible errors in the transmission. Since the
information was transmitted with even parity, the four bits received must have an even
number of 1’s. An error occurs during the transmission if the four bits received have an odd
number of 1’s, indicating that one bit has changed in value during transmission. The output of
the parity checker, denoted by C , will be equal to 1 if an error occurs—that is, if the four bits
received have an odd number of 1’s. The truth table for the even-parity checker is given
below. From it, we see that the function C consists of the eight minterms with binary
numerical values having an odd number of 1’s. The table corresponds to the map of Fig.(a),
which

represents an odd function. The parity checker can be implemented with exclusive-OR gates:
C=x⊕y⊕z⊕P
The logic diagram of the parity checker can be drawn using XOR gates. It is obvious from the
foregoing example that parity generation and checking circuits always have an output
function that includes half of the minterms whose numerical values have either an odd or
even number of 1’s. As a consequence, they can be implemented with exclusive-OR gates. A
function with an even number of 1’s is the complement of an odd function. It is implemented
with exclusive-OR gates, except that the gate associated with the output must be an
exclusive-NOR to provide the required complementation.