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    22LVS14

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    22LVS14

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    kumarrprasanna57
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    22LVS14 (1) (1)

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    16 views2 pages

    22LVS14

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    kumarrprasanna57

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    USN 22LVS14

    First Semester M.Tech. Degree Examination, June/July 2023


    Digital VLSI Design

    Time: 3 hrs. Max. Marks: 100


    Note: 1. Answer any FIVE full questions, choosing ONE full question from each module.
    2. M : Marks , L: Bloom’s level , C: Course outcomes.

    Module – 1 M L C
    Q.1 a. Explain the behavior of MOS system under external bias with energy band 10 L2 CO1
    diagram and relevant equations.
    b. Derive IDS for cut-off, linear and saturation region using gradual channel 10 L3 CO1
    approximation method.
    OR
    Q.2 a. Explain resistive load inverter circuit and derive the equation for VOH and 10 L2 CO1
    VOL of the circuit.
    b. What is scaling in MOSFET? Explain Full Scaling and derive the equation 10 L2 CO1
    for drain current and power density after scaling.
    Module – 2
    Q.3 a. Explain CMOS inverter with reference to operating regions of nMOS and 10 L2 CO2
    pMOS transistors. Also derive the expression for inverter threshold voltage
    VTH .
    b. Explain propagation delay times with reference to input-output voltage 10 L2 CO2
    waveform of a typical inverter. Derive the expression for the propagation
    delay time for high to low output transition (PHL) .
    OR
    Q.4 a. Explain the switching power dissipation of CMOS inverter. Also derive the 10 L2 CO2
    expression for average switching power dissipation over one period.
    b. Draw a general RC tree network consisting of several branches and derive 10 L3 CO2
    the expression (DN) for very large ‘N’ using Elmore Delay Model.
    Module – 3
    Q.5 a. Explain Full CMOS SRAM cell with read and write operation. 10 L2 CO3
    b. With the help of neat diagram explain the various configuration of DRAM 10 L3 CO3
    cell.
    OR
    Q.6 a. Discuss the operation of Three Transistor DRAM cell and draw the typical 12 L3 CO3
    voltage wave forms during four consecutive operations of write “1” , read
    “1”, write “0” and read “0”.
    b. Write short notes on semiconductor memories. 08 L2 CO3
    Module – 4
    Q.7 a. Explain basic principle of pass transistor circuit in logic “1” transfer and 12 L2 CO4
    logic “0” transfer with relevant equations and diagrams.
    b. Explain the three stages of a depletion load nMOS dynamic shift register 08 L2 CO4
    circuit driven by two phase clocking.
    OR
    Q.8 a. Discuss NORA CMOS logic with necessary diagrams. 10 L2 CO4
    b. Explain dynamic CMOS logic and illustrate the cascading problem in 10 L2 CO4
    dynamic CMOS logic.

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    22LVS14

    Module – 5
    Q.9 a. Explain the static behavior of basic BiCMOS circuit. 10 L2 CO5
    b. Discuss the BJT Inverter delay times with necessary circuit diagram. 10 L2 CO5

    OR
    Q.10 a. Analyze the npn BJT operating in a forward active mode and reverse active 10 L4 CO5
    mode using Eber Moll equivalent circuit diagram.
    b. Explain BiCMOS NOR2 and BiCMOS NAND2 gate with relevant 10 L2 CO5
    diagram.

    *****

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