Computing Ds 8Gb DDR4 (A-Ver) Based UDIMMs (Rev.1.3) PDF

288pin DDR4 SDRAM Unbuffered DIMM
DDR4 SDRAM Unbuffered DIMM

Based on 8Gb A-die
HMA851U6AFR6N
HMA81GU6AFR8N
HMA81GU7AFR8N
HMA82GU6AFR8N
HMA82GU7AFR8N
*SK hynix reserves the right to change products or specifications without notice.
Rev. 1.3 / Jun.2017 1

Revision History
Revision No. History Draft Date Remark
0.1 Initial Release Dec.2015
0.2 Updated 2133Mbps (tCK(min) : 0.938ns->0.937ns) Mar.2016

Updated JEDEC Specification
1.0 Added Development plan (ECC 1Rx8/2Rx8) Apr.2016

Updated IDD Specification
1.1 Updated IPP Specification (1Rx8/2Rx8) Apr.2016
1.2 Updated IDD Specification (2133Mbps) Jun.2016
1.3 Corrected Block Diagram / Module Dimension Jun.2017
Rev. 1.3 / Jun.2017 2

Description
SK hynix Unbuffered DDR4 SDRAM DIMMs (Unbuffered Double Data Rate Synchronous DRAM Dual In-Line
Memory Modules) are low power, high-speed operation memory modules that use DDR4 SDRAM devices.
These Unbuffered SDRAM DIMMs are intended for use as main memory when installed in systems such as
PCs and workstations.
Features
• Power Supply: VDD=1.2V (1.14V to 1.26V)

• VDDQ = 1.2V (1.14V to 1.26V)
• VPP - 2.5V (2.375V to 2.75V)
• VDDSPD=2.25V to 3.6V
• Functionality and operations comply with the DDR4 SDRAM datasheet
• 16 internal banks
• Bank Grouping is applied, and CAS to CAS latency (tCCD_L, tCCD_S) for the banks in the same or dif-
ferent bank group accesses are available
• Data transfer rates: PC4-2400, PC4-2133, PC4-1866, PC4-1600
• Bi-Directional Differential Data Strobe
• 8 bit pre-fetch
• Burst Length (BL) switch on-the-fly BL8 or BC4(Burst Chop)
• Supports ECC error correction and detection
• On-Die Termination (ODT)
• Temperature sensor with integrated SPD
• This product is in compliance with the RoHS directive.
• Per DRAM Addressability is supported
• Internal Vref DQ level generation is available
Ordering Information
# of
Part Number Density Organization Component Composition
ranks
HMA851U6AFR6N-TF/UH 4GB 512Mx64 512Mx16(H5AN8G6NAFR)*4 1
HMA81GU6AFR8N-TF/UH 8GB 1Gx64 1Gx8(H5AN8G8NAFR)*8 1
Rev. 1.3 / Jun.2017 3

Key Parameters
CAS
tCK tRCD tRP tRAS tRC
MT/s Grade Latency CL-tRCD-tRP
(ns) (ns) (ns) (ns) (ns)
(tCK)
13.75 13.75 48.75
DDR4-1600 -PB 1.25 11 35 11-11-11
(13.50)* (13.50)* (48.50)*
13.92 13.92 47.92
DDR4-1866 -RD 1.071 13 34 13-13-13
(13.50)* (13.50)* (47.50)*
14.06 14.06 47.06
DDR4-2133 -TF 0.937 15 33 15-15-15
(13.50)* (13.50)* (46.50)*
14.16 14.16 46.16
DDR4-2400 -UH 0.833 17 32 17-17-17
(13.75)* (13.75)* (45.75)*
*SK hynix DRAM devices support optional downbinning to CL15, CL13 and CL11. SPD setting is programmed to match.
Address Table
4GB(1Rx16) 8GB(1Rx8) 16GB(2Rx8)
# of Bank Groups 2 4 4
Bank Address BG Address BG0 BG0~BG1 BG0~BG1
Bank Address in a BG BA0~BA1 BA0~BA1 BA0~BA1
Row Address A0~A15 A0~A15 A0~A15
Column Address A0~ A9 A0~ A9 A0~ A9
Page size 2KB 1 KB 1 KB
Rev. 1.3 / Jun.2017 4

Pin Descriptions
Pin Name Description Pin Name Description
A0-A171 SDRAM address bus SCL I2C serial bus clock for SPD-TSE
BA0, BA1 SDRAM bank select SDA I2C serial bus line for SPD-TSE
BG0, BG1 SDRAM bank group select SA0-SA2 I2C slave address select for SPD-TSE
RAS_n2 SDRAM row address strobe PARITY SDRAM parity input
CAS_n3 SDRAM column address strobe VDD SDRAM I/OO and core power supply
WE_n4 SDRAM write enable C0, C1, C2 Chip ID lines

Optional power Supply on socket but
CS0_n, CS1_n, DIMM Rank Select Lines 12V
not used on UDIMM
SDRAM command/address reference
CKE0, CEK1 SDRAM clock enable lines input VREFCA
supply
SDRAM on-die termination control lines
ODT0, ODT1 VSS Power supply return (ground)
input
ACT_n SDRAM activate VDDSPD Serial SPD-TSE positive power supply
DQ0-DQ63 DIMM memory data bus ALERT_n SDRAM ALERT_n output
CB0-CB7 DIMM ECC check bits VPP SDRAM Supply
Dummy loads for mixed populations of
TDQS0_t-TDQS8_t
x4 based and x8 based RDIMMs.
TDQS0_c-TDQS8_c
Not used on UDIMMs.
SDRAM data strobes
DQS0_t-DQS8_t
(positive line of differential pair)
SDRAM data strobes
DQS0_c-DQS8_c RESET_n Set DRAMs to a Known State
(negative line of differential pair)
DM0_n-DM8_n, SDRAM data masks/data bus inersion SPD signals a thermal event has
EVENT_n
DBI0_n-DBI8_n (x8-based x72 DIMMs) occurred
SDRAM clock (positive line of differen-
CK0_t, CK1_t VTT SDRAM I/O termination supply
tial pair)
SDRAM clock (positive line of differen-
CK0_c, CK1_c RFU Reserved for future use
tial pair)
1. Address A17 is not valid for x8 and x16 based SDRAMs. For UDIMMs, this connection pin is NC.
2. RAS_n is a multiplexed function with A16.
3. CAS_n is a multiplexed function with A15.
4. WE_n is a multiplexed function with A14.
Rev. 1.3 / Jun.2017 5

Input/Output Functional Descriptions
Symbol Type Function
CK0_t, CK0_c, Clock: CK_t and CK_c are differential clock inputs. All address and control input signals
Input
CK1_t, CK1_c are sampled on the crossing of the positive edge of CK_t and negative edge of CK_c.
Clock Enable: CKE HIGH activates and CKE LOW deactivates internal clock signals and
device input buffers and output drivers. Taking CKE LOW provides Precharge Power-
Down and Self-Refresh operation (all banks idle), or Active Power-Down (row Active in
any bank). CKE is aynchronous for Self-Refresh exit. After VREFCA and Internal DQ Vref
CKE0, CKE1 Input have become stable during the power on and initialization sequence, they must be
maintained during all operations (including Self-Refresh). CKE must be maintained high
throughout read and write accesses. Input buffers, excluding CK_t, CK_c, ODT and CKE,
are disabled during power-down. Input buffers, excluding CKE, are disabled during Self-
Refresh.
Chip Select: All commands are masked when CS_n is registered HIGH. CS_n provides for
CS0_n, CS1_n, external Rank selection on systems with multiple Ranks. CS_n is considered part of the
Input
CS2_n, CS3_n command code.
CS2_n and CS_3_n are not used on UDIMMs.
Chip ID: Chip ID is only used for 3DS for 2,4,8 high stack via TSV to select each slice of
C0, C1, C2 Input stacked component. Chip ID is considered part of the command code.
Not used on UDIMMs.
On-Die Termination: ODT (registered HIGH) enables RTT_NOM termination resistance
internal to the DDR4 SDRAM. When enabled, ODT is only applied to each DQ, DQS_t,
DQS_c and DM_n/DBI_n/TDQS_t,NU/TDQS_c (When TDQS is enabled via Mode
ODT0, ODT1 Input
Register A11=1 in MR1) signal for x8 configurations. For x16 configuration, ODT is
applied to each DQ, DQSU_t, DQSU_c, DQSL_t, DQSL_c, DMU_n, and DML_n signal.
The ODT pin will be ignored if MR1 is programmed to disable RTT_NOM.
Activation Command Input: ACT_n defines the Activation command being entered along
ACT_n Input with CS_n. The input into RAS_n/A16, CAS_n/A15 and WE_n/A14 will be considered as
Row Address A16, A15 and A14.
Command Inputs: RAS_n/A16, CAS_n/A15 and WE_n/A14 (along with CS_n) define the
RAS_n/A16, command being entered. Those pins have multi function. For example, for activation
CAS_n/A15, Input with ACT_n Low, these are Addresses like A16, A15, and A14. But for non-activation
WE_n/A14 command with ACT_n High, these are Command pins for Read, Write, and other
commands defined in command truth table.
Input Data Mask and Data Bus Inversion: DM_n is an input mask signal for write data.
Input data is masked when DM_n is sampled LOW coincident with that input data during
a Write access. DM_n is sampled on both edges of DQS. DM is muxed with DBI function
DM_n/DBI_n/
by Mode Register A10, A11, A12 setting in MR5. For x8 device, the function of DM or
TDQS_t, Input/
TDQS is enabled by Mode Register A11 setting in MR1. DBI_n is an input/output
(DMU_n/DBIU_n), Output
identifying whether to store/output the true or inverted data. If DBI_n is LOW, the data
(DML_n/DBIL_n)
will be stored/output after inversion inside the DDR4 SDRAM and not inverted if DBI_n is
HIGH. TDQS is only supported in x8 SDRAM configurations.
TDQS is not valid for UDIMMs.
Rev. 1.3 / Jun.2017 6

Bank Group Inputs: BG0 - BG1 define which bank group an Active, Read, Write, or
Precharge command is being applied. BG0 also determines which mode register is to be
BG0, BG1 Input
accessed during a MRS cycle. x4/x8 SDRAM configurations have BG0 and BG1. x16
based SDRAMs only have BG0.
Bank Address Inputs: BA0 - BA1 define to which bank an Active, Read, Write or
BA0, BA1 Input Precharge command is being applied. Bank address also determines which mode
register is to be accessed during a MRS cycle.
Address Inputs: Provide the row address for ACTIVATE Commands and the column
address for Read/Write commands to select one location out of the memory array in the
respective bank. A10/AP, A12/BC_n, RAS_n/A16, CAS_n/A15 and WE_n/A14 have
A0 - A17 Input
additional functions. See other rows. The address inputs also provide the op-code during
Mode Register Set commands.
A17 is only defined for the x4 SDRAM configuration.
Auto-precharge: A10 is sampled during Read/Write commands to determine whether
Autoprecharge should be performed to the accessed bank after the Read/Write
operation. (HIGH: Autoprecharge; LOW: no Autoprecharge). A10 is sampled during a
A10 / AP Input
Precharge command to determine whether the Precharge applies to one bank (A10
LOW) or all banks (A10 HIGH). If only one bank is to be precharged, the bank is selected
by bank addresses.
Burst Chop: A12/BC_n is sampled during Read and Write commands to determine if
A12 / BC_n Input burst chop (on-the-fly) will be performed. (HIGH, no burst chop; LOW: burst chopped).
See command truth table for details.
CMOS Active Low Asynchronous Reset: Reset is active when RESET_n is LOW, and inactive
RESET_n
Input when RESET_n is HIGH. RESET_n must be HIGH during normal operation.
Data Input/ Output: Bi-directional data bus. If CRC is enabled via Mode register then
Input / CRC code is added at the end of Data Burst. Any DQ from DQ0-DQ3 may indicate the
DQ
Output internal Vref level during test via Mode Register Setting MR4 A4=High. Refer to vendor
specific data sheets to determine which DQ is used.
Data Strobe: output with read data, input with write data. Edge-aligned with read data,
centered in write data. For the x16, DQSL corresponds to the data on DQL0-DQL7;
DQS_t, DQS_c,
Input / DQSU corresponds to the data on DQU0-DQU7. The data strobe DQS_t, DQSL_t and
DQSU_t, DQSU_c,
Output DQSU_t are paired with differential signals DQS_c, DQSL_c, and DQSU_c, respectively,
DQSL_t, DQSL_c
to provide differential pair signaling to the system during reads and writes. DDR4
SDRAM supports differential data strobe only and does not support single-ended.
TDQS_t, TDQS_c Output Termination Data Strobe: TDQS_t/TDQS_c are not valid for UDIMMs.
Command and Address Parity Input : DDR4 Supports Even Parity check in DRAMs with
MR setting. Once it’s enabled via Register in MR5, then DRAM calculates Parity with
PARITY Input ACT_n, RAS_n/A16, CAS_n/A15, WE_n/A14, BG0-BG1, BA0-BA1, A16-A0. Input parity
should be maintained at the rising edge of the clock and at the same time with
command & address with CS_n LOW.
Rev. 1.3 / Jun.2017 7

Alert: It has multiple functions, such as CRC error flag, Command and Address Parity
error flag, as an Output signal. If there is an error in CRC, then ALERT_n goes LOW for
the period time interval and goes back HIGH. If there is an error in Command Address
ALERT_n Output Parity Check, then ALERT_n goes LOW for a relatively long period until on going DRAM
internal recovery transaction is complete. During Connectivity Test mode, this pin
functions as an input.
Using this signal or not is dependent on the system.
RFU Reserved for Future Use. No on DIMM electrical connection is present.
NC No Connect: No on DIMM electrical connection is present.
VDD1 Supply Power Supply: 1.2 V +/- 0.06 V
VSS Supply Ground
VPP Supply DRAM Activating Power Supply: 2.5V (2.375V min , 2.75V max)
VTT2 Supply Power Supply for termination of Address, Command and Control, VDD/2.
12V Supply 12V supply not used on UDIMMs.
VDDSDP Supply Power supply used to power the I2C bus on the SPD-TSE
VREFCA Supply Reference voltage for CA
Note:
1. For PC4 VDD 1.2V. For PC4L VDD is TBD.
2. For PC4 VTT is 0.60V. For PC4L VTT is TBD.
Rev. 1.3 / Jun.2017 8

Pin Assignments
Front Side Back Side Front Side Back Side
Pin Pin Pin Pin
Pin Label Pin Label Pin Label Pin Label
1 NC 145 NC 74 CK0_t 218 CK1_t
2 VSS 146 VREFCA 75 CK0_c 219 CK1_c
3 DQ4 147 VSS 76 VDD 220 VDD
4 VSS 148 DQ5 77 VTT 221 VTT
5 DQ0 149 VSS
KEY
6 VSS 150 DQ1
7 DM0_n, DBI0_n, NC 151 VSS 78 EVENT_n 222 PARITY
8 NC 152 DQS0_c 79 A0 223 VDD
9 VSS 153 DQS0_t 80 VDD 224 BA1
10 DQ6 154 VSS 81 BA0 225 A10/AP
11 VSS 155 DQ7 82 RAS_n/A16 226 VDD
12 DQ2 156 VSS 83 VDD 227 RFU
13 VSS 157 DQ3 84 CS0_n 228 WE_n/A14
14 DQ12 158 VSS 85 VDD 229 VDD
15 VSS 159 DQ13 86 CAS_n/A15 230 NC
16 DQ8 160 VSS 87 ODT0 231 VDD
17 VSS 161 DQ9 88 VDD 232 A13
18 DM1_n, DBI1_n, NC 162 VSS 89 CS1_n 233 VDD
19 NC 163 DQS1_c 90 VDD 234 NC
20 VSS 164 DQS1_t 91 ODT1 235 NC
21 DQ14 165 VSS 92 VDD 236 VDD
22 VSS 166 DQ15 93 NC 237 NC
23 DQ10 167 VSS 94 VSS 238 SA2
24 VSS 168 DQ11 95 DQ36 239 VSS
25 DQ20 169 VSS 96 VSS 240 DQ37
26 VSS 170 DQ21 97 DQ32 241 VSS
27 DQ16 171 VSS 98 VSS 242 DQ33
28 VSS 172 DQ17 99 DM4_n, DBI4_n, NC 243 VSS
29 DM2_n, DBI2_n, NC 173 VSS 100 NC 244 DQS4_c
30 NC 174 DQS2_c 101 VSS 245 DQS4_t
31 VSS 175 DQS2_t 102 DQ38 246 VSS
32 DQ22 176 VSS 103 VSS 247 DQ39
33 VSS 177 DQ23 104 DQ34 248 VSS
34 DQ18 178 VSS 105 VSS 249 DQ35
35 VSS 179 DQ19 106 DQ44 250 VSS
36 DQ28 180 VSS 107 VSS 251 DQ45
37 VSS 181 DQ29 108 DQ40 252 VSS
38 DQ24 182 VSS 109 VSS 253 DQ41
Rev. 1.3 / Jun.2017 9

Front Side Back Side Front Side Back Side
Pin Pin Pin Pin
Pin Label Pin Label Pin Label Pin Label
39 VSS 183 DQ25 110 DM5_n, DBI5_n, NC 254 VSS
40 DM3_n, DBI3_n, NC 184 VSS 111 NC 255 DQS5_C
41 NC 185 DQS3_c 112 VSS 256 DQS5_t
42 VSS 186 DQS3_t 113 DQ46 257 VSS
43 DQ30 187 VSS 114 VSS 258 DQ47
44 VSS 188 DQ31 115 DQ42 259 VSS
45 DQ26 189 VSS 116 VSS 260 DQ43
46 VSS 190 DQ27 117 DQ52 261 VSS
47 CB4, NC 191 VSS 118 VSS 262 DQ53
48 VSS 192 CB5, NC 119 DQ48 263 VSS
49 CB0, NC 193 VSS 120 VSS 264 DQ49
50 VSS 194 CB1, NC 121 DM6_n, DBI6_n, NC 265 VSS
51 DM8_n, DBI8_n, NC 195 VSS 122 NC 266 DQS6_c
52 NC 196 DQS8_c 123 VSS 267 DQS6_t
53 VSS 197 DQS8_t 124 DQ54 268 VSS
54 CB6, NC 198 VSS 125 VSS 269 DQ55
55 VSS 199 CB7, NC 126 DQ50 270 VSS
56 CB2, NC 200 VSS 127 VSS 271 DQ51
57 VSS 201 CB3, NC 128 DQ60 272 VSS
58 RESET_n 202 VSS 129 VSS 273 DQ61
59 VDD 203 CKE1 130 DQ56 274 VSS
60 CKE0 204 VDD 131 VSS 275 DQ57
61 VDD 205 RFU 132 DM7_n, DBI7_n, NC 276 VSS
62 ACT_n 206 VDD 133 NC 277 DQS7_c
63 BG0 207 BG1 134 VSS 278 DQS7_t
64 VDD 208 ALERT_n 135 DQ62 279 VSS
65 A12/BC_n 209 VDD 136 VSS 280 DQ63
66 A9 210 A11 137 DQ58 281 VSS
67 VDD 211 A7 138 VSS 282 DQ59
68 A8 213 VDD 139 SA0 283 VSS
69 A6 214 A5 140 SA1 284 VDDSPD
70 VDD 215 A4 141 SCL 285 SDA
71 A3 215 VDD 142 VPP 286 VPP
72 A1 216 A2 143 VPP 287 VPP
73 VDD 217 VDD 144 RFU 288 VPP
Rev. 1.3 / Jun.2017 10

Functional Block Diagram
4GB, 512Mx64 Module(1Rank of x16)
CK0_t, CK0_c
A[16:0], BA[1:0]
ACT_n, PARITY,BG[1:0]
CS0_n
ODT0
CKE0
ZQ VSS ZQ VSS
CKE
ODT
CS_n
A,BA,BG,Par
CK
CKE
ODT
CS_n
A,BA,BG,Par
CK
DQS0_t DQL_t DQS2_t DQL_t
DQS0_c DQL_c D0 DQS2_c DQL_c D1
DQ [7:0] DQL [7:0] DQ [23:16] DQL [7:0]
DM0_n/DBI0_n DM0_n/DBI0_n DM2_n/DBI2_n DM0_n/DBI0_n
DQS1_t DQU_t DQS3_t DQU_t

DQS1_c DQU_c DQS3_c DQU_c
DQ [15:8] DQU [7:0] DQ [31:24] DQU [7:0]
ZQ VSS ZQ VSS
CKE
ODT
CS_n
A,BA,BG,Par
CK
CKE
ODT
CS_n
A,BA,BG,Par
CK
DQS4_t DQL_t DQS6_t DQL_t
DQS4_c DQL_c D2 DQS6_c DQL_c D3
DQ [39:32] DQL [7:0] DQ [55:48] DQL [7:0]
DQS5_t DQU_t DQS7_t DQU_t

DQS5_c DQU_c DQS7_c DQU_c
DQ [47:40] DQU [7:0] DQ [63:56] DQU [7:0]
VDDSPD SPD
VPP D0–D3 SCL SDA
VDD D0–D3 SA0 SA1 SA2
VTT
SA0 SA1 SA2
VREFCA D0–D3
Serial PD
VSS D0–D3
Note:
1. Unless otherwize noted, resistor values are 15 Ω ±5%.
2. ZQ resistors are 240 Ω ±1%.For all other resistor values refer to the appropriate wiring diagram.
Rev. 1.3 / Jun.2017 11

8GB, 1Gx64 Module(1Rank of x8)
CK0_t, CK0_c
A[16:0], BA[1:0]
CS0_n
ODT0
CKE0
ZQ VSS ZQ VSS
CKE
ODT
CS_n
Address
CK
CKE
ODT
CS_n
Address
CK
DQS0_t DQS_t DQS4_t DQS_t
DQS0_c DQS_c D0 DQS4_c DQS_c D4
DQ [7:0] DQ [7:0] DQ [39:32] DQ [7:0]
DM0_n/DBI0_n DM_n/DBI_n DM4_n/DBI4_n DM_n/DBI_n
ZQ VSS ZQ VSS
CKE
ODT
CS_n
Address
CK
CKE
ODT
CS_n
Address
CK
DQ [15:8] DQ [7:0] DQ [47:40] DQ [7:0]
ZQ VSS ZQ VSS
CKE
ODT
CS_n
Address
CK
CKE
ODT
CS_n
Address
CK
DQ [23:16] DQ [7:0] DQ [55:48] DQ [7:0]
ZQ VSS ZQ VSS
CKE
ODT
CS_n
Addressr
CK
CKE
ODT
CS_n
Address
CK
DQ [31:24] DQ [7:0] DQ [63:56] DQ [7:0]
VDDSPD SPD
SCL SDA
VPP D0–D7

VTT
SA0 SA1 SA2
VREFCA D0–D7
Serial PD
VSS D0–D7
Note:
3. For part 2 of 2 the DQ resistors are shown for simplicity but are the same physical components as shown on part 1 or 2
4. EVENT_n is wired on this design. A standalone SPD may be used as well. No wiring changes are required.
Rev. 1.3 / Jun.2017 12

CK0_t, CK0_c
A[16:0], BA[1:0]
CS0_n
ODT0
CKE0
ZQ VSS ZQ VSS
CKE
ODT
CS_n
Address
CK
CKE
ODT
CS_n
Address
CK
DQ [7:0] DQ [7:0] DQ [39:32] DQ [7:0]
ZQ VSS ZQ VSS
CKE
ODT
CS_n
Address
CK
CKE
ODT
CS_n
Address
CK
DQ [15:8] DQ [7:0] DQ [47:40] DQ [7:0]
ZQ VSS ZQ VSS
CKE
ODT
CS_n
Address
CK
CKE
ODT
CS_n
Address
CK
DQ [23:16] DQ [7:0] DQ [55:48] DQ [7:0]
ZQ VSS ZQ VSS
CKE
ODT
CS_n
Address
CK
CKE
ODT
CS_n
Address
CK
DQ [31:24] DQ [7:0] DQ [63:56] DQ [7:0]
ZQ VSS
CKE
ODT
CS_n
Address
CK
DQS3_t DQS_t
DQS3_c DQS_c D8
CB [7:0] DQ [7:0]
DM8_n/DBI8_n DM_n/DBI_n
VDDSPD SPD
SCL
VPP D0–D8 SDA
EVENT_n EVENT_n
VTT
SA0 SA1 SA2
VREFCA D0–D8
Serial PD with Thermal sensor
VSS D0–D8
Note:
3. For part 2 of 2 the DQ resistors are shown for simplicity but are the same physical components as shown on part 1 or 2
4. EVENT_n is wired on this design. A standalone SPD may be used as well. No wiring changes are required.
Rev. 1.3 / Jun.2017 13

16GB, 2Gx64 Module(2Rank of x8) - page1
CK0_t, CK0_c CK1_t, CK1_c

A[16:0], BA[1:0] A[16:0], BA[1:0]
ACT_n, PARITY,BG[1:0] ACT_n, PARITY,BG[1:0]
CS0_n CS1_n
ODT0 ODT1
CKE0 CKE1
ZQ VSS ZQ VSS
CKE
ODT
CS_n
A,BA,BG,Par
CK
CKE
ODT
CS_n
A,BA,BG,Par
CK
DQS0_t DQS_t DQS_t
DQS0_c DQS_c D0 DQS_c D15
DQ [7:0] DQ [7:0] DQ [7:0]
DM0_n/DBI0_n DM_n/DBI_n DM_n/DBI_n
ZQ VSS ZQ VSS
CKE
ODT
CS_n
A,BA,BG,Par
CK
CKE
ODT
CS_n
A,BA,BG,Par
CK
DQS1_t DQS_t DQS_t
DQ [15:8] DQ [7:0] DQ [7:0]
ZQ VSS ZQ VSS
CKE
ODT
CS_n
A,BA,BG,Par
CK
CKE
ODT
CS_n
A,BA,BG,Par
CK
DQS2_t DQS_t DQS_t
DQ [23:16] DQ [7:0] DQ [7:0]
ZQ VSS ZQ VSS
CKE
ODT
CS_n
A,BA,BG,Par
CK
CKE
ODT
CS_n
A,BA,BG,Par
CK
DQS3_t DQS_t DQS_t
DQ [31:24] DQ [7:0] DQ [7:0]
Note:
Rev. 1.3 / Jun.2017 14

16GB, 2Gx64 Module(2Rank of x8) - page2
CK0_t, CK0_c CK1_t, CK1_c

A[16:0], BA[1:0] A[16:0], BA[1:0]
ACT_n, PARITY,BG[1:0] ACT_n, PARITY,BG[1:0]
CS0_n CS1_n
ODT0 ODT1
CKE0 CKE1
ZQ VSS ZQ VSS
CKE
ODT
CS_n
A,BA,BG,Par
CK
CKE
ODT
CS_n
A,BA,BG,Par
CK
DQS4_t DQS_t DQS_t
DQ [39:32] DQ [7:0] DQ [7:0]
ZQ VSS ZQ VSS
CKE
ODT
CS_n
A,BA,BG,Par
CK
CKE
ODT
CS_n
A,BA,BG,Par
CK
DQS5_t DQS_t DQS_t
DQ [47:40] DQ [7:0] DQ [7:0]
ZQ VSS ZQ VSS
CKE
ODT
CS_n
A,BA,BG,Par
CK
CKE
ODT
CS_n
A,BA,BG,Par
CK
DQS6_t DQS_t DQS_t
DQ [55:48] DQ [7:0] DQ [7:0]
ZQ VSS ZQ VSS
CKE
ODT
CS_n
A,BA,BG,Par
CK
CKE
ODT
CS_n
A,BA,BG,Par
CK
DQS7_t DQS_t DQS_t
DQ [63:56] DQ [7:0] DQ [7:0]
VDDSPD SPD
SCL SDA
VPP D0–D15

VTT
SA0 SA1 SA2
VREFCA D0–D15
Serial PD
VSS D0–D15
Note:
3. EVENT_n is not wired on this design.
Rev. 1.3 / Jun.2017 15

A[16:0],BA[1:0],BG[1:0]
ACT_n, PARITY
CK0_t,CK0_c
CS0_n
ODT0
CKE0
CK1_t,CK1_c
CS1_n
ODT1
CKE1
ZQ VSS ZQ VSS ZQ VSS
CK
A,BA,BG,Par
CKE
ODT
CS_n
ZQ VSS
CK
A,BA,BG,Par
CKE
ODT
CS_n
CKE
ODT
CS_n
CK
A,BA,BG,Par
CKE
ODT
CS_n
CK
A,BA,BG,Par
DQS0_t DQS_t
D0 DQS_t D9 DQS4_t
DQS4_c
DQS_t
DQS_c
D5 DQS_t D14
DQS0_c DQS_c DQS_c DQS_c
DQ [7:0] DQ [7:0] DQ [7:0] DQ [39:32] DQ [7:0] DQ [7:0]
DM0_n/DBI0_n DM_n/DBI_n DM_n/DBI_n DM0_n/DBI0_n DM_n/DBI_n DM_n/DBI_n
CKE
ODT
CS_n
CK
A,BA,BG,Par
ZQ VSS
CKE
ODT
CS_n
CK
A,BA,BG,Par
CKE
ODT
CS_n
CK
A,BA,BG,Par
CKE
ODT
CS_n
CK
A,BA,BG,Par
DQS1_t DQS_t
D1 DQS_t D10 DQS5_t
DQS5_c
DQS_t
DQS_c
D6 DQS_t D15
DQ [15:8] DQ [7:0] DQ [7:0] DQ [47:40] DQ [7:0] DQ [7:0]
CKE
ODT
CS_n
CK
A,BA,BG,Par
ZQ VSS
CKE
ODT
CS_n
CK
A,BA,BG,Par
CK
A,BA,BG,Par
CKE
ODT
CS_n
CK
A,BA,BG,Par
CKE
ODT
CS_n
DQS2_t DQS_t D2 DQS_t

D11 DQS6_t
DQS6_c
DQS_t
DQS_c
D7 DQS_t
D16
DQ [23:16] DQ [7:0] DQ [7:0] DQ [55:48] DQ [7:0] DQ [7:0]

CKE
ODT
CS_n
CK
ZQ VSS A,BA,BG,Par
CKE
ODT
CS_n
CK
A,BA,BG,Par
CKE
ODT
CS_n
CK
A,BA,BG,Par
CKE
ODT
CS_n
CK
A,BA,BG,Par
DQS3_t DQS_t D3 DQS_t

D12 DQS7_t
DQS7_c
DQS_t
DQS_c
D8 DQS_t
D17
DQ [31:24] DQ [7:0] DQ [7:0] DQ [63:56] DQ [7:0] DQ [7:0]
ZQ VSS ZQ VSS
CK
A,BA,BG,Par
CKE
ODT
CS_n
CKE
ODT
CS_n
CK
A,BA,BG,Par
DQS8_t
DQS8_c
DQS_t
DQS_c
D4 DQS_t D13
DQS_c
CB [7:0] DQ [7:0] DQ [7:0]
VDDSPD SPD
SCL
VPP D0–D17 SDA
EVENT_n EVENT_n
VTT
SA0 SA1 SA2
VREFCA D0–D17
Serial PD with Thermal sensor
VSS D0–D17
Note:
1. Unless otherwize noted resistors are 15 Ω ±5%.
Rev. 1.3 / Jun.2017 16

Absolute Maximum Ratings
Absolute Maximum DC Ratings
Absolute Maximum DC Ratings
Symbol Parameter Rating Units NOTE
VDD Voltage on VDD pin relative to Vss -0.3 ~ 1.5 V 1,3
VDDQ Voltage on VDDQ pin relative to Vss -0.3 ~ 1.5 V 1,3
VPP Voltage on VPP pin relative to Vss -0.3 ~ 3.0 V 4
VIN, VOUT Voltage on any pin except VREFCA relative to Vss -0.3 ~ 1.5 V 1,3,5
TSTG Storage Temperature -55 to +100 °C 1,2
NOTE :
1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of the device at these or any other conditions above those indi-
cated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect reliability
2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement
conditions, please refer to JESD51-2 standard.
3. VDD and VDDQ must be within 300 mV of each other at all times;and VREFCA must be not greater than 0.6 x
VDDQ, When VDD and VDDQ are less than 500 mV; VREFCA may be equal to or less than 300 mV
4. VPP must be equal or greater than VDD/VDDQ at all times
5. Overshoot area above 1.5V is specified in DDR4 Device Operation.
DRAM Component Operating Temperature Range

Temperature Range
Symbol Parameter Rating Units Notes

0 to 85 oC 1,2
Normal Operating Temperature Range
TOPER oC
Extended Temperature Range 85 to 95 1,3
Notes:
1. Operating Temperature TOPER is the case surface temperature on the center / top side of the DRAM. For measure-
ment conditions, please refer to the JEDEC document JESD51-2.
2. The Normal Temperature Range specifies the temperatures where all DRAM specifications will be supported.
During operation, the DRAM case temperature must be maintained between 0 - 85oC under all operating condi-
tions.
3. Some applications require operation of the DRAM in the Extended Temperature Range between 85oC and 95oC
case temperature. Full specifications are guaranteed in this range, but the following additional conditions apply:
a. Refresh commands must be doubled in frequency, therefore reducing the Refresh interval tREFI to 3.9 µs. It is
also possible to specify a component with 1X refresh (tREFI to 7.8µs) in the Extended Temperature Range.
Please refer to the DIMM SPD for option availability
b. If Self-Refresh operation is required in the Extended Temperature Range, then it is mandatory to either use
the Manual Self-Refresh mode with Extended Temperature Range capability (MR2 A6 = 0b and MR2 A7 = 1b)
or enable the optional Auto Self-Refresh mode (MR2 A6 = 1b and MR2 A7 = 0b).
Rev. 1.2 / Jun.2017 17

AC & DC Operating Conditions
Recommended DC Operating Conditions
Recommended DC Operating Conditions
Rating
Symbol Parameter Unit NOTE
Min. Typ. Max.
VDD Supply Voltage 1.14 1.2 1.26 V 1,2,3
VDDQ Supply Voltage for Output 1.14 1.2 1.26 V 1,2,3
VPP Supply Voltage for DRAM Activating 2.375 2.5 2.75 V 3
NOTE:
1. Under all conditions VDDQ must be less than or equal to VDD.
2. VDDQ tracks with VDD. AC parameters are measured with VDD and VDDQ tied together.
3. DC bandwidth is limited to 20MHz.
Rev. 1.2 / Jun.2017 18

AC & DC Input Measurement Levels
AC & DC Logic input levels for single-ended signals
Single-ended AC & DC input levels for Command and Address
DDR4-1600/1866/2133/
DDR4-2666/3200
Symbol Parameter 2400 Unit NOTE
Min. Max. Min. Max.
VREFCA+
VIH.CA(DC75) DC input logic high VDD TBD TBD V
0.075
VREFCA-
VIL.CA(DC75) DC input logic low VSS TBD TBD V
0.075
VIH.CA(AC100) AC input logic high VREF + 0.1 Note 2 TBD TBD V 1
VIL.CA(AC100) AC input logic low Note 2 VREF - 0.1 TBD TBD V 1
Reference Voltage for
VREFCA(DC) 0.49*VDD 0.51*VDD TBD TBD V 2,3
ADD, CMD inputs
NOTE :
1. See “Overshoot and Undershoot Specifications”
2. The AC peak noise on VREFCA may not allow VREFCA to deviate from VREFCA(DC) by more than ± 1% VDD (for
reference : approx. ± 12mV)
3. For reference : approx. VDD/2 ± 12mV
Rev. 1.3 / Jun.2017 19

AC and DC Input Measurement Levels: VREF Tolerances
The DC-tolerance limits and ac-noise limits for the reference voltages VREFCA is illustrated in Figure below.
It shows a valid reference voltage VREF(t) as a function of time. (VREF stands for VREFCA).
VREF(DC) is the linear average of VREF(t) over a very long period of time (e.g. 1 sec). This average has to
meet the min/max requirement in Table X. Furthermore VREF(t) may temporarily deviate from VREF(DC) by
no more than ± 1% VDD.
voltage
VDD
VSS
time
Illustration of VREF(DC) tolerance and VREF AC-noise limits
The voltage levels for setup and hold time measurements VIH(AC), VIH(DC), VIL(AC) and VIL(DC) are
dependent on VREF.
"VREF" shall be understood as VREF(DC), as defined in Figure above.
This clarifies, that DC-variations of VREF affect the absolute voltage a signal has to reach to achieve a valid
high or low level and therefore the time to which setup and hold is measured. System timing and voltage
budgets need to account for VREF(DC) deviations from the optimum position within the data-eye of the
input signals.
This also clarifies that the DRAM setup/hold specification and derating values need to include time and
voltage associated with VREF AC-noise. Timing and voltage effects due to AC-noise on VREF up to the spec-
ified limit (+/-1% of VDD) are included in DRAM timings and their associated deratings.
Rev. 1.3 / Jun.2017 20

AC and DC Logic Input Levels for Differential Signals
Differential signal definition
tDVAC
VIH.DIFF.AC.MIN
VIH.DIFF.MIN
(CK_t - CK_c)
Differential Input Voltage (CK-CK)
0.0
half cycle
VIL.DIFF.MAX
VIL.DIFF.AC.MAX
tDVAC
time
NOTE:
1. Differential signal rising edge from VIL.DIFF.MAX to VIH.DIFF.MIN must be monotonic slope.
2. Differential signal falling edge from VIH.DIFF.MIN to VIL.DIFF.MAX must be monotonic slope.
Definition of differential ac-swing and “time above ac-level” tDVAC
Rev. 1.3 / Jun.2017 21

Differential swing requirements for clock (CK_t - CK_c)
Differential AC and DC Input Levels
DDR4 -1600,1866,2133 DDR4 -2400,2666 & 3200
Symbol Parameter unit NOTE
min max min max
VIHdiff differential input high +0.150 NOTE 3 TBD NOTE 3 V 1
VILdiff differential input low NOTE 3 -0.150 NOTE 3 TBD V 1
2 x (VIH(AC) - 2 x (VIH(AC) -
VIHdiff(AC) differential input high ac NOTE 3 NOTE 3 V 2
VREF) VREF)
2 x (VIL(AC) - 2 x (VIL(AC) -
VILdiff(AC) differential input low ac NOTE 3 NOTE 3 V 2
VREF) VREF)
NOTE :
1. Used to define a differential signal slew-rate.
2. for CK_t - CK_c use VIH.CA/VIL.CA(AC) of ADD/CMD and VREFCA;
3. These values are not defined; however, the differential signals CK_t - CK_c, need to be within the respective limits
(VIH.CA(DC) max, VIL.CA(DC)min) for single-ended signals as well as the limitations for overshoot and undershoot.
Allowed time before ringback (tDVAC) for CK_t - CK_c

tDVAC [ps] @ |VIH/Ldiff(AC)| = 200mV tDVAC [ps] @ |VIH/Ldiff(AC)| = TBDmV
Slew Rate [V/ns]
min max min max
> 4.0 120 - TBD -
4.0 115 - TBD -
3.0 110 - TBD -
2.0 105 - TBD -
1.8 100 - TBD -
1.6 95 - TBD -
1.4 90 - TBD -
1.2 85 - TBD -
1.0 80 - TBD -
< 1.0 80 - TBD -
Rev. 1.3 / Jun.2017 22

Single-ended requirements for differential signals
Each individual component of a differential signal (CK_t, CK_c) has also to comply with certain require-
ments for single-ended signals.
CK_t and CK_c have to approximately reach VSEHmin / VSELmax (approximately equal to the ac-levels
(VIH.CA(AC) / VIL.CA(AC) ) for ADD/CMD signals) in every half-cycle.
Note that the applicable ac-levels for ADD/CMD might be different per speed-bin etc. E.g., if Different
value than VIH.CA(AC100)/VIL.CA(AC100) is used for ADD/CMD signals, then these ac-levels apply also for
the single-ended signals CK_t and CK_c
VDD or VDDQ
VSEH min
VSEH
VDD/2 or VDDQ/2
CK
VSEL max
VSEL
VSS or VSSQ
time
Single-ended requirement for differential signals
Note that, while ADD/CMD signal requirements are with respect to VrefCA, the single-ended components
of differential signals have a requirement with respect to VDD / 2; this is nominally the same. The transi-
tion of single-ended signals through the ac-levels is used to measure setup time. For single-ended compo-
nents of differential signals the requirement to reach VSELmax, VSEHmin has no bearing on timing, but
adds a restriction on the common mode characteristics of these signals.
Rev. 1.3 / Jun.2017 23

Single-ended levels for CK_t, CK_c
DDR4-1600/1866/2133 DDR4-2400/2666/3200
Symbol Parameter Unit NOTE
Min Max Min Max
Single-ended high-level for (VDD/2)
VSEH NOTE3 TBD NOTE3 V 1, 2
CK_t , CK_c +0.100
Single-ended low-level for (VDD/2)-
VSEL NOTE3 NOTE3 TBD V 1, 2
CK_t , CK_c 0.100
NOTE :
1. For CK_t - CK_c use VIH.CA/VIL.CA(AC) of ADD/CMD;
2. VIH(AC)/VIL(AC) for ADD/CMD is based on VREFCA;
3. These values are not defined, however the single-ended signals CK_t - CK_c need to be within the respective limits
(VIH.CA(DC) max, VIL.CA(DC)min) for single-ended signals as well as the limitations for overshoot and undershoot.
Rev. 1.3 / Jun.2017 24

Address and Control Overshoot and Undershoot specifications
AC overshoot/undershoot specification for Address, Command and Control pins
Specification
Parameter DDR4- DDR4- DDR4- DDR4- DDR4- Unit
1600 1866 2133 2400 2666
Maximum peak amplitude above VDD Absolute Max
0.06 0.06 0.06 0.06 TBD V
allowed for overshoot area
Delta value between VDD Absolute Max and VDD Max
0.24 0.24 0.24 0.24 TBD V
Maximum peak amplitude allowed for undershoot area 0.3 0.3 0.3 0.3 TBD V-ns
Maximum overshoot area per 1tCK Above Absolute
0.0083 0.0071 0.0062 0.0055 TBD V-ns
Max
Maximum overshoot area per 1tCK Between Absolute
0.2550 0.2185 0.1914 0.1699 TBD V-ns
Max
Maximum undershoot area per 1tCK Below VSS 0.2644 0.2265 0.1984 0.1762 TBD V-ns
(A0-A13,A17,BG0-BG1,BA0-BA1,ACT_n,RAS_n/A16,CAS_n/A15,WE_n/A14,CS_n,CKE,ODT,C2-C0)
Overshoot Area above VDD Absolute Max

VDD Absolute Max Overshoot Area Between
VDD Absolute Max and VDD Max
VDD
Volts 1 tCK
(V)
VSS
Undershoot Area below VSS

Address,Command and Control Overshoot and Undershoot Definition
Rev. 1.3 / Jun.2017 25

Clock Overshoot and Undershoot Specifications
AC overshoot/undershoot specification for Clock
Specification
1600 1866 2133 2400 2666
Maximum peak amplitude above VDD Absolute Max
0.06 0.06 0.06 0.06 TBD V
Delta value between VDD Absolute Max and VDD Max
0.24 0.24 0.24 0.24 TBD V
Maximum peak amplitude allowed for undershoot area 0.3 0.3 0.3 0.3 TBD V
Maximum overshoot area per 1UI Above Absolute Max 0.0038 0.0032 0.0028 0.0025 TBD V-ns
Maximum overshoot area per 1UI Between Absolute
0.1125 0.0964 0.0844 0.0750 TBD V-ns
Max
Maximum undershoot area per 1UI Below VSS 0.1144 0.0980 0.0858 0.0762 TBD V-ns
(CK_t, Ck_c)
Overshoot Area above VDD Absolute Max

VDD Absolute Max Overshoot Area Between
VDD Absolute Max and VDD Max
VDD
Volts 1 UI
(V)
VSS
Undershoot Area below VSS

Clock Overshoot and Undershoot Definition
Rev. 1.3 / Jun.2017 26

Data, Strobe and Mask Overshoot and Undershoot Specifications
AC overshoot/undershoot specification for Data, Strobe and Mask
Specification
1600 1866 2133 2400 2666
Maximum peak amplitude above Max absolute level of
0.16 0.16 0.16 0.16 TBD V
Vin,Vout
Overshoot area Between Max Absolute level of Vin,
0.24 0.24 0.24 0.24 TBD V
Vout and VDDQ Max
Undershoot area Between Min absolute level of
0.30 0.30 0.30 0.30 TBD V
Vin,Vout and VDDQ Max
Maximum peak amplitude below Min absolute level of
0.10 0.10 0.10 0.10 TBD V
Vin,Vout
Maximum overshoot area per 1UI Above Max absolute
0.0150 0.0129 0.0113 0.0100 TBD V-ns
level of Vin,Vout
Maximum overshoot area per 1UI Between Max abso-
0.1050 0.0900 0.0788 0.0700 TBD V-ns
lute level of Vin,Vout and VDDQ Max
Maximum undershoot area per 1UI Between Min abso-
0.1050 0.0900 0.0788 0.0700 TBD V-ns
lute level of Vin,Vout and VSSQ
Maximum undershoot area per 1UI Below Min abso-
0.0150 0.0129 0.0113 0.0100 TBD V-ns
lute level of Vin,Vout
(DQ,DQS_t,DQS_c,DM_n, DBI_n, TDQS_t, TDQS_c)
Overshoot Area above Max absolute level of Vin,Vout
Max absolute level of Vin,Vout Overshoot Area Between

Max absolute level of Vin,Vout and VDDQ
VDDQ
Volts 1 UI
(V)
VSSQ
Undershoot Area Between

Min absolute level of Vin,Vout Min absolute level of Vin,Vout and VSSQ
Undershoot Area below Min absolute level of Vin, Vout
Data, Strobe and Mask Overshoot and Undershoot Definition
Rev. 1.3 / Jun.2017 27

Slew Rate Definitions
Slew Rate Definitions for Differential Input Signals (CK)
Input slew rate for differential signals (CK_t, CK_c) are defined and measured as shown in Table and Fig-
ure below.
Differential Input Slew Rate Definition
Description Defined by
from to
V V
Differential input slew rate for rising edge(CK_t - CK_c) ILdiffmax IHdiffmin [ VIHdiffmin - VILdiffmax ] / DeltaTRdiff
V V
Differential input slew rate for falling edge(CK_t - CK_c) IHdiffmin ILdiffmax [ VIHdiffmin - VILdiffmax ] / DeltaTFdiff
NOTE: The differential signal (i,e.,CK_t - CK_c) must be linear between these thresholds.
Delta TRdiff
Differential Input Voltage(i,e, CK_t - CK_c)
V
IHdiffmin
V
ILdiffmax
Delta TFdiff
Differential Input Slew Rate Definition for CK_t, CK_c
Rev. 1.3 / Jun.2017 28

Slew Rate Definition for Single-ended Input Signals (CMD/ADD)
Delta TRsingle
V
IHCA(AC) Min
V
IHCA(DC) Min
VREFCA(DC)
V
ILCA(DC) Max
V
ILCA(AC) Max
Delta TFsingle
Single-ended Input Slew Rate definition for CMD and ADD

NOTE :
1. Single-ended input slew rate for rising edge = { VIHCA(AC)Min - VILCA(DC)Max } / Delta TR single
2. Single-ended input slew rate for falling edge = { VIHCA(DC)Min - VILCA(AC)Max } / Delta TF single
3. Single-ended signal rising edge from VILCA(DC)Max to VIHCA(DC)Min must be monotonic slope.
4. Single-ended signal falling edge from VIHCA(DC)Min to VILCA(DC)Max must be monotonic slope
Rev. 1.3 / Jun.2017 29

Differential Input Cross Point Voltage
To guarantee tight setup and hold times as well as output skew parameters with respect to clock, each
cross point voltage of differential input signals (CK_t, CK_c) must meet the requirements in Table. The dif-
ferential input cross point voltage VIX is measured from the actual cross point of true and complement sig-
nals to the midlevel between of VDD and VSS.
VDD
CK_t
Vix
VDD/2
Vix
CK_c
VSEH VSEL
VSS
Vix Definition (CK)
Cross point voltage for differential input signals (CK)

DDR4-1600/1866/2133
Symbol Parameter
min max
VDD/2 - 145mV VDD/2 + 100mV
VSEL =< VDD/2 + 145mV
- Area of VSEH, VSEL =< VSEL =< =< VSEH =<
VDD/2 - 145mV =< VSEH
VDD/2 - 100mV VDD/2 + 145mV
Differential Input Cross Point
- (VDD/2 - VSEL) (VSEH - VDD/2)
VlX(CK) Voltage relative to VDD/2 for -120mV 120mV
+ 25mV - 25mV
CK_t, CK_c
DDR4-2400/2666/3200
Symbol Parameter
min max
- Area of VSEH, VSEL TBD TBD TBD TBD
Differential Input Cross Point
VlX(CK) Voltage relative to VDD/2 for TBD TBD TBD TBD
CK_t, CK_c
Rev. 1.3 / Jun.2017 30

CMOS rail to rail Input Levels
CMOS rail to rail Input Levels for RESET_n
CMOS rail to rail Input Levels for RESET_n
Parameter Symbol Min Max Unit NOTE
AC Input High Voltage VIH(AC)_RESET 0.8*VDD VDD V 6
DC Input High Voltage VIH(DC)_RESET 0.7*VDD VDD V 2
DC Input Low Voltage VIL(DC)_RESET VSS 0.3*VDD V 1
AC Input Low Voltage VIL(AC)_RESET VSS 0.2*VDD V 7
Rising time TR_RESET - 1.0 us 4
RESET pulse width tPW_RESET 1.0 - us 3,5
NOTE :
1. After RESET_n is registered LOW, RESET_n level shall be maintained below VIL(DC)_RESET during tPW_RESET,
otherwise, SDRAM may not be reset.
2. Once RESET_n is registered HIGH, RESET_n level must be maintained above VIH(DC)_RESET, otherwise, SDRAM
operation will not be guaranteed until it is reset asserting RESET_n signal LOW.
3. RESET is destructive to data contents.
4. No slope reversal(ringback) requirement during its level transition from Low to High.
5. This definition is applied only “Reset Procedure at Power Stable”.
6. Overshoot might occur. It should be limited by the Absolute Maximum DC Ratings.
7. Undershoot might occur. It should be limited by Absolute Maximum DC Ratings
tPW_RESET
0.8*VDD
0.7*VDD
0.3*VDD
0.2*VDD
TR_RESET
RESET_n Input Slew Rate Definition
Rev. 1.3 / Jun.2017 31

AC and DC Logic Input Levels for DQS Signals
Differential signal definition
Definition of differential DQS Signal AC-swing Level
Differential swing requirements for DQS (DQS_t - DQS_c)

Differential AC and DC Input Levels for DQS
DDR4-1600,1866,2133 DDR4-2400 DDR4-2666,3200
Symbol Parameter Unit Note
Min Max Min Max Min Max
VIHDiffPeak VIH.DIFF.Peak Voltage 186 Note2 TBD TBD TBD TBD mV 1
VILDiffPeak VIL.DIFF.Peak Voltage Note2 -186 TBD TBD TBD TBD mV 1
NOTE :
1. Used to define a differential signal slew-rate.
2. These values are not defined; however, the differential signals DQS_t - DQS_c, need to be within the respective
limits Overshoot, Undershoot Specification for single-ended signals.
Rev. 1.3 / Jun.2017 32

Peak voltage calculation method
The peak voltage of Differential DQS signals are calculated in a following equation.
VIH.DIFF.Peak Voltage = Max(f(t))
VIL.DIFF.Peak Voltage = Min(f(t))
f(t) = VDQS_t - VDQS_c
The Max(f(t)) or Min(f(t)) used t o determine the midpoint which to reference the +/-35% window of the
exempt non-monotonic signaling shall be the samllest peak voltage observed in all ui’s.
Definition of differential DQS Peak Voltage and rage of exempt non-monotonic signaling
Rev. 1.3 / Jun.2017 33

Differential Input Cross Point Voltage
To achieve tight RxMask input requirements as well as output skew parameters with respect to strobe, the
cross point voltage of differential input signals (DQS_t, DQS_c) must meet the requirements in Tabel
below. The differential input cross point voltage VIX_DQS (VIX_DQS_FR and VIX_DQS_RF) ins measured
from the actual cross point of DQS_t, DQS_c relative to the VDQSmid fo the DQS_t and DQS_c signals.
VDQSmid is the midpoint of the minimum levels achieved by the transitioning DQS_t and DQS_c signals,
and noted by VDQS_trans. VDQS_trans is the difference between the lowest horizontal tangent above
VDQSmid of the transitioning DQS signals and the highest horizontal tangent below VDQSmid of the tran-
sitioning DQS signals.
A non-monotonic transitioning signal’s ledge is exempt or not used in determination of a horizontal tangent
provieded the said ledge occurs within +/- 30% of the midpoint of either VID.DIFF.Peak Voltage (DQS_t
rising) of VIL.DIFF.Peak Voltage (DQS_c rising), refer to Furure Definition of differential DQS Peak Voltage
and rage of exempt non-monotonic signaling. A secondary horizontal tangent resulting from a ring-back
transition is also exempt in determination of a horizontal tangent. Thath is, a falling transition’s horizontal
tangent is derived from its negative slope to zero slope transition (point A in Fugure bloew) and a ring-
back’s horizontal tangent derived from its positive slope to zero slope transition (point B in Figure below) is
not a valid horizontal tangent; and a rising transition’s horizontal tangent is derived from its positive slope
to zero slope transition (point C in Figure below) and a ring-back’s horizontal tangent derived from its neg-
ative slope to zero slope transition (point D in Figure below) is not a valid horizontal tangent.
Vix Definition (DQS)
Rev. 1.3 / Jun.2017 34

Cross point voltage for differential input signals
DDR4- DDR4-
Symbol Parameter 1600,1866,2133,2400 2666,2933,3200 Unit Note
Min Max Min Max
DQS_t and DQS_c crossing relative
Vix_DOS_
to the midpoint of the DQS_t and - 25 TBD 25 % 1,2
ratio
DQS_c signal swings
NOTE :
1. Vix_DQS_Ratio is DQS VIX crossing (Vix_DQS_FR or Vix_DQS_RF) divided by VDQS_trans. VDQS_trans is the
difference between the lowest horizontal tangent above VDQSmid of the transitioning DQS signals and the highest
horizontal tangent below VDQSmid of the transitioning DQS signals.
2. VDQSmid will be similar to the VREFDQ internal setting value obtained during Vref Training if the DQS and DQs
drivers and paths are matched.
Rev. 1.3 / Jun.2017 35

Differential Input Slew Rate Definition
Input slew rate for differential signals (DQS_t, DQS_c) are defined and measured as shown in Figure
below.
NOTE :
1. Differential signal rising edge from VILDiff_DQS to VIHDiff_DQS must be monotonic slope.
2. Differential signal falling edge from VIHDiff_DQS to VILDiff_DQS must be monotonic slope.
Differential Input Slew Rate Definition for DQS_t, DQS_c
Differential Input Slew Rate Definition for DQS_t, DQS_c
From To
Differential input slew rate for
VILDiff_DQS VIHDiff_DQS |VILDiff_DQS - VIHDiff_DQS|/DeltaTRdiff
rising edge(DQS_t - DQS_c)
Differential input slew rate for
VIHDiff_DQS VILDiff_DQS |VILDiff_DQS - VIHDiff_DQS|/DeltaTFdiff
falling edge(DQS_t - DQS_c)
Differential Input Level for DQS_t, DQS_c

DDR4-1600,1866,2133 DDR4-2400 DDR4-2666,3200
VIHDiff_DQS Differential Input High 136 - 130 - TBD TBD mV
VILDiff_DQS Differential Input Low - -136 - -130 TBD TBD mV
Rev. 1.3 / Jun.2017 36

Differential Input Slew Rate for DQS_t, DQS_c
DDR4-1600,1866,2133 DDR4-2400 DDR4-2666,3200
Differential Input
SRIdiff 3 18 3 18 TBD TBD V/ns
Slew Rate
Rev. 1.3 / Jun.2017 37

AC and DC output Measurement levels
Single-ended AC & DC Output Levels
Single-ended AC & DC output levels
DDR4-1600/1866/2133/
Symbol Parameter Units NOTE
2400/2666/3200
VOH(DC) DC output high measurement level (for IV curve linearity) 1.1 x VDDQ V
VOM(DC) DC output mid measurement level (for IV curve linearity) 0.8 x VDDQ V
VOL(DC) DC output low measurement level (for IV curve linearity) 0.5 x VDDQ V
VOH(AC) AC output high measurement level (for output SR) (0.7 + 0.15) x VDDQ V 1
VOL(AC) AC output low measurement level (for output SR) (0.7 - 0.15) x VDDQ V 1
NOTE :
1. The swing of ± 0.15 × VDDQ is based on approximately 50% of the static single-ended output peak-to-peak swing
with a driver impedance of RZQ/7Ω and an effective test load of 50Ω to VTT = VDDQ.
Differential AC & DC Output Levels

Differential AC & DC output levels
DDR4-1600/1866/
Symbol Parameter Units NOTE
2133/2400/2666/3200
VOHdiff(AC) AC differential output high measurement level (for output SR) +0.3 x VDDQ V 1
VOLdiff(AC) AC differential output low measurement level (for output SR) -0.3 x VDDQ V 1
NOTE :
1. The swing of ± 0.3 × VDDQ is based on approximately 50% of the static differential output peak-to-peak swing with
a driver impedance of RZQ/7Ω and an effective test load of 50Ω to VTT = VDDQ at each of the differential outputs.
Rev. 1.3 / Jun.2017 38

Single-ended Output Slew Rate
With the reference load for timing measurements, output slew rate for falling and rising edges is defined
and measured between VOL(AC) and VOH(AC) for single ended signals as shown in Table and Figure below.
Single-ended output slew rate definition

Measured
From To
[VOH(AC)-VOL(AC)] /
Single ended output slew rate for rising edge VOL(AC) VOH(AC)
Delta TRse
[VOH(AC)-VOL(AC)] /
Single ended output slew rate for falling edge VOH(AC) VOL(AC)
Delta TFse
NOTE :
1. Output slew rate is verified by design and characterization, and may not be subject to production test.
VOH(AC)
VOL(AC)
delta TFse delta TRse
Single-ended Output Slew Rate Definition
Single-ended output slew rate

DDR4-1600 DDR4-1866 DDR4-2133 DDR4-2400 DDR4-2666 DDR4-3200
Parameter Symbol Units
Min Max Min Max Min Max Min Max Min Max Min Max
Single ended output slew rate SRQse 4 9 4 9 4 9 4 9 TBD TBD TBD TBD V/ns
Description: SR: Slew Rate
Q: Query Output (like in DQ, which stands for Data-in, Query-Output)
se: Single-ended Signals
For Ron = RZQ/7 setting
NOTE:
1. In two cases, a maximum slew rate of 12 V/ns applies for a single DQ signal within a byte lane.
-Case 1 is defined for a single DQ signal within a byte lane which is switching into a certain direction (either from high
to low or low to high) while all remaining DQ signals in the same byte lane are static (i.e. they stay at either high or
low).
-Case 2 is defined for a single DQ signal within a byte lane which is switching into a certain direction (either from high
to low or low to high) while all remaining DQ signals in the same byte lane are switching into the opposite direction
(i.e. from low to high or high to low respectively). For the remaining DQ signal switching into the opposite direction,
the regular maximum limit of 9 V/ns applies
Rev. 1.3 / Jun.2017 39

Differential Output Slew Rate
With the reference load for timing measurements, output slew rate for falling and rising edges is defined
and measured between VOLdiff(AC) and VOHdiff(AC) for differential signals as shown in Table and Figure
below.
Differential output slew rate definition

Measured
From To
[VOHdiff(AC)-VOLdiff(AC)] /
Differential output slew rate for rising edge VOLdiff(AC) VOHdiff(AC)
Delta TRdiff
[VOHdiff(AC)-VOLdiff(AC)] /
Differential output slew rate for falling edge VOHdiff(AC) VOLdiff(AC)
Delta TFdiff
NOTE :
1. Output slew rate is verified by design and characterization, and may not be subject to production test.
VOHdiff(AC)
VOLdiff(AC)
delta TFdiff delta TRdiff
Differential Output Slew Rate Definition
Differential output slew rate

DDR4-1600 DDR4-1866 DDR4-2133 DDR4-2400 DDR4-2666 DDR4-3200
Parameter Symbol Units
Min Max Min Max Min Max Min Max Min Max Min Max
Differential output slew rate SRQdiff 8 18 8 18 8 18 8 18 TBD TBD TBD TBD V/ns
Description:
SR: Slew Rate
Q: Query Output (like in DQ, which stands for Data-in, Query-Output)
diff: Differential Signals
For Ron = RZQ/7 setting
Rev. 1.3 / Jun.2017 40

Single-ended AC & DC Output Levels of Connectivity Test Mode
Following output parameters will be applied for DDR4 SDRAM Output Signal during Connectivity Test
Mode.
Single-ended AC & DC output levels of Connectivity Test Mode

DDR4-1600/1866/2133/
2400/2666/3200
VOH(DC) DC output high measurement level (for IV curve linearity) 1.1 x VDDQ V
VOM(DC) DC output mid measurement level (for IV curve linearity) 0.8 x VDDQ V
VOL(DC) DC output low measurement level (for IV curve linearity) 0.5 x VDDQ V
VOB(DC) DC output below measurement level (for IV curve linearity) 0.2 x VDDQ V
VOH(AC) AC output high measurement level (for output SR) VTT + (0.1 x VDDQ) V 1
VOL(AC) AC output below measurement level (for output SR) VTT - (0.1 x VDDQ) V 1
NOTE :
1. The effective test load is 50 terminated by VTT = 0.5 * VDDQ.
VOH(AC)
VTT 0.5 * VDDQ
VOL(AC)
TF_output_CT TR_output_CT
Differential Output Slew Rate Definition of Connectivity Test Mode
Single-ended output slew rate of Connectivity Test Mode

DDR4-1600/1866/2133/2400/2666/3200
Parameter Symbol Unit Note
Min Max
Output signal Falling time TF_output_CT - 10 ns/V
Output signal Rising time TR_output_CT - 10 ns/V
Rev. 1.3 / Jun.2017 41

Standard Speed Bins
DDR4-1600 Speed Bins and Operations
Speed Bin DDR4-1600K
CL-nRCD-nRP 11-11-11 Unit NOTE
Parameter Symbol min max
Internal read command to first 13.75
tAA 18.00 ns 10
data (13.50)5,10
Internal read command to first
tAA_DBI tAA(min) + 2nCK tAA(max) +2nCK ns 10
data with read DBI enabled
ACT to internal read or write 13.75
tRCD - ns 10
delay time (13.50)5,10
13.75
PRE command period tRP - ns 10
(13.50)5,10
ACT to PRE command period tRAS 35 9 x tREFI ns 10
ACT to ACT or REF command 48.75
tRC - ns 10
period (48.50)5,10
Normal Read DBI
1,2,3,4,9,
CL = 9 CL = 11 tCK(AVG) 1.5 1.6 ns
CWL = 9 12
CL = 10 CL = 12 tCK(AVG) Reserved ns 1,2,3,4,9
CL = 10 CL = 12 tCK(AVG) Reserved ns 1,2,3,4
CWL = 9,11 CL = 11 CL = 13 tCK(AVG) 1.25 <1.5 ns 1,2,3,4
CL = 12 CL = 14 tCK(AVG) 1.25 <1.5 ns 1,2,3
Supported CL Settings 9,11,12 nCK 11,12
Supported CL Settings with read DBI 11,13,14 nCK 11
Supported CWL Settings 9,11 nCK
Rev. 1.3 / Jun.2017 42

Speed Bin DDR4-1866M
Internal read command to first 13.9212
tAA 18.00 ns 10
data (13.50)5,10
Internal read command to first
tAA_DBI tAA(min) + 2nCK tAA(max) +2nCK ns 10
data with read DBI enabled
ACT to internal read or write delay 13.92
tRCD - ns 10
time (13.50)5,10
13.92
(13.50)5,10
ACT to ACT or REF command 47.92
tRC - ns 10
period (47.50)5,10
Normal Read DBI
1,2,3,4,9,
CL = 9 CL = 11 tCK(AVG) 1.5 1.6 ns
CWL = 9 10
CL = 10 CL = 12 tCK(AVG) Reserved ns 4
CWL = 9,11 CL = 11 CL = 13 tCK(AVG) 1.25 <1.5 ns 1,2,3,4,6
CL = 12 CL = 14 tCK(AVG) 1.25 <1.5 ns 1,2,3,6
CL = 14 CL = 16 tCK(AVG) 1.071 <1.25 ns 1,2,3
Supported CL Settings 9,11,12,13,14 nCK 11,12
Supported CL Settings with read DBI 11,13,14 ,15,16 nCK 12
Supported CWL Settings 9,10,11,12 nCK
Rev. 1.3 / Jun.2017 43

Speed Bin DDR4-2133P
12
14.06
Internal read command to first data tAA 18.00 ns 10
(13.50)5,10
Internal read command to first data
tAA_DBI tAA(min)+3nCK tAA(max)+3nCK ns 10
with read DBI enabled
tRCD - ns 10
time (13.50)5,10
14.06
(13.50)5,10
47.06
ACT to ACT or REF command period tRC - ns 10
(46.50)5,10
Normal Read DBI
1,2,3,4,9,1
CL = 9 CL = 11 tCK(AVG) 1.5 1.6 ns
CWL = 9 2
CL = 11 CL = 13 tCK(AVG) 1.25 <1.5 ns 1,2,3,4,7
CWL = 9,11
CL = 12 CL = 14 tCK(AVG) 1.25 <1.5 ns 1,2,3,7
CL = 13 CL = 15 tCK(AVG) 1.071 <1.25 ns 1,2,3,4,7
CWL = 10,12
CL = 14 CL = 16 tCK(AVG) 1.071 <1.25 ns 1,2,3,7
CL = 16 CL = 19 tCK(AVG) 0.937 <1.071 ns 1,2,3
Supported CL Settings 9,11,12,13,14,15,16 nCK 11,12
Supported CL Settings with read DBI 11,13,14,15,16,18,19 nCK
Supported CWL Settings 9,10,11,12,14 nCK
Rev. 1.3 / Jun.2017 44

Speed Bin DDR4-2400T
14.16
Internal read command to first data tAA 18.00 ns 10
(13.75)5,10
Internal read command to first data
tAA_DBI tAA(min)+3nCK tAA(max)+3nCK ns 10
with read DBI enabled
tRCD - ns 10
time (13.75)5,10
14.16
(13.75)5,10
46.16
ACT to ACT or REF command period tRC - ns 10
(45.75)5,10
Normal Read DBI
CWL = 9
CL = 10 CL = 12 tCK(AVG) 1.5 1.6 ns 1,2,3,4,9
CL = 12 CL = 14 tCK(AVG) 1.25 <1.5 ns 1,2,3,8
CL = 14 CL = 16 tCK(AVG) 1.071 <1.25 ns 1,2,3,8
CL = 16 CL = 19 tCK(AVG) 0.937 <1.071 ns 1,2,3,8
CWL = 12,16
CL = 17 CL = 20 tCK(AVG) 0.833 <0.937 ns
CL = 18 CL = 21 tCK(AVG) 0.833 <0.937 ns 1,2,3
Supported CL Settings 10,11,12,13,14,15,16,17,18 nCK 11
Supported CL Settings with read DBI 12,13,14,15,16,18,19,20,21 nCK
Supported CWL Settings 9,10,11,12,14,16 nCK
Rev. 1.3 / Jun.2017 45

Speed Bin Table Notes
Absolute Specification
- VDDQ = VDD = 1.20V +/- 0.06 V
- VPP = 2.5V +0.25/-0.125 V
- The values defined with above-mentioned table are DLL ON case.
- DDR4-1600, 1866, 2133 and 2400 Speed Bin Tables are valid only when Geardown Mode is disabled.
1. The CL setting and CWL setting result in tCK(avg).MIN and tCK(avg).MAX requirements. When making
a selection of tCK(avg), both need to be fulfilled: Requirements from CL setting as well as require-
ments from CWL setting.
2. tCK(avg).MIN limits: Since CAS Latency is not purely analog - data and strobe output are synchronized
by the DLL - all possible intermediate frequencies may not be guaranteed. CL in clock cycle is calcu-
lated from tAA following rounding algorithm defined in DDR4 Device Operation(Rounding Algorithms)
3. tCK(avg).MAX limits: Calculate tCK(avg) = tAA.MAX / CL SELECTED and round the resulting tCK(avg)
down to the next valid speed bin (i.e. 1.5ns or 1.25ns or 1.071 ns or 0.938 ns or 0.833 ns). This result
is tCK(avg).MAX corresponding to CL SELECTED.
4. ‘Reserved’ settings are not allowed. User must program a different value.
5. 'Optional' settings allow certain devices in the industry to support this setting, however, it is not a
mandatory feature. Refer to supplier's data sheet and/or the DIMM SPD information if and how this
setting is supported.
6. Any DDR4-1866 speed bin also supports functional operation at lower frequencies as shown in the
table which are not subject to Production Tests but verified by Design/Characterization.
9. DDR4-1600 AC timing apply if DRAM operates at lower than 1600 MT/s data rate.
10. Parameters apply from tCK(avg)min to tCK(avg)max at all standard JEDEC clock period values as
stated in the Speed Bin Tables.
11. CL number in parentheses, it means that these numbers are optional.
12. DDR4 SDRAM supports CL=9 as long as a system meets tAA(min).
13. Each speed bin lists the timing requirements that need to be supported in order for a given DRAM to
be JEDEC compliant. JEDEC compliance does not require support for all speed bins within a given
speed. JEDEC compliance requires meeting the parameters for a least one of the listed speed bins.
Rev. 1.3 / Jun.2017 46

IDD and IDDQ Specification Parameters and Test Conditions
IDD, IPP and IDDQ Measurement Conditions
In this chapter, IDD, IPP and IDDQ measurement conditions such as test load and patterns are defined.
Figure shows the setup and test load for IDD, IPP and IDDQ measurements.
• IDD currents (such as IDD0, IDD0A, IDD1, IDD1A, IDD2N, IDD2NA, IDD2NL, IDD2NT, IDD2P, IDD2Q,
IDD3N, IDD3NA, IDD3P, IDD4R, IDD4RA, IDD4W, IDD4WA, IDD5B, IDD5F2, IDD5F4, IDD6N, IDD6E,
IDD6R, IDD6A, IDD7 and IDD8) are measured as time-averaged currents with all VDD balls of the
DDR4 SDRAM under test tied together. Any IPP or IDDQ current is not included in IDD currents.
• IPP currents have the same definition as IDD except that the current on the VPP supply is measured.
• IDDQ currents (such as IDDQ2NT and IDDQ4R) are measured as time-averaged currents with all
VDDQ balls of the DDR4 SDRAM under test tied together. Any IDD current is not included in IDDQ cur-
rents.
Attention: IDDQ values cannot be directly used to calculate IO power of the DDR4 SDRAM. They can
be used to support correlation of simulated IO power to actual IO power as outlined in Figure 2. In
DRAM module application, IDDQ cannot be measured separately since VDD and VDDQ are using one
merged-power layer in Module PCB.
For IDD, IPP and IDDQ measurements, the following definitions apply:
• “0” and “LOW” is defined as VIN <= VILAC(max).
• “1” and “HIGH” is defined as VIN >= VIHAC(min).
• “MID-LEVEL” is defined as inputs are VREF = VDD / 2.
• Timings used for IDD, IPP and IDDQ Measurement-Loop Patterns are provided in Table 1.
• Basic IDD, IPP and IDDQ Measurement Conditions are described in Table 2.
• Detailed IDD, IPP and IDDQ Measurement-Loop Patterns are described in Table 3 through Table 11.
• IDD Measurements are done after properly initializing the DDR4 SDRAM. This includes but is not lim-
ited to setting 
RON = RZQ/7 (34 Ohm in MR1); 
RTT_NOM = RZQ/6 (40 Ohm in MR1);
RTT_WR = RZQ/2 (120 Ohm in MR2);
RTT_PARK = Disable;
Qoff = 0B (Output Buffer enabled) in MR1;
TDQS_t disabled in MR1;
CRC disabled in MR2;
CA parity feature disabled in MR5;
Gear down mode disabled in MR3
Read/Write DBI disabled in MR5;
DM disabled in MR5
• Attention: The IDD, IPP and IDDQ Measurement-Loop Patterns need to be executed at least one time
before actual IDD or IDDQ measurement is started.
• Define D = {CS_n, ACT_n, RAS_n, CAS_n, WE_n } := {HIGH, LOW, LOW, LOW, LOW} ; apply BG/BA
changes when directed.
• Define D# = {CS_n, ACT_n, RAS_n, CAS_n, WE_n } := {HIGH, HIGH, HIGH, HIGH, HIGH} ; apply
invert of BG/BA changes when directed above.
Rev. 1.2 / Jun.2017 47

IDD IPP IDDQ
VDD VPP VDDQ

RESET
CK_t/CK_c
DDR4 SDRAM
CKE
CS DQS_t/DQS_c
C DQ
ACT,RAS,CAS,WE DM
A,BG,BA
ODT VSS VSSQ
ZQ
NOTE:
1. DIMM level Output test load condition may be different from above
Figure 1 - Measurement Setup and Test Load for IDD, IPP and IDDQ Measurements
Application specific
memory channel IDDQ
TestLad
environment
Channel
IO Powe IDDQ IDDQ
Simuaion Measurement
Simulatin
X Correlation
X
Channel IO Power
Number
Figure 2 - Correlation from simulated Channel IO Power to actual Channel IO Power supported by IDDQ
Measurement
Rev. 1.2 / Jun.2017 48

Table 1 -Timings used for IDD, IPP and IDDQ Measurement-Loop Patterns
DDR4-1600 DDR4-1866 DDR4-2133 DDR4-2400
Symbol Unit
11-11-11 13-13-13 15-15-15 17-17-17
tCK 1.25 1.071 0.937 0.833 ns
CL 11 13 15 17 nCK
CWL 11 12 14 17 nCK
nRCD 11 13 15 17 nCK
nRC 39 45 51 56 nCK
nRAS 28 32 36 39 nCK
nRP 11 13 15 17 nCK
x4 16 16 16 16 nCK
nFAW x8 20 22 23 26 nCK
x16 28 28 32 36 nCK
x4 4 4 4 4 nCK
nRRDS x8 4 4 4 4 nCK
x16 5 5 6 7 nCK
x4 5 5 6 6 nCK
nRRDL x8 5 5 6 6 nCK
x16 6 6 7 8 nCK
tCCD_S 4 4 4 4 nCK
tCCD_L 5 5 6 6 nCK
tWTR_S 2 3 3 3 nCK
tWTR_L 6 7 8 9 nCK
nRFC 2Gb 128 150 171 193 nCK
nRFC 4Gb 208 243 278 313 nCK
nRFC 8Gb 280 327 374 421 nCK
nRFC 16Gb TBD TBD TBD TBD nCK
Rev. 1.2 / Jun.2017 49

Table 2 -Basic IDD, IPP and IDDQ Measurement Conditions
Symbol Description
Operating One Bank Active-Precharge Current (AL=0)
CKE: High; External clock: On; tCK, nRC, nRAS, CL: see Table 1; BL: 81; AL: 0; CS_n: High
between ACT and PRE; Command, Address, Bank Group Address, Bank Address Inputs: partially
IDD0
toggling according to Table 3; Data IO: VDDQ; DM_n: stable at 1; Bank Activity: Cycling with one
bank active at a time: 0,0,1,1,2,2,... (see Table 3); Output Buffer and RTT: Enabled in Mode Regis-
ters2; ODT Signal: stable at 0; Pattern Details: see Table 3
Operating One Bank Active-Precharge Current (AL=CL-1)
IDD0A
AL = CL-1, Other conditions: see IDD0
Operating One Bank Active-Precharge IPP Current
IPP0
Same condition with IDD0
Operating One Bank Active-Read-Precharge Current (AL=0)
CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, CL: see Table 1; BL: 81; AL: 0; CS_n: High
between ACT, RD and PRE; Command, Address, Bank Group Address, Bank Address Inputs,
IDD1
Data IO: partially toggling according to Table 4; DM_n: stable at 1; Bank Activity: Cycling with one
bank active at a time: 0,0,1,1,2,2,... (see Table 4); Output Buffer and RTT: Enabled in Mode Regis-
ters2; ODT Signal: stable at 0; Pattern Details: see Table 4
Operating One Bank Active-Read-Precharge Current (AL=CL-1)
IDD1A
AL = CL-1, Other conditions: see IDD1
Operating One Bank Active-Read-Precharge IPP Current
IPP1
Precharge Standby Current (AL=0)
CKE: High; External clock: On; tCK, CL: see Table 1; BL: 81; AL: 0; CS_n: stable at 1; Command,
IDD2N Address, Bank Group Address, Bank Address Inputs: partially toggling according to Table 5; Data
IO: VDDQ; DM_n: stable at 1; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in
Mode Registers2; ODT Signal: stable at 0; Pattern Details: see Table 5
Precharge Standby Current (AL=CL-1)
IDD2NA
AL = CL-1, Other conditions: see IDD2N
Precharge Standby IPP Current
IPP2N
Same condition with IDD2N
Precharge Standby ODT Current
IDD2NT Address, Bank Group Address, Bank Address Inputs: partially toggling according to Table 6; Data
IO: VSSQ; DM_n: stable at 1; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in
Mode Registers2; ODT Signal: toggling according to Table 6; Pattern Details: see Table 6
IDDQ2NT Precharge Standby ODT IDDQ Current
(Optional) Same definition like for IDD2NT, however measuring IDDQ current instead of IDD current
Precharge Standby Current with CAL enabled
IDD2NL
Same definition like for IDD2N, CAL enabled3
Precharge Standby Current with Gear Down mode enabled
IDD2NG
Same definition like for IDD2N, Gear Down mode enabled3,5
Precharge Standby Current with DLL disabled
IDD2ND
Same definition like for IDD2N, DLL disabled3
Rev. 1.2 / Jun.2017 50

Precharge Standby Current with CA parity enabled
IDD2N_par
Same definition like for IDD2N, CA parity enabled3
Precharge Power-Down Current CKE: Low; External clock: On; tCK, CL: see Table 1; BL: 81; AL:
0; CS_n: stable at 1; Command, Address, Bank Group Address, Bank Address Inputs: stable at
IDD2P
0; Data IO: VDDQ; DM_n: stable at 1; Bank Activity: all banks closed; Output Buffer and RTT:
Enabled in Mode Registers2; ODT Signal: stable at 0
Precharge Power-Down IPP Current
IPP2P
Same condition with IDD2P
Precharge Quiet Standby Current
IDD2Q Address, Bank Group Address, Bank Address Inputs: stable at 0; Data IO: VDDQ; DM_n: stable
at 1;Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers2; ODT
Signal: stable at 0
Active Standby Current
IDD3N Address, Bank Group Address, Bank Address Inputs: partially toggling according to Table 5; Data
IO: VDDQ; DM_n: stable at 1;Bank Activity: all banks open; Output Buffer and RTT: Enabled in
Mode Registers2; ODT Signal: stable at 0; Pattern Details: see Table 5
Active Standby Current (AL=CL-1)
IDD3NA
AL = CL-1, Other conditions: see IDD3N
Active Standby IPP Current
IPP3N
Active Power-Down Current
CKE: Low; External clock: On; tCK, CL: see Table 1; BL: 81; AL: 0; CS_n: stable at 1; Command,
IDD3P Address, Bank Group Address, Bank Address Inputs: stable at 0; Data IO: VDDQ; DM_n: stable
at 1; Bank Activity: all banks open; Output Buffer and RTT: Enabled in Mode Registers2; ODT Signal:
stable at 0
Active Power-Down IPP Current
IPP3P
Same condition with IDD3P
Operating Burst Read Current
CKE: High; External clock: On; tCK, CL: see Table 1; BL: 82; AL: 0; CS_n: High between RD;
Command, Address, Bank Group Address, Bank Address Inputs: partially toggling according to
IDD4R Table 7; Data IO: seamless read data burst with different data between one burst and the next one
according to Table 7; DM_n: stable at 1; Bank Activity: all banks open, RD commands cycling through
banks: 0,0,1,1,2,2,... (see Table 7); Output Buffer and RTT: Enabled in Mode Registers2; ODT Signal:
stable at 0; Pattern Details: see Table 7
Operating Burst Read Current (AL=CL-1)
IDD4RA
AL = CL-1, Other conditions: see IDD4R
Operating Burst Read Current with Read DBI
IDD4RB
Read DBI enabled3, Other conditions: see IDD4R
Operating Burst Read IPP Current
IPP4R
Same condition with IDD4R
IDDQ4R Operating Burst Read IDDQ Current
(Optional) Same definition like for IDD4R, however measuring IDDQ current instead of IDD current
IDDQ4RB Operating Burst Read IDDQ Current with Read DBI
(Optional) Same definition like for IDD4RB, however measuring IDDQ current instead of IDD current
Rev. 1.2 / Jun.2017 51

Operating Burst Write Current
CKE: High; External clock: On; tCK, CL: see Table 1; BL: 81; AL: 0; CS_n: High between WR;
IDD4W Table 8; Data IO: seamless write data burst with different data between one burst and the next one
according to Table 8; DM_n: stable at 1; Bank Activity: all banks open, WR commands cycling through
banks: 0,0,1,1,2,2,... (see Table 8); Output Buffer and RTT: Enabled in Mode Registers2; ODT Signal:
stable at HIGH; Pattern Details: see Table 8
Operating Burst Write Current (AL=CL-1)
IDD4WA
AL = CL-1, Other conditions: see IDD4W
Operating Burst Write Current with Write DBI
IDD4WB
Write DBI enabled3, Other conditions: see IDD4W
Operating Burst Write Current with Write CRC
IDD4WC
Write CRC enabled3, Other conditions: see IDD4W
Operating Burst Write Current with CA Parity
IDD4W_par
CA Parity enabled3, Other conditions: see IDD4W
Operating Burst Write IPP Current
IPP4W
Same condition with IDD4W
Burst Refresh Current (1X REF)
CKE: High; External clock: On; tCK, CL, nRFC: see Table 1; BL: 81; AL: 0; CS_n: High between REF;
IDD5B
Table 9; Data IO: VDDQ; DM_n: stable at 1; Bank Activity: REF command every nRFC (see Table 9);
Output Buffer and RTT: Enabled in Mode Registers2; ODT Signal: stable at 0; Pattern Details: see
Table 9
Burst Refresh Write IPP Current (1X REF)
IPP5B
Same condition with IDD5B
IDD5F2
tRFC=tRFC_x2, Other conditions: see IDD5B
IPP5F2
Same condition with IDD5F2
IDD5F4
tRFC=tRFC_x4, Other conditions: see IDD5B
IPP5F4
Same condition with IDD5F4
Self Refresh Current: Normal Temperature Range
TCASE: 0 - 85°C; Low Power Array Self Refresh (LP ASR) : Normal4; CKE: Low; External clock:
IDD6N Off; CK_t and CK_c#: LOW; CL: see Table 1; BL: 81; AL: 0; CS_n#, Command, Address, Bank Group
Address, Bank Address, Data IO: High; DM_n: stable at 1; Bank Activity: Self-Refresh operation;
Output Buffer and RTT: Enabled in Mode Registers2; ODT Signal: MID-LEVEL
Self Refresh IPP Current: Normal Temperature Range
IPP6N
Self-Refresh Current: Extended Temperature Range)
TCASE: 0 - 95°C; Low Power Array Self Refresh (LP ASR) : Extended4; CKE: Low; External clock:
IDD6E Off; CK_t and CK_c: LOW; CL: see Table 1; BL: 81; AL: 0; CS_n, Command, Address, Bank Group
Address, Bank Address, Data IO: High; DM_n:stable at 1; Bank Activity: Extended Temperature
Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registers2; ODT Signal: MID-LEVEL
Self Refresh IPP Current: Extended Temperature Range
IPP6E
Same condition with IDD6E
Rev. 1.2 / Jun.2017 52

Self-Refresh Current: Reduced Temperature Range
TCASE: 0 - TBD (~35-45)°C; Low Power Array Self Refresh (LP ASR) : Reduced4; CKE: Low;
External clock: Off; CK_t and CK_c#: LOW; CL: see Table 1; BL: 81; AL: 0; CS_n#, Command,
IDD6R
Address, Bank Group Address, Bank Address, Data IO: High; DM_n:stable at 1; Bank Activity:
Extended Temperature Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registers2;
ODT Signal: MID-LEVEL
Self Refresh IPP Current: Reduced Temperature Range
IPP6R
Same condition with IDD6R
Auto Self-Refresh Current
TCASE: 0 - 95°C; Low Power Array Self Refresh (LP ASR) : Auto4; CKE: Low; External clock: Off;
IDD6A CK_t and CK_c#: LOW; CL: see Table 1; BL: 81; AL: 0; CS_n#, Command, Address, Bank Group
Address, Bank Address, Data IO: High; DM_n:stable at 1; Bank Activity: Auto Self-Refresh
operation; Output Buffer and RTT: Enabled in Mode Registers2; ODT Signal: MID-LEVEL
Auto Self-Refresh IPP Current
IPP6A
Same condition with IDD6A
Operating Bank Interleave Read Current
CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, nRRD, nFAW, CL: see Table 1; BL: 81; AL:
CL-1; CS_n: High between ACT and RDA; Command, Address, Bank Group Address, Bank Address
IDD7 Inputs: partially toggling according to Table 10; Data IO: read data bursts with different data between
one burst and the next one according to Table 10; DM_n: stable at 1; Bank Activity: two times
interleaved cycling through banks (0, 1, ...7) with different addressing, see Table 10; Output Buffer and
RTT: Enabled in Mode Registers2; ODT Signal: stable at 0; Pattern Details: see Table 10
Operating Bank Interleave Read IPP Current
IPP7
Maximum Power Down Current
IDD8
TBD
Maximum Power Down IPP Current
IPP8
Rev. 1.2 / Jun.2017 53

NOTE :
1. Burst Length: BL8 fixed by MRS: set MR0 [A1:0=00].
2. Output Buffer Enable
- set MR1 [A12 = 0] : Qoff = Output buffer enabled
- set MR1 [A2:1 = 00] : Output Driver Impedance Control = RZQ/7
RTT_Nom enable
- set MR1 [A10:8 = 011] : RTT_NOM = RZQ/6
RTT_WR enable
- set MR2 [A10:9 = 01] : RTT_WR = RZQ/2
RTT_PARK disable
- set MR5 [A8:6 = 000]
3. CAL enabled : set MR4 [A8:6 = 001] : 1600MT/s
010] : 1866MT/s, 2133MT/s
011] : 2400MT/s
Gear Down mode enabled :set MR3 [A3 = 1] : 1/4 Rate
DLL disabled : set MR1 [A0 = 0]
CA parity enabled :set MR5 [A2:0 = 001] : 1600MT/s,1866MT/s, 2133MT/s
010] : 2400MT/s
Read DBI enabled : set MR5 [A12 = 1]
Write DBI enabled : set :MR5 [A11 = 1]
4. Low Power Array Self Refresh (LP ASR) : set MR2 [A7:6 = 00] : Normal
01] : Reduced Temperature range
10] : Extended Temperature range
11] : Auto Self Refresh
5. IDD2NG should be measured after sync pulse(NOP) input.
Rev. 1.2 / Jun.2017 54

Table 3 - IDD0, IDD0A and IPP0 Measurement-Loop Pattern1
RAS_n/ A16
CAS_n/ A15
A[17,13,11]
CK_t /CK_c
WE_n/ A14
A12/BC_n
Command
Sub-Loop
A[10]/AP
BG[1:0]2
Number
BA[1:0]
C[2:0]3
ACT_n
A[9:7]
A[6:3]
A[2:0]
Cycle
CS_n
ODT
CKE
Data4
0 0 ACT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -
1,2 D, D 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -
D_#,
3,4
D_#
1 1 1 1 1 0 0 32 3 0 0 0 7 F 0 -
... repeat pattern 1...4 until nRAS - 1, truncate if necessary

nRAS PRE 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 -
... repeat pattern 1...4 until nRC - 1, truncate if necessary
1 1*nRC repeat Sub-Loop 0, use BG[1:0]2 = 1, BA[1:0] = 1 instead
Static High
toggling

11 11*nRC repeat Sub-Loop 0, use BG[1:0]2 = 3, BA[1:0] = 3 instead For x4
and x8
12 12*nRC repeat Sub-Loop 0, use BG[1:0]2 = 2, BA[1:0] = 1 instead only
NOTE:
1 .DQS_t, DQS_c are VDDQ.
2. BG1 is don’t care for x16 device
3. C[2:0] are used only for 3DS device
4. DQ signals are VDDQ.
Rev. 1.2 / Jun.2017 55

Table 4 - IDD1, IDD1A and IPP1 Measurement-Loop Patterna)
A[17,13,11]
RAS_n/A16
CAS_n/A15
CK_t, CK_c
WE_n/A14
A12/BC_n
Command
A[10]/AP
Sub-Loop
BG[1:0]2
Number
BA[1:0]
C[2:0]3
ACT_n
A[9:7]
A[6:3]
A[2:0]
Cycle
CS_n
ODT
CKE
Data4
0 0 ACT 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 -
1, 2 D, D 1 0 0 0
0 0 0 0 0 0 0 0 0 0 0 -
3, 4 D#, D# 1 1 1 1
0 3b 3 0 0 0 7 F 1 0 0 -
... repeat pattern 1...4 until nRCD - AL - 1, truncate if necessary
nRCD -AL RD 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 D0=00, D1=FF
D2=FF, D3=00
D4=FF, D5=00
D6=00, D7=FF
nRAS PRE 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 -
... repeat pattern 1...4 until nRC - 1, truncate if necessary
1 1*nRC + 0 ACT 0 0 0 1 1 0 0 1 1 0 0 0 0 0 0 -
1*nRC + 1, 2 D, D 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -
1*nRC + 3, 4 D#, D# 1 1 1 1 1 0 0 3b 3 0 0 0 7 F 0 -
... repeat pattern nRC + 1...4 until 1*nRC + nRAS - 1, truncate if necessary
1*nRC + nRCD RD 0 1 1 0 1 0 0 1 1 0 0 0 0 0 0 D0=FF, D1=00
- AL D2=00, D3=FF
D4=00, D5=FF
Static High
D6=FF, D7=00
toggling

1*nRC + nRAS PRE 0 1 0 1 0 0 0 1 1 0 0 0 0 0 0 -
... repeat nRC + 1...4 until 2*nRC - 1, truncate if necessary
For x4 and x8 only
NOTE:
1. DQS_t, DQS_c are used according to RD Commands, otherwise VDDQ
4.Burst Sequence driven on each DQ signal by Read Command. Outside burst operation, DQ signals are VDDQ.
Rev. 1.2 / Jun.2017 56

Table 5 - IDD2N, IDD2NA, IDD2NL, IDD2NG, IDD2ND, IDD2N_par, IPP2,IDD3N,
IDD3NA and IDD3P
Measurement-Loop Pattern1
A[17,13,11]
RAS_n/A16
CAS_n/A15
CK_t, CK_c
WE_n/A14
A12/BC_n
Command
A[10]/AP
Sub-Loop
BG[1:0]2
Number
BA[1:0]
C[2:0]3
A[9:7]
A[6:3]
A[2:0]
ACT_n
Cycle
CS_n
ODT
CKE
Data4
0 0 D, D 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1 D, D 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
2 D#, 1 1 1 1 1 0 0 32 3 0 0 0 7 F 0 0
D#
3 D#, 1 1 1 1 1 0 0 32 3 0 0 0 7 F 0 0
D#
1 4-7 repeat Sub-Loop 0, use BG[1:0]2 = 1, BA[1:0] = 1 instead
Static High

toggling

NOTE :
1. DQS_t, DQS_c are VDDQ.
Rev. 1.2 / Jun.2017 57

Table 6 - IDD2NT and IDDQ2NT Measurement-Loop Pattern1
A[17,13,11]
RAS_n/A16
CAS_n/A15
CK_t, CK_c
WE_n/A14
A12/BC_n
Command
A[10]/AP
Sub-Loop
BG[1:0]2
Number
BA[1:0]
C[2:0]3
ACT_n
A[9:7]
A[6:3]
A[2:0]
Cycle
CS_n
ODT
CKE
Data4
0 0 D, D 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -
1 D, D 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -
2 D#, D# 1 1 1 1 1 0 0 32 3 0 0 0 7 F 0 -
3 D#, D# 1 1 1 1 1 0 0 32 3 0 0 0 7 F 0 -
1 4-7 repeat Sub-Loop 0, but ODT = 1 and BG[1:0]2 = 1, BA[1:0] = 1 instead
Static High
toggling

For x4
11 44-47 repeat Sub-Loop 0, but ODT = 1 and BG[1:0]2 = 3, BA[1:0] = 3 instead and x8
12 48-51 repeat Sub-Loop 0, but ODT = 0 and BG[1:0]2 = 2, BA[1:0] = 1 instead only
NOTE :
Rev. 1.2 / Jun.2017 58

Table 7 - IDD4R, IDDR4RA, IDD4RB and IDDQ4R Measurement-Loop Pattern1
A[17,13,11]
RAS_n/A16
CAS_n/A15
CK_t, CK_c
WE_n/A14
A12/BC_n
Command
A[10]/AP
Sub-Loop
BG[1:0]2
Number
BA[1:0]
C[2:0]3
ACT_n
A[9:7]
A[6:3]
A[2:0]
Cycle
CS_n
ODT
CKE
Data4
0 0 RD 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 D0=00, D1=FF
D2=FF, D3=00
D4=FF, D5=00
D6=00, D7=FF
1 D 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -
2,3 D#, D# 1 1 1 1 1 0 0 3 2 3 0 0 0 7 F 0 -
1 4 RD 0 1 1 0 1 0 0 1 1 0 0 0 7 F 0 D0=FF, D1=00
D2=00, D3=FF
D4=00, D5=FF
D6=FF, D7=00
5 D 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -
6,7 D#, D# 1 1 1 1 1 0 0 3 2 3 0 0 0 7 F 0 -
Static High

toggling

For x4 and x8 only
NOTE :
1. DQS_t, DQS_c are used according to RD Commands, otherwise VDDQ.
4. Burst Sequence driven on each DQ signal by Read Command.
Rev. 1.2 / Jun.2017 59

Table 8 - IDD4W, IDD4WA, IDD4WB and IDD4W_par Measurement-Loop Pattern1
A[17,13,11]
RAS_n/A16
CAS_n/A15
CK_t, CK_c
WE_n/A14
A12/BC_n
Command
A[10]/AP
Sub-Loop
BG[1:0]2
Number
BA[1:0]
C[2:0]3
ACT_n
A[9:7]
A[6:3]
A[2:0]
Cycle
CS_n
ODT
CKE
Data4
0 0 WR 0 1 1 0 1 1 0 0 0 0 0 0 0 0 0 D0=00, D1=FF
D2=FF, D3=00
D4=FF, D5=00
D6=00, D7=FF
1 D 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 -
2,3 D#, D# 1 1 1 1 1 1 0 3 2 3 0 0 0 7 F 0 -
1 4 WR 0 1 1 0 1 1 0 1 1 0 0 0 7 F 0 D0=FF, D1=00
D2=00, D3=FF
D4=00, D5=FF
D6=FF, D7=00
5 D 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 -
6,7 D#, D# 1 1 1 1 1 1 0 3 2 3 0 0 0 7 F 0 -
2 8-11 repeat Sub-Loop 0, use BG[1:0] = 0, BA[1:0] = 2 instead 2
Static High

toggling

For x4 and x8 only
NOTE :
1. DQS_t, DQS_c are used according to WR Commands, otherwise VDDQ.
4. Burst Sequence driven on each DQ signal by Write Command.
Rev. 1.2 / Jun.2017 60

Table 9 - IDD4WC Measurement-Loop Pattern1
A[17,13,11]
RAS_n/A16
CAS_n/A15
CK_t, CK_c
WE_n/A14
A12/BC_n
Command
A[10]/AP
Sub-Loop
BG[1:0]b
Number
BA[1:0]
C[2:0]c
ACT_n
A[9:7]
A[6:3]
A[2:0]
Cycle
CS_n
ODT
CKE
Datad
0 0 WR 0 1 1 0 1 1 0 0 0 0 0 0 0 0 0 D0=00, D1=FF
D2=FF, D3=00
D4=FF, D5=00
D6=00, D7=FF
D8=CRC
1,2 D, D 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 -
3,4 D#, D# 1 1 1 1 1 1 0 3 2 3 0 0 0 7 F 0 -
5 WR 0 1 1 0 1 1 0 1 1 0 0 0 7 F 0 D0=FF, D1=00
D2=00, D3=FF
D4=00, D5=FF
D6=FF, D7=00
D8=CRC
6,7 D, D 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 -
8,9 D#, D# 1 1 1 1 1 1 0 32 3 0 0 0 7 F 0 -
Static High
toggling

For x4 and x8 only
NOTE :
2. BG1 is don’t care for x16 device.
3. C[2:0] are used only for 3DS device.
4. Burst Sequence driven on each DQ signal by Write Command.
Rev. 1.2 / Jun.2017 61

Table 10 - IDD5B Measurement-Loop Pattern1
A[17,13,11]
RAS_n/A16
CAS_n/A15
CK_t, CK_c
WE_n/A14
A12/BC_n
Command
A[10]/AP
Sub-Loop
BG[1:0]2
Number
BA[1:0]
C[2:0]3
ACT_n
A[9:7]
A[6:3]
A[2:0]
Cycle
CS_n
ODT
CKE
Data4
0 0 REF 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -
1 1 D 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -
2 D 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -
3 D#, D# 1 1 1 1 1 0 0 32 3 0 0 0 7 F 0 -
4 D#, D# 1 1 1 1 1 0 0 32 3 0 0 0 7 F 0 -
4-7 repeat pattern 1...4, use BG[1:0]2 = 1, BA[1:0] = 1 instead
Static High
toggling

For x4 and x8
44-47 repeat pattern 1...4, use BG[1:0]2 = 3, BA[1:0] = 3 instead only
2 64 ... nRFC - 1 repeat Sub-Loop 1, Truncate, if necessary
NOTE :
Rev. 1.2 / Jun.2017 62

Table 11 - IDD7 Measurement-Loop Pattern1
A[17,13,11]
RAS_n/A16
CAS_n/A15
CK_t, CK_c
WE_n/A14
A12/BC_n
Command
A[10]/AP
Sub-Loop
BG[1:0]2
Number
BA[1:0]
C[2:0]3
ACT_n
A[9:7]
A[6:3]
A[2:0]
Cycle
CS_n
ODT
CKE
Data4
0 0 ACT 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0
1 RDA 0 1 1 0 1 0 0
0 D0=00, D1=FF 0 0 0 1 0 0
D2=FF, D3=00
D4=FF, D5=00
D6=00, D7=FF
2 D 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -
3 D# 1 1 1 1 1 0 0 32 3 0 0 0 7 F 0 -
... repeat pattern 2...3 until nRRD - 1, if nRRD > 4. Truncate if necessary
1 nRRD ACT 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 -
nRRD + 1 RDA 0 1 1 0 1 0 1 1 0 0 1 0 0 0 D0=FF, D1=00
D2=00, D3=FF
D4=00, D5=FF
D6=FF, D7=00
... repeat pattern 2 ... 3 until 2*nRRD - 1, if nRRD > 4. Truncate if necessary
2 2*nRRD repeat Sub-Loop 0, use BG[1:0]2 = 0, BA[1:0] = 2 instead
3 3*nRRD repeat Sub-Loop 1, use BG[1:0]2 = 1, BA[1:0] = 3 instead
4 4*nRRD repeat pattern 2 ... 3 until nFAW - 1, if nFAW > 4*nRRD. Truncate if necessary
Static High
5 nFAW BG[1:0]2 = 0, BA[1:0] = 1

toggling
repeat Sub-Loop 0, use instead

6 nFAW + nRRD repeat Sub-Loop 1, use BG[1:0]2 = 1, BA[1:0] = 2 instead
7 nFAW + 2*nRRD repeat Sub-Loop 0, use BG[1:0]2 = 0, BA[1:0] = 3 instead
8 nFAW + 3*nRRD repeat Sub-Loop 1, use BG[1:0]2 = 1, BA[1:0] = 0 instead
9 nFAW + 4*nRRD repeat Sub-Loop 4
10 2*nFAW repeat Sub-Loop 0, use BG[1:0]2 = 2, BA[1:0] = 0 instead

11 2*nFAW + nRRD repeat Sub-Loop 1, use BG[1:0]2 = 3, BA[1:0] = 1 instead
12 2*nFAW + 2*nRRD repeat Sub-Loop 0, use BG[1:0]2 = 2, BA[1:0] = 2 instead
14 2*nFAW + 4*nRRD repeat Sub-Loop 4
For x4 and x8
15 3*nFAW repeat Sub-Loop 0, use BG[1:0]2 = 2, BA[1:0] = 1 instead only
16 3*nFAW + nRRD repeat Sub-Loop 1, use BG[1:0]2 = 3, BA[1:0] = 2 instead
19 3*nFAW + 4*nRRD repeat Sub-Loop 4
20 4*nFAW repeat pattern 2 ... 3 until nRC - 1, if nRC > 4*nFAW. Truncate if necessary
NOTE :
4. Burst Sequence driven on each DQ signal by Read Command. Outside burst operation, DQ signals are VDDQ
Rev. 1.2 / Jun.2017 63

IDD Specifications (Tcase: 0 to 95oC)
4GB, 512Mx 64 U-DIMM: HMA851U6AFR6N
IDD IPP
unit note unit note
Symbol 2133 2400 Symbol 2133 2400
IDD0 176 184 mA IPP0 40 40 mA
IDD0A 176 184 mA IPP1 40 40 mA
IDD1 228 240 mA IPP2N 13 13 mA
IDD1A 240 252 mA IPP2P 13 13 mA
IDD2N 104 108 mA IPP3N 72 72 mA
IDD2NA 104 108 mA IPP3P 72 72 mA
IDD2NT 124 128 mA IPP4R 72 72 mA
IDD2NL 72 72 mA IPP4W 72 72 mA
IDD2NG 104 104 mA IPP5B 260 260 mA
IDD2ND 104 104 mA IPP5F2 180 184 mA
IDD2NP 104 104 mA IPP5F4 160 160 mA
IDD2P 72 72 mA IPP6N 16 16 mA
IDD2Q 88 88 mA IPP6E 28 28 mA
IDD3N 176 180 mA IPP6R 16 16 mA
IDD3NA 176 180 mA IPP6A 28 28 mA
IDD3P 144 148 mA IPP7 96 96 mA
IDD4R 708 780 mA IPP8 13 13 mA
IDD4RA 748 816 mA
IDD4RB 736 816 mA
IDD4W 616 680 mA
IDD4WA 628 688 mA
IDD4WB 616 680 mA
IDD4WC 592 656 mA
IDD4WP 656 744 mA
IDD5B 780 784 mA
IDD5F2 560 568 mA
IDD5F4 492 508 mA
IDD6N 88 88 mA
IDD6E 112 112 mA
IDD6R 56 56 mA
IDD6A 112 112 mA
IDD7 724 740 mA
IDD8 48 48 mA
Rev. 1.3 / Jun.2017 64

8GB, 1Gx 64 U-DIMM: HMA81GU6AFR8N
IDD IPP
unit note unit note
Symbol 2133 2400 Symbol 2133 2400
IDD0 296 304 mA IPP0 48 48 mA
IDD0A 296 304 mA IPP1 56 56 mA
IDD1 368 384 mA IPP2N 26 26 mA
IDD1A 392 408 mA IPP2P 26 26 mA
IDD2N 208 216 mA IPP3N 120 120 mA
IDD2NA 208 216 mA IPP3P 120 120 mA
IDD2NT 248 256 mA IPP4R 120 120 mA
IDD2NL 144 144 mA IPP4W 120 120 mA
IDD2NG 208 208 mA IPP5B 520 520 mA
IDD2ND 208 208 mA IPP5F2 360 368 mA
IDD2NP 208 208 mA IPP5F4 320 320 mA
IDD2P 144 144 mA IPP6N 32 32 mA
IDD2Q 176 176 mA IPP6E 56 56 mA
IDD3N 352 360 mA IPP6R 33 33 mA
IDD3P 288 296 mA IPP7 152 152 mA
IDD4R 920 992 mA IPP8 26 26 mA
IDD4RA 992 1072 mA
IDD4RB 992 1072 mA
IDD4W 888 960 mA
IDD4WA 912 984 mA
IDD4WB 880 960 mA
IDD4WC 848 912 mA
IDD4WP 904 1088 mA
IDD5B 1560 1568 mA
IDD5F2 1120 1136 mA
IDD5F4 984 1016 mA
IDD6N 176 176 mA
IDD6E 224 224 mA
IDD6R 112 112 mA
IDD6A 224 224 mA
IDD7 1160 1216 mA
IDD8 96 96 mA
Rev. 1.3 / Jun.2017 65

IDD IPP
unit note unit note
Symbol 2133 2400 Symbol 2133 2400
IDD0 333 342 mA IPP0 54 54 mA
IDD0A 333 342 mA IPP1 63 63 mA
IDD1 411 432 mA IPP2N 29 29 mA
IDD1A 441 459 mA IPP2P 29 29 mA
IDD2N 234 243 mA IPP3N 135 135 mA
IDD2NA 234 243 mA IPP3P 135 135 mA
IDD2NT 279 288 mA IPP4R 135 135 mA
IDD2NL 162 162 mA IPP4W 135 135 mA
IDD2NG 234 234 mA IPP5B 585 585 mA
IDD2ND 234 234 mA IPP5F2 405 414 mA
IDD2NP 234 234 mA IPP5F4 360 360 mA
IDD2P 162 162 mA IPP6N 36 36 mA
IDD2Q 198 198 mA IPP6E 63 63 mA
IDD3N 396 405 mA IPP6R 37 37 mA
IDD3P 324 333 mA IPP7 171 171 mA
IDD4R 1035 1116 mA IPP8 29 29 mA
IDD4RA 1116 1206 mA
IDD4RB 1116 1206 mA
IDD4W 999 1080 mA
IDD4WA 1026 1107 mA
IDD4WB 990 1080 mA
IDD4WC 954 1026 mA
IDD4WP 1017 1224 mA
IDD5B 1755 1764 mA
IDD5F2 1260 1278 mA
IDD5F4 1107 1143 mA
IDD6N 198 198 mA
IDD6E 252 252 mA
IDD6R 126 126 mA
IDD6A 252 252 mA
IDD7 1305 1368 mA
IDD8 108 108 mA
Rev. 1.3 / Jun.2017 66

IDD IPP
unit note unit note
Symbol 2133 2400 Symbol 2133 2400
IDD0 504 520 mA IPP0 74 74 mA
IDD0A 504 520 mA IPP1 82 82 mA
IDD1 576 600 mA IPP2N 51 51 mA
IDD1A 600 624 mA IPP2P 51 51 mA
IDD2N 416 432 mA IPP3N 240 240 mA
IDD2NA 416 432 mA IPP3P 240 240 mA
IDD2NT 496 512 mA IPP4R 146 146 mA
IDD2NL 288 288 mA IPP4W 146 146 mA
IDD2NG 416 416 mA IPP5B 546 546 mA
IDD2ND 416 416 mA IPP5F2 386 394 mA
IDD2NP 416 416 mA IPP5F4 346 346 mA
IDD2P 288 288 mA IPP6N 64 64 mA
IDD2Q 352 352 mA IPP6E 112 112 mA
IDD3N 704 720 mA IPP6R 66 66 mA
IDD3NA 704 720 mA IPP6A 112 112 mA
IDD3P 576 592 mA IPP7 178 178 mA
IDD4R 1128 1208 mA IPP8 51 51 mA
IDD4RA 1200 1288 mA
IDD4RB 1200 1288 mA
IDD4W 1096 1176 mA
IDD4WA 1120 1200 mA
IDD4WB 1088 1176 mA
IDD4WC 1056 1128 mA
IDD4WP 1112 1304 mA
IDD5B 1768 1784 mA
IDD5F2 1328 1352 mA
IDD5F4 1192 1232 mA
IDD6N 352 352 mA
IDD6E 448 448 mA
IDD6R 224 224 mA
IDD6A 448 448 mA
IDD7 1368 1432 mA
IDD8 192 192 mA
Rev. 1.3 / Jun.2017 67

IDD IPP
unit note unit note
Symbol 2133 2400 Symbol 2133 2400
IDD0 567 585 mA IPP0 83 83 mA
IDD0A 567 585 mA IPP1 92 92 mA
IDD1 648 675 mA IPP2N 58 58 mA
IDD1A 675 702 mA IPP2P 58 58 mA
IDD2N 468 486 mA IPP3N 270 270 mA
IDD2NA 468 486 mA IPP3P 270 270 mA
IDD2NT 558 576 mA IPP4R 164 164 mA
IDD2NL 324 324 mA IPP4W 164 164 mA
IDD2NG 468 468 mA IPP5B 614 614 mA
IDD2ND 468 468 mA IPP5F2 434 443 mA
IDD2NP 468 468 mA IPP5F4 389 389 mA
IDD2P 324 324 mA IPP6N 72 72 mA
IDD2Q 396 396 mA IPP6E 126 126 mA
IDD3N 792 810 mA IPP6R 74 74 mA
IDD3NA 792 810 mA IPP6A 126 126 mA
IDD3P 648 666 mA IPP7 200 200 mA
IDD4R 1269 1359 mA IPP8 58 58 mA
IDD4RA 1350 1449 mA
IDD4RB 1350 1449 mA
IDD4W 1233 1323 mA
IDD4WA 1260 1350 mA
IDD4WB 1224 1323 mA
IDD4WC 1188 1269 mA
IDD4WP 1251 1467 mA
IDD5B 1989 2007 mA
IDD5F2 1494 1521 mA
IDD5F4 1341 1386 mA
IDD6N 396 396 mA
IDD6E 504 504 mA
IDD6R 252 252 mA
IDD6A 504 504 mA
IDD7 1539 1611 mA
IDD8 216 216 mA
Rev. 1.3 / Jun.2017 68

Module Dimensions
512Mx64 - HMA851U6AFR6N
Front
133.35
129.55
2.10
30.75
3.00 SPD
11.00
17.10
14.10
Detail A Detail B Detail D Detail E Detail C Detail F
2.70±0.15
8.00
Pin 1 Pin 35 Pin 47 Pin 105 Pin 117
3.35
64.60 56.10
Back
31.25±0.15
2x R0.60 Max
Side
Detail of Contacts A, F Detail of Contacts B Detail of Contacts C
0.60± 0.03 Pin 35 Pin 47 Pin 105 Pin 117 3.18mm max
2.10
2.10
2.60
2.60
Max 0.30
2.10
9.35 9.35
10.20 10.20
Non-matarized keep out area

0.85 Detail of Contacts D Detail of Contacts E
Max 0.25 Max 0.35
0.60± 0.03
4.30
3.85±0.1
0.2 ±0.15
Max 0.30 1.40±0.1mm

max
0.20 ±0.15
0.85
Max 0.25 Max 0.35 1.50 ±0.05
5.95
Note:
1.  0.13 tolerance on all dimensions unless otherwise stated.
Units: millimeters
Rev. 1.3 / Jun.2017 69

1Gx64 - HMA81GU6AFR8N
Front
133.35
129.55
2.10
SPD
30.75
3.00
11.00
17.10
14.10
2.70±0.15
8.00
3.35
64.60 56.10
Back
31.25±0.15
2x R0.60 Max
Side
2.10
2.10
2.60
2.60
Max 0.30
2.10
9.35 9.35
10.20 10.20

Max 0.25 Max 0.35
0.60± 0.03
4.30
3.85±0.1
0.2 ±0.15
Max 0.30 1.40±0.1mm

max
0.20 ±0.15
0.85
Max 0.25 Max 0.35 1.50 ±0.05
5.95
Note:
Units: millimeters
Rev. 1.3 / Jun.2017 70

Front
133.35
129.55
2.10
30.75
3.00
11.00
17.10
14.10
2.70±0.15
8.00
3.35
64.60 56.10
Back
31.25±0.15
SPD/TS
2x R0.60 Max
Side
2.10
2.10
2.60
2.60
Max 0.30
2.10
9.35 9.35
10.20 10.20

Max 0.25 Max 0.35
0.60± 0.03
4.30
3.85±0.1
0.2 ±0.15
Max 0.30 1.40±0.1mm

max
0.20 ±0.15
0.85
Max 0.25 Max 0.35 1.50 ±0.05
5.95
Note:
Units: millimeters
Rev. 1.3 / Jun.2017 71

Front
133.35
129.55
2.10
30.75
3.00
SPD
11.00
17.10
14.10
2.70±0.15
8.00
3.35
64.60 56.10
Back
31.25±0.15
2x R0.60 Max
Side
2.10
2.10
2.60
2.60
Max 0.30
2.10
9.35 9.35
10.20 10.20

Max 0.25 Max 0.35
0.60± 0.03
4.30
3.85±0.1
0.2 ±0.15
Max 0.30 1.40±0.1mm

max
0.20 ±0.15
0.85
Max 0.25 Max 0.35 1.50 ±0.05
5.95
Note:
Units: millimeters
Rev. 1.3 / Jun.2017 72

Front
133.35
129.55
2.10
30.75
3.00 SPD/TS
11.00
17.10
14.10
2.70±0.15
8.00
3.35
64.60 56.10
Back
31.25±0.15
2x R0.60 Max
Side
2.10
2.10
2.60
2.60
Max 0.30
2.10
9.35 9.35
10.20 10.20

Max 0.25 Max 0.35
0.60± 0.03
4.30
3.85±0.1
0.2 ±0.15
Max 0.30 1.40±0.1mm

max
0.20 ±0.15
0.85
Max 0.25 Max 0.35 1.50 ±0.05
5.95
Note:
Units: millimeters
Rev. 1.3 / Jun.2017 73

Computing Ds 8Gb DDR4 (A-Ver) Based UDIMMs (Rev.1.3) PDF

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Computing Ds 8Gb DDR4 (A-Ver) Based UDIMMs (Rev.1.3) PDF

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288pin DDR4 SDRAM Unbuffered DIMM

DDR4 SDRAM Unbuffered DIMM

Rev. 1.3 / Jun.2017 1

Revision No. History Draft Date Remark

0.1 Initial Release Dec.2015

0.2 Updated 2133Mbps (tCK(min) : 0.938ns->0.937ns) Mar.2016

1.0 Added Development plan (ECC 1Rx8/2Rx8) Apr.2016

1.1 Updated IPP Specification (1Rx8/2Rx8) Apr.2016

1.2 Updated IDD Specification (2133Mbps) Jun.2016

1.3 Corrected Block Diagram / Module Dimension Jun.2017

Rev. 1.3 / Jun.2017 2

• Power Supply: VDD=1.2V (1.14V to 1.26V)

HMA851U6AFR6N-TF/UH 4GB 512Mx64 512Mx16(H5AN8G6NAFR)*4 1

HMA81GU6AFR8N-TF/UH 8GB 1Gx64 1Gx8(H5AN8G8NAFR)*8 1

HMA81GU7AFR8N-TF/UH 8GB 1Gx72 1Gx8(H5AN8G8NAFR)*9 1

HMA82GU6AFR8N-TF/UH 16GB 2Gx64 1Gx8(H5AN8G8NAFR)*16 2

HMA82GU7AFR8N-TF/UH 16GB 2Gx72 1Gx8(H5AN8G8NAFR)*18 2

Rev. 1.3 / Jun.2017 3

4GB(1Rx16) 8GB(1Rx8) 16GB(2Rx8)

Bank Address BG Address BG0 BG0~BG1 BG0~BG1

Bank Address in a BG BA0~BA1 BA0~BA1 BA0~BA1

Row Address A0~A15 A0~A15 A0~A15

Column Address A0~ A9 A0~ A9 A0~ A9

Page size 2KB 1 KB 1 KB

Rev. 1.3 / Jun.2017 4

RAS_n2 SDRAM row address strobe PARITY SDRAM parity input

WE_n4 SDRAM write enable C0, C1, C2 Chip ID lines

Rev. 1.3 / Jun.2017 5

Symbol Type Function

Rev. 1.3 / Jun.2017 6

Rev. 1.3 / Jun.2017 7

Rev. 1.3 / Jun.2017 8

Rev. 1.3 / Jun.2017 9

Rev. 1.3 / Jun.2017 10

DQS1_t DQU_t DQS3_t DQU_t

DQS5_t DQU_t DQS7_t DQU_t

Rev. 1.3 / Jun.2017 11

VDD D0–D7 SA0 SA1 SA2

Rev. 1.3 / Jun.2017 12

Rev. 1.3 / Jun.2017 13

CK0_t, CK0_c CK1_t, CK1_c

Rev. 1.3 / Jun.2017 14

CK0_t, CK0_c CK1_t, CK1_c

VDD D0–D15 SA0 SA1 SA2

Rev. 1.3 / Jun.2017 15

ZQ VSS ZQ VSS ZQ VSS

ZQ VSS ZQ VSS ZQ VSS

ZQ VSS ZQ VSS ZQ VSS

DQS2_t DQS_t D2 DQS_t

ZQ VSS ZQ VSS ZQ VSS

DQS3_t DQS_t D3 DQS_t

Rev. 1.3 / Jun.2017 16

DRAM Component Operating Temperature Range

Symbol Parameter Rating Units Notes

Rev. 1.2 / Jun.2017 17

Rev. 1.2 / Jun.2017 18

Rev. 1.3 / Jun.2017 19

Illustration of VREF(DC) tolerance and VREF AC-noise limits

"VREF" shall be understood as VREF(DC), as defined in Figure above.