H5an8g6nafr VKC

8Gb DDR4 SDRAM
8Gb DDR4 SDRAM

Lead-Free&Halogen-Free
(RoHS Compliant)
H5AN8G4NAFR-xxC
H5AN8G8NAFR-xxC
H5AN8G6NAFR-xxC
* SK hynix reserves the right to change products or specifications without notice.
Rev. 1.2 / Jul.2017 1

Revision History
Revision No. History Draft Date Remark
0.01 Initial Release Oct. 2015 Priliminary
0.1 Updated JEDEC Specification Dec.2015

Changed Ordering Frequency
Changed Speed Bin : 2666Mbps CL19(VK)
1.0 Updated 2133Mbps (tCK(min) : 0.938ns->0.937ns) Apr.2016

Updated IDD Specification
1.1 Updated IDD Specification (2133/2666Mbps) Jun.2016
1.2 Collected typo Jun.2017
Rev. 1.2 / Jul.2017 2

Description
The H5AN8G4NAFR-xxC, H5AN8G8NAFR-xxC and H5AN8G6NAFR-xxC are a 8Gb CMOS Double Data Rate
IV (DDR4) Synchronous DRAM, ideally suited for the main memory applications which requires large mem-
ory density and high bandwidth. SK hynix 8Gb DDR4 SDRAMs offer fully synchronous operations refer-
enced to both rising and falling edges of the clock. While all addresses and control inputs are latched on
the rising edges of the CK (falling edges of the CK), Data, Data strobes and Write data masks inputs are
sampled on both rising and falling edges of it. The data paths are internally pipelined and 8-bit prefetched
to achieve very high bandwidth.
Device Features and Ordering Information
FEATURES
• VDD=VDDQ=1.2V +/- 0.06V • Two Termination States such as RTT_PARK and
• Fully differential clock inputs (CK, CK) operation RTT_NOM switchable by ODT pin
• Differential Data Strobe (DQS, DQS) • Asynchronous RESET pin supported
• On chip DLL align DQ, DQS and DQS transition with CK  • ZQ calibration supported
transition • TDQS (Termination Data Strobe) supported (x8 only)
• DM masks write data-in at the both rising and falling  • Write Levelization supported
edges of the data strobe • 8 bit pre-fetch
• All addresses and control inputs except data, data • This product in compliance with the RoHS directive.
strobes and data masks latched on the rising edges of
the clock • Internal Vref DQ level generation is available
• Programmable CAS latency 9, 10, 11, 12, 13, 14, 15, • Write CRC is supported at all speed grades
16, 17, 18, 19 and 20 supported • Maximum Power Saving Mode is supported
• Programmable additive latency 0, CL-1, and CL-2  • TCAR(Temperature Controlled Auto Refresh) mode is
supported (x4/x8 only) supported
• Programmable CAS Write latency (CWL) = 9, 10, 11, • LP ASR(Low Power Auto Self Refresh) mode is sup-
12, 14, 16, 18 ported
• Programmable burst length 4/8 with both nibble  • Fine Granularity Refresh is supported
sequential and interleave mode
• Per DRAM Addressability is supported
• BL switch on the fly
• Geardown Mode(1/2 rate, 1/4 rate) is supported
• 16banks
• Programable Preamble for read and write is supported
• Average Refresh Cycle (Tcase of 0 oC~ 95 oC) • Self Refresh Abort is supported
- 7.8 µs at 0oC ~ 85 oC • CA parity (Command/Address Parity) mode is sup-
- 3.9 µs at 85oC ~ 95 oC ported
• JEDEC standard 78ball FBGA(x4/x8), 96ball FBGA(x16) • Bank Grouping is applied, and CAS to CAS latency
• Driver strength selected by MRS (tCCD_L, tCCD_S) for the banks in the same or different
bank group accesses are available
• Dynamic On Die Termination supported
• DBI(Data Bus Inversion) is supported(x8)
Rev. 1.2 / Jul.2017 3

ORDERING INFORMATION
Part No. Configuration Package
H5AN8G4NAFR-*xxc 2G x 4
78ball FBGA
H5AN8G8NAFR-*xxC 1G x 8
H5AN8G6NAFR-*xxC 512M x 16 96ball FBGA
* xx means Speed Bin Grade
OPERATING FREQUENCY
CAS
tCK tRCD tRP tRAS tRC
MT/s Grade Latency CL-tRCD-tRP
(ns) (ns) (ns) (ns) (ns)
(tCK)
13.75 13.75 48.75
DDR4-1600 -PB 1.25 11 35 11-11-11
(13.50)* (13.50)* (48.50)*
13.92 13.92 47.92
DDR4-1866 -RD 1.071 13 34 13-13-13
(13.50)* (13.50)* (47.50)*
14.06 14.06 47.06
DDR4-2133 -TF 0.937 15 33 15-15-15
(13.50)* (13.50)* (46.50)*
14.16 14.16 46.16
DDR4-2400 -UH 0.833 17 32 17-17-17
(13.75)* (13.75)* (45.75)*
14.25 14.25 46.25
DDR4-2666 -VK 0.75 19 32 19-19-19
(13.75)* (13.75)* (45.75)*
*SK hynix DRAM devices support optional downbinning to CL17, CL15, CL13 and CL11. SPD setting is programmed to match.
Rev. 1.2 / Jul.2017 4

Package Ballout/Mechanical Dimension
x4 Package Ball out (Top view): 78ball FBGA Package
1 2 3 4 5 6 7 8 9
A VDD VSSQ NC DM_n, DBI_n VSSQ VSS A

B VPP VDDQ DQS_c DQ1 VDDQ ZQ B
C VDDQ DQ0 DQS_t VDD VSS VDDQ C
D VSSQ NC DQ2 DQ3 NC VSSQ D
E VSS VDDQ NC NC VDDQ VSS E
F VDD NC ODT CK_t CK_c VDD F
G VSS NC CKE CS_n NC TEN G
WE_n CAS_n RAS_n
H VDD ACT_n VSS H
A14 A15 A16
A10 A12
J VREFCA BG0 BG1 VDD J
AP BC_n
K VSS BA0 A4 A3 BA1 VSS K
L RESET_n A6 A0 A1 A5 ALERT_n L
M VDD A8 A2 A9 A7 VPP M
N VSS A11 PAR NC A13 VDD N
1 2 3 4 5 6 7 8 9
Rev. 1.2 / Jul.2017 5

1 2 3 4 5 6 7 8 9
DM_n/DBI_n
A VDD VSSQ TDQS_c VSSQ VSS A
TDQS_t
B VPP VDDQ DQS_c DQ1 VDDQ ZQ B
C VDDQ DQ0 DQS_t VDD VSS VDDQ C
D VSSQ DQ4 DQ2 DQ3 DQ5 VSSQ D
E VSS VDDQ DQ6 DQ7 VDDQ VSS E
F VDD NC ODT CK_t CK_c VDD F
G VSS NC CKE CS_n NC TEN G
WE_n CAS_n RAS_n
H VDD ACT_n VSS H
A14 A15 A16
A10 A12
J VREFCA BG0 BG1 VDD J
AP BC_n
K VSS BA0 A4 A3 BA1 VSS K
L RESET_n A6 A0 A1 A5 ALERT_n L
M VDD A8 A2 A9 A7 VPP M
N VSS A11 PAR NC A13 VDD N
1 2 3 4 5 6 7 8 9
Rev. 1.2 / Jul.2017 6

1 2 3 4 5 6 7 8 9
A VDDQ VSSQ DQU0 DQSU_c VSSQ VDDQ A

B VPP VSS VDD DQSU_t DQU1 VDD B
C VDDQ DQU4 DQU2 DQU3 DQU5 VSSQ C
D VDD VSSQ DQU6 DQU7 VSSQ VDDQ D
DMU_n/ DML_n/
E VSS VSSQ VSSQ VSS E
DBIU_n DBIL_n
F VSSQ VDDQ DQSL_c DQL1 VDDQ ZQ F
G VDDQ DQL0 DQSL_t VDD VSS VDDQ G
H VSSQ DQL4 DQL2 DQL3 DQL5 VSSQ H
J VDD VDDQ DQL6 DQL7 VDDQ VDD J
K VSS CKE ODT CK_t CK_c VSS K
WE_n RAS_n
L VDD ACT_n CS_n VDD L
A14 A16
A12 CAS_n
M VREFCA BG0 A10/AP VSS M
BC_n A15
N VSS BA0 A4 A3 BA1 TEN N
P RESET_n A6 A0 A1 A5 ALERT_n P
R VDD A8 A2 A9 A7 VPP R
T VSS A11 PAR NC A13 VDD T
1 2 3 4 5 6 7 8 9
Rev. 1.2 / Jul.2017 7

Pin Functional Description
Symbol Type Function
Clock: CK_t and CK_c are differential clock inputs. All address and control input signals
CK_t, CK_c Input
are sampled on the crossing of the positive edge of CK_t and negative edge of CK_c.
Clock Enable: CKE HIGH activates, and CKE Low deactivates, internal clock signals and
device input buffers and output drivers. Taking CKE Low provides Precharge Power-
Down and Self-Refresh operation (all banks idle), or Active Power-Down (row Active in
any bank). CKE is asynchronous for Self-Refresh exit. After VREFCA and VREFDQ have
CKE, (CKE1) Input
become stable during the power on and initialization sequence, they must be maintained
during all operations (including Self-Refresh). CKE must be maintained high throughout
read and write accesses. Input buffers, excluding CK, CK_c, ODT and CKE, are disabled
during power-down. Input buffers, excluding CKE, are disabled during Self-Refresh.
Chip Select: All commands are masked when CS_n is registered HIGH. CS_n provides for
CS_n, (CS1_n) Input external Rank selection on systems with multiple Ranks. CS_n is considered part of the
command code.
Chip ID: Chip ID is only used for 3DS for 2,4,8high stack via TSV to select each slice of
C0,C1,C2 Input
stacked compnent. Chip ID is considered part of the command code.
On Die Termination: ODT (registered HIGH) enables termination resistance internal to
the DDR4 SDRAM. When enabled, ODT is only applied to each DQ, DQS_t, DQS_c and
DM_n/DBI_n/TDQS_t,NU/TDQS_c (When TDQS is enabled via Mode Register A11=1 in
ODT, (ODT1) Input
MR1) signal for x8 configurations. For x16 configuration ODT is applied to each DQ,
DQSU_c, DQSU_t, DQSL_t, DQSL_c, DMU_n, and DML_n signal. The ODT pin will be
ignored if MR1 is programmed to disable RTT_NOM.
Activation Command Input: ACT_n defines the Activation command being entered along
ACT_n Input with CS_n. The input into RAS_n/A16, CAS_n/A15 and WE_n/A14 will be considered as
Row Address A16, A15 and A14.
Command Inputs RAS_n/A16, CAS_n/A15 and WE_n/A14 (along with CS_n) define the
RAS_n/A16, command being entered. Those pins have multi function. For example, for activation
CAS_n/A15, Input with ACT_n Low, those are Addressing like A16,A15 and A14 but for non-activation com-
WE_n/A14 mand with ACT_n High, those are Command pins for Read, Write and other command
defined in command truth table.
Input Data Mask and Data Bus Inversion: DM_n is an input mask signal for write data.
DM_n/DBI_n/ Input data is masked when DM_n is sampled LOW coincident with that input data during
TDQS_t, a Write access. DM_n is sampled on both edges of DQS. DM is muxed with DBI function
Input/ by Mode Register A10,A11,A12 setting in MR5. For x8 device, the function of DM or
(DMU_n/DBI- Output TDQS is enabled by Mode Register A11 setting in MR1. DBI_n is an input/output identif-
U_n), (DML_n/ ing wherther to store/output the true or inverted data. If DBI_n is LOW, the data will be
DBIL_n) stored/output after inversion inside the DDR4 SDRAM and not inverted if DBI_n is HIGH.
TDQS is only supported in x8.
Bank Group Inputs: BG0 - BG1 define to which bank group an Active, Read, Write or Pre-
BG0 - BG1 Input charge command is being applied. BG0 also detemines which mode register is to be
accessed during a MRS cycle. x4/8 have BG0 and BG1 but x16 has only BG0.
Bank Address Inputs: BA0 - BA1 define to which bank an Active, Read, Write or Pre-
BA0 - BA1 Input charge command is being applied. Bank address also determines if the mode register or
extended mode register is to be accessed during a MRS cycle.
Rev. 1.2 / Jul.2017 8

Address Inputs: Provied the row address for ACTIVATE Commands and the column
address for Read/Write commands th select one location out of the memory array in the
A0 - A17 Input respective bank. (A10/AP, A12/BC_n, RAS_n/A16, CAS_n/A15 and WE_n/A14 have addi-
tional functions, see other rows. The address inputs also provide the op-code during
Mode Register Set commands. A17 is only defined for the x4 configration.
Auto-precharge: A10 is sampled during Read/Write commands to determine whether
Autoprecharge should be performed to the accessed bank after the Read/Write opera-
tion. (HIGH: Autoprecharge; LOW: no Autoprecharge).A10 is sampled during a Pre-
A10 / AP Input
charge command to determine whether the Precharge applies to one bank (A10 LOW) or
all banks (A10 HIGH). If only one bank is to be precharged, the bank is selected by bank
addresses.
Burst Chop: A12 / BC_n is sampled during Read and Write commands to determine if
A12 / BC_n Input burst chop (on-the-fly) will be performed. (HIGH, no burst chop; LOW: burst chopped).
See command truth table for details.
Active Low Asynchronous Reset: Reset is active whenRESET_n is LOW, and inactive
RESET_n Input when RESET_n is HIGH. RESET_n must be HIGH during normal operation. RESET_n is a
CMOS rail to rail signal with DC high and low at 80% and 20% of VDD.
Data Input/ Output: Bi-directional data bus. If CRC is enabled via Mode register then
CRC code is added at the end of Data Burst. Any DQ from DQ0~DQ3 may indicate the
Input /
DQ internal Vref level during test via Mode Register Setting MR4 A4=High. During this
Output
mode, RTT value should be set to Hi-Z. Refer to vendor specific datasheets to determine
which DQ is used.
Data Strobe: output with read data, input with write data. Edge-aligned with read data,
centered in write data. For x16, DQSL corresponds to the data on DQL0-DQL7; DQSU
DQS_t, DQS_c,
Input / corresponds to the data on DQU0-DQU7. The data strobe DQS_t, DQSL_t, and DQSU_t
DQSU_t, DQSU_c,
Output are paired with differential signals DQS_c, DQSL_c, and DQSU_c, respectively, to provide
DQSL_t, DQSL_c
differential pair signaling to the system during reads and writes. DDR4 SDRAM supports
differential data strobe only and does not support single-ended.
Termination Data Strobe: TDQS_t/TDQS_c is applicable for x8 DRAMs only. When
enabled via Mode Register A11 = 1 in MR1, the DRAM will enable the same termination
resistance function on TDQS_t/TDQS_c that is applied to DQS_t/DQS_c. When disabled
TDQS_t, TDQS_c Output
via mode register A11 = 0 in MR1, DM/DBI/TDQS will provide the data mask function or
Data Bus Inversion depending on MR5; A11, 12, 10 and TDQS_c is not used. x4/x16
DRAMs must disable the TDQS function via mode register A11 = 0 in MR1.
Command and Address Parity Input : DDR4 Supports Even Parity check in DRAM with
MR setting. Once it’s enabled via Register in MR5, then DRAM calculates Parity with
PAR Input ACT_n, RAS_n/A16, CAS_n/A15, WE_n/A14, BG0-BG1, BA0-BA1, A17-A,0 and C0-
C2(3DS devices). Input parity should maintain at the rising edge of the clock and at the
same time with command & address with CS_n LOW.
Alert: It has multi functions such as CRC error flag, Command and Address Parity error
flag as Output signal. If there is error in CRC, then Alert_n goes LOW for the period time
interval and goes back HIGH. If there is error in Command Address Parity Check, then
ALERT_n Output Alert_n goes LOW for relatively long period until on going DRAM internal recovery trans-
action to complete. During Connectivity Test mode, this pin works as input. Using this
signal or not is dependent on system. In case of not connected as Signal, ALERT_n Pin
must be bounded to VDD on board.
Rev. 1.2 / Jul.2017 9

Connectivity Test Mode Enable: Required on x16 devices and optional input on x4/x8
with densities equal to or greater than 8Gb. HIGH in this pin will enable Connectivity Test
TEN Input Mode operation along with other pins. It is a CMOS rail to rail signal with AC high and
low at 80% and 20% of VDD. Using this signal or not is dependent on System. This pin
may be DRAM internally pulled low through a weak pull-down resistor to VSS.
NC No Connect: No internal electrical connection is present.
VDDQ Supply DQ Power Supply: 1.2 V +/- 0.06 V
VSSQ Supply DQ Ground
VDD Supply Power Supply: 1.2 V +/- 0.06 V
VSS Supply Ground
Vpp Supply DRAM Activation Power Supply: 2.5V (2.375V min , 2.75 max)
VREFCA Supply Reference voltage for CA
ZQ Supply Reference Pin for ZQ calibration
Note:
Input only pins (BG0-BG-1, BA0-BA1, A0-A17, ACT_n, RAS_n,/A16, CAS_n/A15, WE_n/A14, CS_n, CKE, ODT, and
RESET_n) do not supply termination.
Rev. 1.2 / Jul.2017 10

ROW AND COLUMN ADDRESS TABLE
8Gb
Configuration 2Gb x 4 1Gb x 8 512Mb x 16
# of Bank Groups 4 4 2
Bank Address BG Address BG0~BG1 BG0~BG1 BG0
Bank Address in a BG BA0~BA1 BA0~BA1 BA0~BA1
Row Address A0~A16 A0~A15 A0~A15
Column Address A0~ A9 A0~ A9 A0~ A9
Page size 512B 1 KB 2KB
Rev. 1.2 / Jul.2017 11

Absolute Maximum Ratings
Absolute Maximum DC Ratings
Absolute Maximum DC Ratings
Symbol Parameter Rating Units NOTE
VDD Voltage on VDD pin relative to Vss -0.3 ~ 1.5 V 1,3
VDDQ Voltage on VDDQ pin relative to Vss -0.3 ~ 1.5 V 1,3
VPP Voltage on VPP pin relative to Vss -0.3 ~ 3.0 V 4
VIN, VOUT Voltage on any pin except VREFCA relative to Vss -0.3 ~ 1.5 V 1,3,5
TSTG Storage Temperature -55 to +100 °C 1,2
NOTE :
1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of the device at these or any other conditions above those indi-
cated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect reliability
2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement
conditions, please refer to JESD51-2 standard.
3. VDD and VDDQ must be within 300 mV of each other at all times;and VREFCA must be not greater than 0.6 x
VDDQ, When VDD and VDDQ are less than 500 mV; VREFCA may be equal to or less than 300 mV
4. VPP must be equal or greater than VDD/VDDQ at all times
5. Overshoot area above 1.5V is specified in DDR4 Device Operation.
DRAM Component Operating Temperature Range

Temperature Range
Symbol Parameter Rating Units Notes

0 to 85 oC 1,2
Normal Operating Temperature Range
TOPER oC
Extended Temperature Range 85 to 95 1,3
Notes:
1. Operating Temperature TOPER is the case surface temperature on the center / top side of the DRAM. For measure-
ment conditions, please refer to the JEDEC document JESD51-2.
2. The Normal Temperature Range specifies the temperatures where all DRAM specifications will be supported.
During operation, the DRAM case temperature must be maintained between 0 - 85oC under all operating condi-
tions.
3. Some applications require operation of the DRAM in the Extended Temperature Range between 85oC and 95oC
case temperature. Full specifications are guaranteed in this range, but the following additional conditions apply:
a. Refresh commands must be doubled in frequency, therefore reducing the Refresh interval tREFI to 3.9 µs. It is
also possible to specify a component with 1X refresh (tREFI to 7.8µs) in the Extended Temperature Range.
Please refer to the DIMM SPD for option availability
b. If Self-Refresh operation is required in the Extended Temperature Range, then it is mandatory to either use
the Manual Self-Refresh mode with Extended Temperature Range capability (MR2 A6 = 0b and MR2 A7 = 1b)
or enable the optional Auto Self-Refresh mode (MR2 A6 = 1b and MR2 A7 = 0b).
Rev. 1.2 / Jul.2017 12

AC & DC Operating Conditions
Recommended DC Operating Conditions
Recommended DC Operating Conditions
Rating
Symbol Parameter Unit NOTE
Min. Typ. Max.
VDD Supply Voltage 1.14 1.2 1.26 V 1,2,3
VDDQ Supply Voltage for Output 1.14 1.2 1.26 V 1,2,3
VPP Supply Voltage for DRAM Activating 2.375 2.5 2.75 V 3
NOTE:
1. Under all conditions VDDQ must be less than or equal to VDD.
2. VDDQ tracks with VDD. AC parameters are measured with VDD and VDDQ tied together.
3. DC bandwidth is limited to 20MHz.
Rev. 1.2 / Jul.2017 13

IDD and IDDQ Specification Parameters and Test Conditions
IDD, IPP and IDDQ Measurement Conditions
In this chapter, IDD, IPP and IDDQ measurement conditions such as test load and patterns are defined.
Figure shows the setup and test load for IDD, IPP and IDDQ measurements.
• IDD currents (such as IDD0, IDD0A, IDD1, IDD1A, IDD2N, IDD2NA, IDD2NL, IDD2NT, IDD2P, IDD2Q,
IDD3N, IDD3NA, IDD3P, IDD4R, IDD4RA, IDD4W, IDD4WA, IDD5B, IDD5F2, IDD5F4, IDD6N, IDD6E,
IDD6R, IDD6A, IDD7 and IDD8) are measured as time-averaged currents with all VDD balls of the
DDR4 SDRAM under test tied together. Any IPP or IDDQ current is not included in IDD currents.
• IPP currents have the same definition as IDD except that the current on the VPP supply is measured.
• IDDQ currents (such as IDDQ2NT and IDDQ4R) are measured as time-averaged currents with all
VDDQ balls of the DDR4 SDRAM under test tied together. Any IDD current is not included in IDDQ cur-
rents.
Attention: IDDQ values cannot be directly used to calculate IO power of the DDR4 SDRAM. They can
be used to support correlation of simulated IO power to actual IO power as outlined in Figure 2. In
DRAM module application, IDDQ cannot be measured separately since VDD and VDDQ are using one
merged-power layer in Module PCB.
For IDD, IPP and IDDQ measurements, the following definitions apply:
• “0” and “LOW” is defined as VIN <= VILAC(max).
• “1” and “HIGH” is defined as VIN >= VIHAC(min).
• “MID-LEVEL” is defined as inputs are VREF = VDD / 2.
• Timings used for IDD, IPP and IDDQ Measurement-Loop Patterns are provided in Table 1.
• Basic IDD, IPP and IDDQ Measurement Conditions are described in Table 2.
• Detailed IDD, IPP and IDDQ Measurement-Loop Patterns are described in Table 3 through Table 11.
• IDD Measurements are done after properly initializing the DDR4 SDRAM. This includes but is not lim-
ited to setting 
RON = RZQ/7 (34 Ohm in MR1); 
RTT_NOM = RZQ/6 (40 Ohm in MR1);
RTT_WR = RZQ/2 (120 Ohm in MR2);
RTT_PARK = Disable;
Qoff = 0B (Output Buffer enabled) in MR1;
TDQS_t disabled in MR1;
CRC disabled in MR2;
CA parity feature disabled in MR5;
Gear down mode disabled in MR3
Read/Write DBI disabled in MR5;
DM disabled in MR5
• Attention: The IDD, IPP and IDDQ Measurement-Loop Patterns need to be executed at least one time
before actual IDD or IDDQ measurement is started.
• Define D = {CS_n, ACT_n, RAS_n, CAS_n, WE_n } := {HIGH, LOW, LOW, LOW, LOW} ; apply BG/BA
changes when directed.
• Define D# = {CS_n, ACT_n, RAS_n, CAS_n, WE_n } := {HIGH, HIGH, HIGH, HIGH, HIGH} ; apply
invert of BG/BA changes when directed above.
Rev. 1.2 / Jul.2017 14

IDD IPP IDDQ
VDD VPP VDDQ

RESET
CK_t/CK_c
DDR4 SDRAM
CKE
CS DQS_t/DQS_c
C DQ
ACT,RAS,CAS,WE DM
A,BG,BA
ODT VSS VSSQ
ZQ
NOTE:
1. DIMM level Output test load condition may be different from above
Figure 1 - Measurement Setup and Test Load for IDD, IPP and IDDQ Measurements
Application specific
memory channel IDDQ
TestLad
environment
Channel
IO Powe IDDQ IDDQ
Simuaion Measurement
Simulatin
X Correlation
X
Channel IO Power
Number
Figure 2 - Correlation from simulated Channel IO Power to actual Channel IO Power supported by IDDQ
Measurement
Rev. 1.2 / Jul.2017 15

Table 1 -Timings used for IDD, IPP and IDDQ Measurement-Loop Patterns
DDR4-1600 DDR4-1866 DDR4-2133 DDR4-2400
Symbol Unit
11-11-11 13-13-13 15-15-15 17-17-17
tCK 1.25 1.071 0.937 0.833 ns
CL 11 13 15 17 nCK
CWL 11 12 14 17 nCK
nRCD 11 13 15 17 nCK
nRC 39 45 51 56 nCK
nRAS 28 32 36 39 nCK
nRP 11 13 15 17 nCK
x4 16 16 16 16 nCK
nFAW x8 20 22 23 26 nCK
x16 28 28 32 36 nCK
x4 4 4 4 4 nCK
nRRDS x8 4 4 4 4 nCK
x16 5 5 6 7 nCK
x4 5 5 6 6 nCK
nRRDL x8 5 5 6 6 nCK
x16 6 6 7 8 nCK
tCCD_S 4 4 4 4 nCK
tCCD_L 5 5 6 6 nCK
tWTR_S 2 3 3 3 nCK
tWTR_L 6 7 8 9 nCK
nRFC 2Gb 128 150 171 193 nCK
nRFC 4Gb 208 243 278 313 nCK
nRFC 8Gb 280 327 374 421 nCK
nRFC 16Gb TBD TBD TBD TBD nCK
Rev. 1.2 / Jul.2017 16

Table 2 -Basic IDD, IPP and IDDQ Measurement Conditions
Symbol Description
Operating One Bank Active-Precharge Current (AL=0)
CKE: High; External clock: On; tCK, nRC, nRAS, CL: see Table 1; BL: 81; AL: 0; CS_n: High
between ACT and PRE; Command, Address, Bank Group Address, Bank Address Inputs: partially
IDD0
toggling according to Table 3; Data IO: VDDQ; DM_n: stable at 1; Bank Activity: Cycling with one
bank active at a time: 0,0,1,1,2,2,... (see Table 3); Output Buffer and RTT: Enabled in Mode Regis-
ters2; ODT Signal: stable at 0; Pattern Details: see Table 3
Operating One Bank Active-Precharge Current (AL=CL-1)
IDD0A
AL = CL-1, Other conditions: see IDD0
Operating One Bank Active-Precharge IPP Current
IPP0
Same condition with IDD0
Operating One Bank Active-Read-Precharge Current (AL=0)
CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, CL: see Table 1; BL: 81; AL: 0; CS_n: High
between ACT, RD and PRE; Command, Address, Bank Group Address, Bank Address Inputs,
IDD1
Data IO: partially toggling according to Table 4; DM_n: stable at 1; Bank Activity: Cycling with one
bank active at a time: 0,0,1,1,2,2,... (see Table 4); Output Buffer and RTT: Enabled in Mode Regis-
ters2; ODT Signal: stable at 0; Pattern Details: see Table 4
Operating One Bank Active-Read-Precharge Current (AL=CL-1)
IDD1A
AL = CL-1, Other conditions: see IDD1
Operating One Bank Active-Read-Precharge IPP Current
IPP1
Precharge Standby Current (AL=0)
CKE: High; External clock: On; tCK, CL: see Table 1; BL: 81; AL: 0; CS_n: stable at 1; Command,
IDD2N Address, Bank Group Address, Bank Address Inputs: partially toggling according to Table 5; Data
IO: VDDQ; DM_n: stable at 1; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in
Mode Registers2; ODT Signal: stable at 0; Pattern Details: see Table 5
Precharge Standby Current (AL=CL-1)
IDD2NA
AL = CL-1, Other conditions: see IDD2N
Precharge Standby IPP Current
IPP2N
Same condition with IDD2N
Precharge Standby ODT Current
IDD2NT Address, Bank Group Address, Bank Address Inputs: partially toggling according to Table 6; Data
IO: VSSQ; DM_n: stable at 1; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in
Mode Registers2; ODT Signal: toggling according to Table 6; Pattern Details: see Table 6
IDDQ2NT Precharge Standby ODT IDDQ Current
(Optional) Same definition like for IDD2NT, however measuring IDDQ current instead of IDD current
Precharge Standby Current with CAL enabled
IDD2NL
Same definition like for IDD2N, CAL enabled3
Precharge Standby Current with Gear Down mode enabled
IDD2NG
Same definition like for IDD2N, Gear Down mode enabled3,5
Precharge Standby Current with DLL disabled
IDD2ND
Same definition like for IDD2N, DLL disabled3
Rev. 1.2 / Jul.2017 17

Precharge Standby Current with CA parity enabled
IDD2N_par
Same definition like for IDD2N, CA parity enabled3
Precharge Power-Down Current CKE: Low; External clock: On; tCK, CL: see Table 1; BL: 81; AL:
0; CS_n: stable at 1; Command, Address, Bank Group Address, Bank Address Inputs: stable at
IDD2P
0; Data IO: VDDQ; DM_n: stable at 1; Bank Activity: all banks closed; Output Buffer and RTT:
Enabled in Mode Registers2; ODT Signal: stable at 0
Precharge Power-Down IPP Current
IPP2P
Same condition with IDD2P
Precharge Quiet Standby Current
IDD2Q Address, Bank Group Address, Bank Address Inputs: stable at 0; Data IO: VDDQ; DM_n: stable
at 1;Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers2; ODT
Signal: stable at 0
Active Standby Current
IDD3N Address, Bank Group Address, Bank Address Inputs: partially toggling according to Table 5; Data
IO: VDDQ; DM_n: stable at 1;Bank Activity: all banks open; Output Buffer and RTT: Enabled in
Mode Registers2; ODT Signal: stable at 0; Pattern Details: see Table 5
Active Standby Current (AL=CL-1)
IDD3NA
AL = CL-1, Other conditions: see IDD3N
Active Standby IPP Current
IPP3N
Active Power-Down Current
CKE: Low; External clock: On; tCK, CL: see Table 1; BL: 81; AL: 0; CS_n: stable at 1; Command,
IDD3P Address, Bank Group Address, Bank Address Inputs: stable at 0; Data IO: VDDQ; DM_n: stable
at 1; Bank Activity: all banks open; Output Buffer and RTT: Enabled in Mode Registers2; ODT Signal:
stable at 0
Active Power-Down IPP Current
IPP3P
Same condition with IDD3P
Operating Burst Read Current
CKE: High; External clock: On; tCK, CL: see Table 1; BL: 82; AL: 0; CS_n: High between RD;
Command, Address, Bank Group Address, Bank Address Inputs: partially toggling according to
IDD4R Table 7; Data IO: seamless read data burst with different data between one burst and the next one
according to Table 7; DM_n: stable at 1; Bank Activity: all banks open, RD commands cycling through
banks: 0,0,1,1,2,2,... (see Table 7); Output Buffer and RTT: Enabled in Mode Registers2; ODT Signal:
stable at 0; Pattern Details: see Table 7
Operating Burst Read Current (AL=CL-1)
IDD4RA
AL = CL-1, Other conditions: see IDD4R
Operating Burst Read Current with Read DBI
IDD4RB
Read DBI enabled3, Other conditions: see IDD4R
Operating Burst Read IPP Current
IPP4R
Same condition with IDD4R
IDDQ4R Operating Burst Read IDDQ Current
(Optional) Same definition like for IDD4R, however measuring IDDQ current instead of IDD current
IDDQ4RB Operating Burst Read IDDQ Current with Read DBI
(Optional) Same definition like for IDD4RB, however measuring IDDQ current instead of IDD current
Rev. 1.2 / Jul.2017 18

Operating Burst Write Current
CKE: High; External clock: On; tCK, CL: see Table 1; BL: 81; AL: 0; CS_n: High between WR;
IDD4W Table 8; Data IO: seamless write data burst with different data between one burst and the next one
according to Table 8; DM_n: stable at 1; Bank Activity: all banks open, WR commands cycling through
banks: 0,0,1,1,2,2,... (see Table 8); Output Buffer and RTT: Enabled in Mode Registers2; ODT Signal:
stable at HIGH; Pattern Details: see Table 8
Operating Burst Write Current (AL=CL-1)
IDD4WA
AL = CL-1, Other conditions: see IDD4W
Operating Burst Write Current with Write DBI
IDD4WB
Write DBI enabled3, Other conditions: see IDD4W
Operating Burst Write Current with Write CRC
IDD4WC
Write CRC enabled3, Other conditions: see IDD4W
Operating Burst Write Current with CA Parity
IDD4W_par
CA Parity enabled3, Other conditions: see IDD4W
Operating Burst Write IPP Current
IPP4W
Same condition with IDD4W
Burst Refresh Current (1X REF)
CKE: High; External clock: On; tCK, CL, nRFC: see Table 1; BL: 81; AL: 0; CS_n: High between REF;
IDD5B
Table 9; Data IO: VDDQ; DM_n: stable at 1; Bank Activity: REF command every nRFC (see Table 9);
Output Buffer and RTT: Enabled in Mode Registers2; ODT Signal: stable at 0; Pattern Details: see
Table 9
Burst Refresh Write IPP Current (1X REF)
IPP5B
Same condition with IDD5B
IDD5F2
tRFC=tRFC_x2, Other conditions: see IDD5B
IPP5F2
Same condition with IDD5F2
IDD5F4
tRFC=tRFC_x4, Other conditions: see IDD5B
IPP5F4
Same condition with IDD5F4
Self Refresh Current: Normal Temperature Range
TCASE: 0 - 85°C; Low Power Array Self Refresh (LP ASR) : Normal4; CKE: Low; External clock:
IDD6N Off; CK_t and CK_c#: LOW; CL: see Table 1; BL: 81; AL: 0; CS_n#, Command, Address, Bank Group
Address, Bank Address, Data IO: High; DM_n: stable at 1; Bank Activity: Self-Refresh operation;
Output Buffer and RTT: Enabled in Mode Registers2; ODT Signal: MID-LEVEL
Self Refresh IPP Current: Normal Temperature Range
IPP6N
Self-Refresh Current: Extended Temperature Range)
TCASE: 0 - 95°C; Low Power Array Self Refresh (LP ASR) : Extended4; CKE: Low; External clock:
IDD6E Off; CK_t and CK_c: LOW; CL: see Table 1; BL: 81; AL: 0; CS_n, Command, Address, Bank Group
Address, Bank Address, Data IO: High; DM_n:stable at 1; Bank Activity: Extended Temperature
Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registers2; ODT Signal: MID-LEVEL
Self Refresh IPP Current: Extended Temperature Range
IPP6E
Same condition with IDD6E
Rev. 1.2 / Jul.2017 19

Self-Refresh Current: Reduced Temperature Range
TCASE: 0 - TBD (~35-45)°C; Low Power Array Self Refresh (LP ASR) : Reduced4; CKE: Low;
External clock: Off; CK_t and CK_c#: LOW; CL: see Table 1; BL: 81; AL: 0; CS_n#, Command,
IDD6R
Address, Bank Group Address, Bank Address, Data IO: High; DM_n:stable at 1; Bank Activity:
Extended Temperature Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registers2;
ODT Signal: MID-LEVEL
Self Refresh IPP Current: Reduced Temperature Range
IPP6R
Same condition with IDD6R
Auto Self-Refresh Current
TCASE: 0 - 95°C; Low Power Array Self Refresh (LP ASR) : Auto4; CKE: Low; External clock: Off;
IDD6A CK_t and CK_c#: LOW; CL: see Table 1; BL: 81; AL: 0; CS_n#, Command, Address, Bank Group
Address, Bank Address, Data IO: High; DM_n:stable at 1; Bank Activity: Auto Self-Refresh
operation; Output Buffer and RTT: Enabled in Mode Registers2; ODT Signal: MID-LEVEL
Auto Self-Refresh IPP Current
IPP6A
Same condition with IDD6A
Operating Bank Interleave Read Current
CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, nRRD, nFAW, CL: see Table 1; BL: 81; AL:
CL-1; CS_n: High between ACT and RDA; Command, Address, Bank Group Address, Bank Address
IDD7 Inputs: partially toggling according to Table 10; Data IO: read data bursts with different data between
one burst and the next one according to Table 10; DM_n: stable at 1; Bank Activity: two times
interleaved cycling through banks (0, 1, ...7) with different addressing, see Table 10; Output Buffer and
RTT: Enabled in Mode Registers2; ODT Signal: stable at 0; Pattern Details: see Table 10
Operating Bank Interleave Read IPP Current
IPP7
Maximum Power Down Current
IDD8
TBD
Maximum Power Down IPP Current
IPP8
Rev. 1.2 / Jul.2017 20

NOTE :
1. Burst Length: BL8 fixed by MRS: set MR0 [A1:0=00].
2. Output Buffer Enable
- set MR1 [A12 = 0] : Qoff = Output buffer enabled
- set MR1 [A2:1 = 00] : Output Driver Impedance Control = RZQ/7
RTT_Nom enable
- set MR1 [A10:8 = 011] : RTT_NOM = RZQ/6
RTT_WR enable
- set MR2 [A10:9 = 01] : RTT_WR = RZQ/2
RTT_PARK disable
- set MR5 [A8:6 = 000]
3. CAL enabled : set MR4 [A8:6 = 001] : 1600MT/s
010] : 1866MT/s, 2133MT/s
011] : 2400MT/s
Gear Down mode enabled :set MR3 [A3 = 1] : 1/4 Rate
DLL disabled : set MR1 [A0 = 0]
CA parity enabled :set MR5 [A2:0 = 001] : 1600MT/s,1866MT/s, 2133MT/s
010] : 2400MT/s
Read DBI enabled : set MR5 [A12 = 1]
Write DBI enabled : set :MR5 [A11 = 1]
4. Low Power Array Self Refresh (LP ASR) : set MR2 [A7:6 = 00] : Normal
01] : Reduced Temperature range
10] : Extended Temperature range
11] : Auto Self Refresh
5. IDD2NG should be measured after sync pulse(NOP) input.
Rev. 1.2 / Jul.2017 21

Table 3 - IDD0, IDD0A and IPP0 Measurement-Loop Pattern1
RAS_n/ A16
CAS_n/ A15
A[17,13,11]
CK_t /CK_c
WE_n/ A14
A12/BC_n
Command
Sub-Loop
A[10]/AP
BG[1:0]2
Number
BA[1:0]
C[2:0]3
ACT_n
A[9:7]
A[6:3]
A[2:0]
Cycle
CS_n
ODT
CKE
Data4
0 0 ACT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -
1,2 D, D 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -
D_#,
3,4
D_#
1 1 1 1 1 0 0 32 3 0 0 0 7 F 0 -
... repeat pattern 1...4 until nRAS - 1, truncate if necessary

nRAS PRE 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 -
... repeat pattern 1...4 until nRC - 1, truncate if necessary
1 1*nRC repeat Sub-Loop 0, use BG[1:0]2 = 1, BA[1:0] = 1 instead
Static High
toggling

11 11*nRC repeat Sub-Loop 0, use BG[1:0]2 = 3, BA[1:0] = 3 instead For x4
and x8
12 12*nRC repeat Sub-Loop 0, use BG[1:0]2 = 2, BA[1:0] = 1 instead only
NOTE:
1 .DQS_t, DQS_c are VDDQ.
2. BG1 is don’t care for x16 device
3. C[2:0] are used only for 3DS device
4. DQ signals are VDDQ.
Rev. 1.2 / Jul.2017 22

Table 4 - IDD1, IDD1A and IPP1 Measurement-Loop Patterna)
A[17,13,11]
RAS_n/A16
CAS_n/A15
CK_t, CK_c
WE_n/A14
A12/BC_n
Command
A[10]/AP
Sub-Loop
BG[1:0]2
Number
BA[1:0]
C[2:0]3
ACT_n
A[9:7]
A[6:3]
A[2:0]
Cycle
CS_n
ODT
CKE
Data4
0 0 ACT 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 -
1, 2 D, D 1 0 0 0
0 0 0 0 0 0 0 0 0 0 0 -
3, 4 D#, D# 1 1 1 1
0 3b 3 0 0 0 7 F 1 0 0 -
... repeat pattern 1...4 until nRCD - AL - 1, truncate if necessary
nRCD -AL RD 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 D0=00, D1=FF
D2=FF, D3=00
D4=FF, D5=00
D6=00, D7=FF
nRAS PRE 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 -
... repeat pattern 1...4 until nRC - 1, truncate if necessary
1 1*nRC + 0 ACT 0 0 0 1 1 0 0 1 1 0 0 0 0 0 0 -
1*nRC + 1, 2 D, D 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -
1*nRC + 3, 4 D#, D# 1 1 1 1 1 0 0 3b 3 0 0 0 7 F 0 -
... repeat pattern nRC + 1...4 until 1*nRC + nRAS - 1, truncate if necessary
1*nRC + nRCD RD 0 1 1 0 1 0 0 1 1 0 0 0 0 0 0 D0=FF, D1=00
- AL D2=00, D3=FF
D4=00, D5=FF
Static High
D6=FF, D7=00
toggling

1*nRC + nRAS PRE 0 1 0 1 0 0 0 1 1 0 0 0 0 0 0 -
... repeat nRC + 1...4 until 2*nRC - 1, truncate if necessary
For x4 and x8 only
NOTE:
1. DQS_t, DQS_c are used according to RD Commands, otherwise VDDQ
4.Burst Sequence driven on each DQ signal by Read Command. Outside burst operation, DQ signals are VDDQ.
Rev. 1.2 / Jul.2017 23

Table 5 - IDD2N, IDD2NA, IDD2NL, IDD2NG, IDD2ND, IDD2N_par, IPP2,IDD3N,
IDD3NA and IDD3P
Measurement-Loop Pattern1
A[17,13,11]
RAS_n/A16
CAS_n/A15
CK_t, CK_c
WE_n/A14
A12/BC_n
Command
A[10]/AP
Sub-Loop
BG[1:0]2
Number
BA[1:0]
C[2:0]3
A[9:7]
A[6:3]
A[2:0]
ACT_n
Cycle
CS_n
ODT
CKE
Data4
0 0 D, D 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1 D, D 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
2 D#, 1 1 1 1 1 0 0 32 3 0 0 0 7 F 0 0
D#
3 D#, 1 1 1 1 1 0 0 32 3 0 0 0 7 F 0 0
D#
1 4-7 repeat Sub-Loop 0, use BG[1:0]2 = 1, BA[1:0] = 1 instead
Static High

toggling

NOTE :
1. DQS_t, DQS_c are VDDQ.
Rev. 1.2 / Jul.2017 24

Table 6 - IDD2NT and IDDQ2NT Measurement-Loop Pattern1
A[17,13,11]
RAS_n/A16
CAS_n/A15
CK_t, CK_c
WE_n/A14
A12/BC_n
Command
A[10]/AP
Sub-Loop
BG[1:0]2
Number
BA[1:0]
C[2:0]3
ACT_n
A[9:7]
A[6:3]
A[2:0]
Cycle
CS_n
ODT
CKE
Data4
0 0 D, D 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -
1 D, D 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -
2 D#, D# 1 1 1 1 1 0 0 32 3 0 0 0 7 F 0 -
3 D#, D# 1 1 1 1 1 0 0 32 3 0 0 0 7 F 0 -
1 4-7 repeat Sub-Loop 0, but ODT = 1 and BG[1:0]2 = 1, BA[1:0] = 1 instead
Static High
toggling

For x4
11 44-47 repeat Sub-Loop 0, but ODT = 1 and BG[1:0]2 = 3, BA[1:0] = 3 instead and x8
12 48-51 repeat Sub-Loop 0, but ODT = 0 and BG[1:0]2 = 2, BA[1:0] = 1 instead only
NOTE :
Rev. 1.2 / Jul.2017 25

Table 7 - IDD4R, IDDR4RA, IDD4RB and IDDQ4R Measurement-Loop Pattern1
A[17,13,11]
RAS_n/A16
CAS_n/A15
CK_t, CK_c
WE_n/A14
A12/BC_n
Command
A[10]/AP
Sub-Loop
BG[1:0]2
Number
BA[1:0]
C[2:0]3
ACT_n
A[9:7]
A[6:3]
A[2:0]
Cycle
CS_n
ODT
CKE
Data4
0 0 RD 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 D0=00, D1=FF
D2=FF, D3=00
D4=FF, D5=00
D6=00, D7=FF
1 D 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -
2,3 D#, D# 1 1 1 1 1 0 0 3 2 3 0 0 0 7 F 0 -
1 4 RD 0 1 1 0 1 0 0 1 1 0 0 0 7 F 0 D0=FF, D1=00
D2=00, D3=FF
D4=00, D5=FF
D6=FF, D7=00
5 D 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -
6,7 D#, D# 1 1 1 1 1 0 0 3 2 3 0 0 0 7 F 0 -
Static High

toggling

For x4 and x8 only
NOTE :
1. DQS_t, DQS_c are used according to RD Commands, otherwise VDDQ.
4. Burst Sequence driven on each DQ signal by Read Command.
Rev. 1.2 / Jul.2017 26

Table 8 - IDD4W, IDD4WA, IDD4WB and IDD4W_par Measurement-Loop Pattern1
A[17,13,11]
RAS_n/A16
CAS_n/A15
CK_t, CK_c
WE_n/A14
A12/BC_n
Command
A[10]/AP
Sub-Loop
BG[1:0]2
Number
BA[1:0]
C[2:0]3
ACT_n
A[9:7]
A[6:3]
A[2:0]
Cycle
CS_n
ODT
CKE
Data4
0 0 WR 0 1 1 0 1 1 0 0 0 0 0 0 0 0 0 D0=00, D1=FF
D2=FF, D3=00
D4=FF, D5=00
D6=00, D7=FF
1 D 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 -
2,3 D#, D# 1 1 1 1 1 1 0 3 2 3 0 0 0 7 F 0 -
1 4 WR 0 1 1 0 1 1 0 1 1 0 0 0 7 F 0 D0=FF, D1=00
D2=00, D3=FF
D4=00, D5=FF
D6=FF, D7=00
5 D 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 -
6,7 D#, D# 1 1 1 1 1 1 0 3 2 3 0 0 0 7 F 0 -
2 8-11 repeat Sub-Loop 0, use BG[1:0] = 0, BA[1:0] = 2 instead 2
Static High

toggling

For x4 and x8 only
NOTE :
1. DQS_t, DQS_c are used according to WR Commands, otherwise VDDQ.
4. Burst Sequence driven on each DQ signal by Write Command.
Rev. 1.2 / Jul.2017 27

Table 9 - IDD4WC Measurement-Loop Pattern1
A[17,13,11]
RAS_n/A16
CAS_n/A15
CK_t, CK_c
WE_n/A14
A12/BC_n
Command
A[10]/AP
Sub-Loop
BG[1:0]b
Number
BA[1:0]
C[2:0]c
ACT_n
A[9:7]
A[6:3]
A[2:0]
Cycle
CS_n
ODT
CKE
Datad
0 0 WR 0 1 1 0 1 1 0 0 0 0 0 0 0 0 0 D0=00, D1=FF
D2=FF, D3=00
D4=FF, D5=00
D6=00, D7=FF
D8=CRC
1,2 D, D 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 -
3,4 D#, D# 1 1 1 1 1 1 0 3 2 3 0 0 0 7 F 0 -
5 WR 0 1 1 0 1 1 0 1 1 0 0 0 7 F 0 D0=FF, D1=00
D2=00, D3=FF
D4=00, D5=FF
D6=FF, D7=00
D8=CRC
6,7 D, D 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 -
8,9 D#, D# 1 1 1 1 1 1 0 32 3 0 0 0 7 F 0 -
Static High
toggling

For x4 and x8 only
NOTE :
2. BG1 is don’t care for x16 device.
3. C[2:0] are used only for 3DS device.
4. Burst Sequence driven on each DQ signal by Write Command.
Rev. 1.2 / Jul.2017 28

Table 10 - IDD5B Measurement-Loop Pattern1
A[17,13,11]
RAS_n/A16
CAS_n/A15
CK_t, CK_c
WE_n/A14
A12/BC_n
Command
A[10]/AP
Sub-Loop
BG[1:0]2
Number
BA[1:0]
C[2:0]3
ACT_n
A[9:7]
A[6:3]
A[2:0]
Cycle
CS_n
ODT
CKE
Data4
0 0 REF 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -
1 1 D 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -
2 D 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -
3 D#, D# 1 1 1 1 1 0 0 32 3 0 0 0 7 F 0 -
4 D#, D# 1 1 1 1 1 0 0 32 3 0 0 0 7 F 0 -
4-7 repeat pattern 1...4, use BG[1:0]2 = 1, BA[1:0] = 1 instead
Static High
toggling

For x4 and x8
44-47 repeat pattern 1...4, use BG[1:0]2 = 3, BA[1:0] = 3 instead only
2 64 ... nRFC - 1 repeat Sub-Loop 1, Truncate, if necessary
NOTE :
Rev. 1.2 / Jul.2017 29

Table 11 - IDD7 Measurement-Loop Pattern1
A[17,13,11]
RAS_n/A16
CAS_n/A15
CK_t, CK_c
WE_n/A14
A12/BC_n
Command
A[10]/AP
Sub-Loop
BG[1:0]2
Number
BA[1:0]
C[2:0]3
ACT_n
A[9:7]
A[6:3]
A[2:0]
Cycle
CS_n
ODT
CKE
Data4
0 0 ACT 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0
1 RDA 0 1 1 0 1 0 0
0 D0=00, D1=FF 0 0 0 1 0 0
D2=FF, D3=00
D4=FF, D5=00
D6=00, D7=FF
2 D 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -
3 D# 1 1 1 1 1 0 0 32 3 0 0 0 7 F 0 -
... repeat pattern 2...3 until nRRD - 1, if nRRD > 4. Truncate if necessary
1 nRRD ACT 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 -
nRRD + 1 RDA 0 1 1 0 1 0 1 1 0 0 1 0 0 0 D0=FF, D1=00
D2=00, D3=FF
D4=00, D5=FF
D6=FF, D7=00
... repeat pattern 2 ... 3 until 2*nRRD - 1, if nRRD > 4. Truncate if necessary
2 2*nRRD repeat Sub-Loop 0, use BG[1:0]2 = 0, BA[1:0] = 2 instead
3 3*nRRD repeat Sub-Loop 1, use BG[1:0]2 = 1, BA[1:0] = 3 instead
4 4*nRRD repeat pattern 2 ... 3 until nFAW - 1, if nFAW > 4*nRRD. Truncate if necessary
Static High
5 nFAW BG[1:0]2 = 0, BA[1:0] = 1

toggling
repeat Sub-Loop 0, use instead

6 nFAW + nRRD repeat Sub-Loop 1, use BG[1:0]2 = 1, BA[1:0] = 2 instead
7 nFAW + 2*nRRD repeat Sub-Loop 0, use BG[1:0]2 = 0, BA[1:0] = 3 instead
8 nFAW + 3*nRRD repeat Sub-Loop 1, use BG[1:0]2 = 1, BA[1:0] = 0 instead
9 nFAW + 4*nRRD repeat Sub-Loop 4
10 2*nFAW repeat Sub-Loop 0, use BG[1:0]2 = 2, BA[1:0] = 0 instead

11 2*nFAW + nRRD repeat Sub-Loop 1, use BG[1:0]2 = 3, BA[1:0] = 1 instead
12 2*nFAW + 2*nRRD repeat Sub-Loop 0, use BG[1:0]2 = 2, BA[1:0] = 2 instead
14 2*nFAW + 4*nRRD repeat Sub-Loop 4
For x4 and x8
15 3*nFAW repeat Sub-Loop 0, use BG[1:0]2 = 2, BA[1:0] = 1 instead only
16 3*nFAW + nRRD repeat Sub-Loop 1, use BG[1:0]2 = 3, BA[1:0] = 2 instead
19 3*nFAW + 4*nRRD repeat Sub-Loop 4
20 4*nFAW repeat pattern 2 ... 3 until nRC - 1, if nRC > 4*nFAW. Truncate if necessary
NOTE :
4. Burst Sequence driven on each DQ signal by Read Command. Outside burst operation, DQ signals are VDDQ
Rev. 1.2 / Jul.2017 30

IDD Specifications
IDD and IPP values are for full operating range of voltage and temperature unless otherwise noted. IDD
and IPP values are for full operating range of voltage and temperature unless otherwise noted.
IDD and IDDQ Specification
2133 2400 2666
Symbol Unit NOTE
x4 x8 x16 x4 x8 x16 x4 x8 x16
IDD0 37 37 44 38 38 46 40 40 48 mA
IDD0A 37 37 44 38 38 46 40 40 48 mA
IDD1 44 46 57 46 48 60 49 51 62 mA
IDD1A 46 49 60 48 51 63 51 54 66 mA
IDD2N 26 26 26 27 27 27 29 29 29 mA
IDD2NA 26 26 26 27 27 27 29 29 29 mA
IDD2NT 31 31 31 32 32 32 35 35 35 mA
IDD2NL 18 18 18 18 18 18 19 19 19 mA
IDD2NG 26 26 26 26 26 26 29 29 29 mA
IDD2ND 26 26 26 26 26 26 29 29 29 mA
IDD2N_par 26 26 26 26 26 26 29 29 29 mA
IDD2P 18 18 18 18 18 18 19 19 19 mA
IDD2Q 22 22 22 22 22 22 24 24 24 mA
IDD3N 44 44 44 45 45 45 47 47 47 mA
IDD3NA 44 44 44 45 45 45 47 47 47 mA
IDD3P 36 36 36 37 37 37 38 38 38 mA
IDD4R 104 115 177 113 124 195 122 134 229 mA
IDD4RA 113 124 187 123 134 204 134 146 222 mA
IDD4RB 112 124 184 122 134 204 132 145 221 mA
IDD4W 98 111 154 107 120 170 116 131 185 mA
IDD4WA 100 114 157 109 123 172 119 134 187 mA
IDD4WB 94 110 154 102 120 170 110 130 185 mA
IDD4WC 91 106 148 99 114 164 108 124 179 mA
IDD4WC_par 108 113 164 122 136 186 131 146 200 mA
IDD5B 195 195 195 196 196 196 197 197 197 mA
IDD5F2 140 140 140 142 142 142 144 144 144 mA
IDD5F4 123 123 123 127 127 127 129 129 129 mA
IDD6N 22 22 22 22 22 22 22 22 22 mA
IDD6E 28 28 28 28 28 28 28 28 28 mA
IDD6R 14 14 14 14 14 14 14 14 14 mA
IDD6A 28 28 28 28 28 28 28 28 28 mA
IDD7 160 145 181 177 152 185 244 160 210 mA
IDD8 12 12 12 12 12 12 12 12 12 mA
NOTE :
1. Users should refer to the DRAM supplier data sheet and/or the DIMM SPD to determine if DDR4 SDRAM devices support the follow-
ing options or requirements referred to in this material.
Rev. 1.2 / Jul.2017 31

IPP Specification
2133 2400 2666
Symbol Unit NOTE
x4 x8 x16 x4 x8 x16 x4 x8 x16
IPP0 6 6 10 6 6 10 6 6 10 mA
IPP1 7 7 10 7 7 10 7 7 10 mA
IPP2N 3.2 3.2 3.2 3.2 3.2 3.2 3.2 3.2 3.2 mA
IPP2P 3.2 3.2 3.2 3.2 3.2 3.2 3.2 3.2 3.2 mA
IPP3N 15 15 18 15 15 18 15 15 18 mA
IPP3P 15 15 18 15 15 18 15 15 18 mA
IPP4R 15 15 18 15 15 18 15 15 18 mA
IPP4W 15 15 18 15 15 18 15 15 18 mA
IPP5B 65 65 65 65 65 65 65 65 65 mA
IPP5F2 45 45 45 46 46 46 47 47 47 mA
IPP5F4 40 40 40 40 40 40 40 40 40 mA
IPP6N 4 4 4 4 4 4 4 4 4 mA
IPP6E 7 7 7 7 7 7 7 7 7 mA
IPP6R 4.1 4.1 4.1 4.1 4.1 4.1 4.1 4.1 4.1 mA
IPP6A 7 7 7 7 7 7 7 7 7 mA
IPP7 25 19 24 25 19 24 29 21 28 mA
IPP8 3.2 3.2 3.2 3.2 3.2 3.2 3.2 3.2 3.2 mA
NOTE :
1.Users should refer to the DRAM supplier data sheet and/or the DIMM SPD to determine if DDR4 SDRAM devices support the following
options or requirements referred to in this material.
IDD6 Specification
Temperature 2133/2400/2666
Symbol Range x4 x8 x16 Unit NOTE
oC
IDD6N 0 - 85 22 22 22 mA 3,4
0 - 95 oC 28 28 28 mA 4,5,6
IDD6E
oC
IDD6R 0 - 45 14 14 14 mA 4,6,8
oC
IDD6A 0 - 85 28 28 28 mA 4,6,7
NOTE :
1. Some IDD currents are higher for x16 organization due to larger page-size architecture.
2. Max. values for IDD currents considering worst case conditions of process, temperature and voltage.
3. Applicable for MR2 settings A6=0 and A7=0.
4. Supplier data sheets include a max value for IDD6.
5. Applicable for MR2 settings A6=0 and A7=1. IDD6E is only specified for devices which support the Extended Temperature Range
feature.
6. Refer to the supplier data sheet for the value specification method (e.g. max, typical) for IDD6E and IDD6A
7. Applicable for MR2 settings A6=1 and A7=0. IDD6A is only specified for devices which support the Auto Self Refresh feature.
8. Applicable for MR2 settings MR2 [A7:A6 = 01] : Reduced Temperature range. IDD6R is verified by design and characterization, and
may not be subject to production test
Rev. 1.2 / Jul.2017 32

Input/Output Capacitance
Silicon pad I/O Capacitance
DDR4-
DDR4-2400,2666
Symbol Parameter 1600,1866,2133 Unit NOTE
min max min max
CIO Input/output capacitance 0.55 1.4 0.55 1.15 pF 1,2,3
CDIO Input/output capacitance delta -0.1 0.1 -0.1 0.1 pF 1,2,3,11
Input/output capacitance delta
CDDQS 0.05 0.05 pF 1,2,3,5
DQS_t and DQS_c
Input capacitance, CK_t and
CCK 0.2 0.8 0.2 0.7 pF 1,3
CK_c
Input capacitance delta CK_t and
CDCK 0.05 0.05 pF 1,3,4
CK_c
Input capacitance
CI 0.2 0.8 0.2 0.7 pF 1,3,6
(CTRL, ADD, CMD pins only)
Input capacitance delta
CDI_ CTRL -0.1 0.1 -0.1 0.1 pF 1,3,7,8
(All CTRL pins only)
Input capacitance delta
CDI_ ADD_CMD -0.1 0.1 -0.1 0.1 pF 1,2,9,10
(All ADD/CMD pins only)
Input/output capacitance of
CALERT 0.5 1.5 0.5 1.5 pF 1,3
ALERT
CZQ Input/output capacitance of ZQ - 2.3 - 2.3 pF 1,3,12
CTEN Input capacitance of TEN 0.2 2.3 0.2 2.3 pF 1,3,13
NOTE :
1. This parameter is not subject to production test. It is verified by design and characterization. The silicon only capacitance is vali-
dated by de-embedding the package L & C parasitic. The capacitance is measured with VDD, VDDQ, VSS, VSSQ applied with all
other signal pins floating. Measurement procedure tbd.
2. DQ, DM_n, DQS_T, DQS_C, TDQS_T, TDQS_C. Although the DM, TDQS_T and TDQS_C pins have different functions, the loading
matches DQ and DQS
3. This parameter applies to monolithic devices only; stacked/dual-die devices are not covered here
4. Absolute value CK_T-CK_C
5. Absolute value of CIO(DQS_T)-CIO(DQS_C)
6. CI applies to ODT, CS_n, CKE, A0-A17, BA0-BA1, BG0-BG1, RAS_n/A16, CAS_n/A15, WE_n/A14, ACT_n and PAR.
7. CDI CTRL applies to ODT, CS_n and CKE
8. CDI_CTRL = CI(CTRL)-0.5*(CI(CLK_T)+CI(CLK_C))
9. CDI_ADD_ CMD applies to, A0-A17, BA0-BA1, BG0-BG1,RAS_n/A16, CAS_n/A15, WE_n/A14, ACT_n and PAR.
10. CDI_ADD_CMD = CI(ADD_CMD)-0.5*(CI(CLK_T)+CI(CLK_C))
11. CDIO = CIO(DQ,DM)-0.5*(CIO(DQS_T)+CIO(DQS_C))
12. Maximum external load capacitance on ZQ pin: tbd pF.
13. TEN pis may be DRAM internally pulled low through a weak pull-down resistor to VSS. In this case CTEN might not be valid and
system shall verify TEN signal with Vendor specific information.
Rev. 1.2 / Jul.2017 33

DRAM package electrical specifications (x4/x8)
DDR4-1600,1866,2133,2400,2666
min max
ZIO Input/output Zpkg 45 85  1,2,4,5,10,11
TDIO Input/output Pkg Delay 14 42 ps 1,3,4,5,11
LIO Input/output Lpkg - 3.3 nH 11,12
CIO Input/output Cpkg - 0.78 pF 11,13
ZIO DQS DQS_t, DQS_c Zpkg 45 85  1,2,5,10,11
TdIO DQS DQS_t, DQS_c Pkg Delay 14 42 ps 1,3,5,10,11
LIO DQS DQS Lpkg - 3.3 nH 11,12
CIO DQS DQS Cpkg - 0.78 pF 11,13
DZDIO DQS Delta Zpkg DQS_t, DQS_c - 10  1,2,5,7,10
DTdDIO DQS Delta Delay DQS_t, DQS_c - 5 ps 1,3,5,7,10
ZI CTRL Input- CTRL pins Zpkg 50 90  1,2,5,9,10,11
TdI CTRL Input- CTRL pins Pkg Delay 14 42 ps 1,3,5,9,10,11
LI CTRL Input CTRL Lpkg - 3.4 nH 11,12
CI CTRL Input CTRL Cpkg - 0.7 pF 11,13
ZIADD CMD Input- CMD ADD pins Zpkg 50 90  1,2,5,8,10,11
TdIADD CMD Input- CMD ADD pins Pkg Delay 14 45 ps 1,3,5,8,10,11
LI ADD CMD Input CMD ADD Lpkg - 3.6 nH 11,12
CI ADD CMD Input CMD ADD Cpkg - 0.74 pF 11,13
ZCK CLK_t & CLK_c Zpkg 50 90  1,2,5,10,11
TdCK CLK_t & CLK_c Pkg Delay 14 42 ps 1,3,5,10,11
LI CLK Input CLK Lpkg - 3.4 nH 11,12
CI CLK Input CLK Cpkg - 0.7 pF 11,13
DZDLK Delta Zpkg CLK_t & CLK_c - 10  1,2,5,6,10
DTdLK Delta Delay CLK_t & CLK_c - 5 ps 1,3,5,6,10
ZO ZQ ZQ Zpkg - 100  1,2,5,10,11
TdO ZQ ZQ Delay 20 90 ps 1,3,5,10,11
ZO ALERT ALERT Zpkg 40 100  1,2,5,10,11
TdO ALERT ALERT Delay 20 55 ps 1,3,5,10,11
NOTE :
Rev. 1.2 / Jul.2017 34

1. This parameter is not subject to production test. It is verified by design and characterization. The package parasitic( L & C) are val-
idated using package only samples. The capacitance is measured with VDD, VDDQ, VSS, VSSQ shorted with all other signal pins
floating. The inductance is measured with VDD, VDDQ, VSS and VSSQ shorted and all other signal pins shorted at the die side(not
pin). Measurement procedure tbd
2. Package only impedance (Zpkg) is calculated based on the Lpkg and Cpkg total for a given pin where:
Zpkg(total per pin) = Lpkg/Cpkg
3. Package only delay(Tpkg) is calculated based on Lpkg and Cpkg total for a given pin where:
Tdpkg(total per pin) = LpkgCpkg
4. Z & Td IO applies to DQ, DM, TDQS_T and TDQS_C

5. This parameter applies to monolithic devices only; stacked/dual-die devices are not covered here
6. Absolute value of ZCK_t-ZCK_c for impedance(Z) or absolute value of TdCK_t-TdCK_c for delay(Td).
7. Absolute value of ZIO(DQS_t)-ZIO(DQS_c) for impedance(Z) or absolute value of TdIO(DQS_t)-TdIO(DQS_c) for delay(Td)
8. ZI & Td ADD CMD applies to A0-A13, ACT_n, BA0-BA1, BG0-BG1, RAS_n/A16, CAS_n/A15, WE_n/A14 and PAR.
9. ZI & Td CTRL applies to ODT, CS_n and CKE
10. This table applies to monolithic X4 and X8 devices.
11. Package implementations shall meet spec if the Zpkg and Pkg Delay fall within the ranges shown, and the maximum Lpkg and
Cpkg do not exceed the maximum values shown.
12. It is assumed that Lpkg can be approximated as Lpkg = Zo*Td.
13. It is assumed that Cpkg can be approximated as Cpkg = Td/Zo.
Rev. 1.2 / Jul.2017 35

DRAM package electrical specifications (x16)
DDR4-1600,1866,2133,2400,2666
min max
ZIO Input/output Zpkg 45 85  1
TDIO Input/output Pkg Delay 14 45 ps 1
LIO Input/output Lpkg - 3.4 nH 1,2
CIO Input/output Cpkg - 0.82 pF 1,3
ZIO DQS DQS_t, DQS_c Zpkg 45 85  1
TdIO DQS DQS_t, DQS_c Pkg Delay 14 45 ps 1
LIO DQS DQS Lpkg - 3.4 nH 1,2
CIO DQS DQS Cpkg - 0.82 pF 1,3
Delta Zpkg DQSU_t, DQSU_c - 10  -
DZDIO DQS
Delta Zpkg DQSL_t, DQSL_c - 10  -
DTdDIO DQS Delta Delay DQSU_t, DQSU_c - 5 ps -
Delta Delay DQSL_t, DQSL_c - 5 ps -
ZI CTRL Input- CTRL pins Zpkg 50 90  1
TdI CTRL Input- CTRL pins Pkg Delay 14 42 ps 1
LI CTRL Input CTRL Lpkg - 3.4 nH 1,2
CI CTRL Input CTRL Cpkg - 0.7 pF 1,3
ZIADD CMD Input- CMD ADD pins Zpkg 50 90  1
TdIADD CMD Input- CMD ADD pins Pkg Delay 14 52 ps 1
LI ADD CMD Input CMD ADD Lpkg - 3.9 nH 1,2
CI ADD CMD Input CMD ADD Cpkg - 0.86 pF 1,3
ZCK CLK_t & CLK_c Zpkg 50 90  1
TdCK CLK_t & CLK_c Pkg Delay 14 42 ps 1
LI CLK Input CLK Lpkg - 3.4 nH 1,2
CI CLK Input CLK Cpkg - 0.7 pF 1,3
DZDLK Delta Zpkg CLK_t & CLK_c - 10  -
DTdLK Delta Delay CLK_t & CLK_c - 5 ps -
ZO ZQ ZQ Zpkg - 100  -
TdO ZQ ZQ Delay 20 90 ps -
ZO ALERT ALERT Zpkg 40 100  -
TdO ALERT ALERT Delay 20 55 ps -
NOTE :
Rev. 1.2 / Jul.2017 36

1. Package implementations shall meet spec if the Zpkg and Pkg Delay fall within the ranges shown, and the maximum Lpkg and
Cpkg do not exceed the maximum values shown.
2. It is assumed that Lpkg can be approximated as Lpkg = Zo*Td.
3. It is assumed that Cpkg can be approximated as Cpkg = Td/Zo.
Rev. 1.2 / Jul.2017 37

Standard Speed Bins
DDR4-1600 Speed Bins and Operations
Speed Bin DDR4-1600K
CL-nRCD-nRP 11-11-11 Unit NOTE
Parameter Symbol min max
Internal read command to first 13.7513
tAA 18.00 ns 11
data (13.50)5,11
Internal read command to first
tAA_DBI tAA(min) + 2nCK tAA(max) +2nCK ns 11
data with read DBI enabled
ACT to internal read or write 13.75
tRCD - ns 11
delay time (13.50)5,11
13.75
PRE command period tRP - ns 11
(13.50)5,11
ACT to PRE command period tRAS 35 9 x tREFI ns 11
ACT to ACT or REF command 48.75
tRC - ns 11
period (48.50)5,11
Normal Read DBI
1,2,3,4,10
CL = 9 CL = 11 tCK(AVG) 1.5 1.6 ns
CWL = 9 ,13
CL = 10 CL = 12 tCK(AVG) Reserved ns 1,2,3,4,10
CL = 10 CL = 12 tCK(AVG) Reserved ns 1,2,3,4
CWL = 9,11 CL = 11 CL = 13 tCK(AVG) 1.25 <1.5 ns 1,2,3,4
CL = 12 CL = 14 tCK(AVG) 1.25 <1.5 ns 1,2,3
Supported CL Settings 9,11,12 nCK 12,13
Supported CL Settings with read DBI 11,13,14 nCK 12
Supported CWL Settings 9,11 nCK
Rev. 1.2 / Jul.2017 38

Speed Bin DDR4-1866M
Internal read command to first 13.9213
tAA 18.00 ns 11
data (13.50)5,11
Internal read command to first
tAA_DBI tAA(min) + 2nCK tAA(max) +2nCK ns 11
data with read DBI enabled
ACT to internal read or write delay 13.92
tRCD - ns 11
time (13.50)5,11
13.92
(13.50)5,11
ACT to ACT or REF command 47.92
tRC - ns 11
period (47.50)5,11
Normal Read DBI
1,2,3,4,10
CL = 9 CL = 11 tCK(AVG) 1.5 1.6 ns
CWL = 9 ,11
CL = 10 CL = 12 tCK(AVG) Reserved ns 4
CWL = 9,11 CL = 11 CL = 13 tCK(AVG) 1.25 <1.5 ns 1,2,3,4,6
CL = 12 CL = 14 tCK(AVG) 1.25 <1.5 ns 1,2,3,6
CL = 14 CL = 16 tCK(AVG) 1.071 <1.25 ns 1,2,3
Supported CL Settings 9,11,12,13,14 nCK 12,13
Supported CL Settings with read DBI 11,13,14 ,15,16 nCK 13
Supported CWL Settings 9,10,11,12 nCK
Rev. 1.2 / Jul.2017 39

Speed Bin DDR4-2133P
13
14.06
Internal read command to first data tAA 18.00 ns 11
(13.50)5,11
Internal read command to first data
tAA_DBI tAA(min)+3nCK tAA(max)+3nCK ns 11
with read DBI enabled
tRCD - ns 11
time (13.50)5,11
14.06
(13.50)5,11
47.06
ACT to ACT or REF command period tRC - ns 11
(46.50)5,11
Normal Read DBI
1,2,3,4,10,
CL = 9 CL = 11 tCK(AVG) 1.5 1.6 ns
CWL = 9 13
CL = 11 CL = 13 tCK(AVG) 1.25 <1.5 ns 1,2,3,4,7
CWL = 9,11
CL = 12 CL = 14 tCK(AVG) 1.25 <1.5 ns 1,2,3,7
CL = 13 CL = 15 tCK(AVG) 1.071 <1.25 ns 1,2,3,4,7
CWL = 10,12
CL = 14 CL = 16 tCK(AVG) 1.071 <1.25 ns 1,2,3,7
CL = 16 CL = 19 tCK(AVG) 0.937 <1.071 ns 1,2,3
Supported CL Settings 9,11,12,13,14,15,16 nCK 12,13
Supported CL Settings with read DBI 11,13,14,15,16,18,19 nCK
Supported CWL Settings 9,10,11,12,14 nCK
Rev. 1.2 / Jul.2017 40

Speed Bin DDR4-2400T
14.16
(13.75)5,11
tRCD - ns 11
time (13.75)5,11
14.16
(13.75)5,11
46.16
(45.75)5,11
Normal Read DBI
CWL = 9
CL = 10 CL = 12 tCK(AVG) 1.5 1.6 ns 1,2,3,4,10
CL = 12 CL = 14 tCK(AVG) 1.25 <1.5 ns 1,2,3,8
CL = 14 CL = 16 tCK(AVG) 1.071 <1.25 ns 1,2,3,8
CL = 16 CL = 19 tCK(AVG) 0.937 <1.071 ns 1,2,3,8
CWL = 12,16
CL = 17 CL = 20 tCK(AVG) 0.833 <0.937 ns
CL = 18 CL = 21 tCK(AVG) 0.833 <0.937 ns 1,2,3
Supported CL Settings 10,11,12,13,14,15,16,17,18 nCK 12
Supported CL Settings with read DBI 12,13,14,15,16,18,19,20,21 nCK
Supported CWL Settings 9,10,11,12,14,16 nCK
Rev. 1.2 / Jul.2017 41

Speed Bin DDR4-2666V
13
14.25
(13.75)5,11
tRCD - ns 11
time (13.75)5,11
14.2513
(13.75)5,11
46.25
(45.75)5,11
Normal Read DBI
CWL = 9
CL = 10 CL = 12 tCK(AVG) 1.5 1.6 ns 1,2,3,10
CL = 12 CL = 14 tCK(AVG) 1.25 <1.5 ns 1,2,3,9
CL = 14 CL = 16 tCK(AVG) 1.071 <1.25 ns 1,2,3,9
CL = 16 CL = 19 tCK(AVG) 0.937 <1.071 ns 1,2,3,9
CWL = 12,16
CL = 17 CL = 20 tCK(AVG) 0.833 <0.937 ns 1,2,3,4,9
CL = 18 CL = 21 tCK(AVG) 0.833 <0.937 ns 1,2,3
CWL = 14,18
CL = 19 CL = 22 tCK(AVG) 0.75 <0.833 ns 1,2,3,4
CL = 20 CL = 23 tCK(AVG) 0.75 <0.833 ns 1,2,3
Supported CL Settings 10,11,12,13,14,15,16,17,18,19,20 nCK 12
Supported CL Settings with read DBI 12,13,14,15,17,18,19,20,21,22,23 nCK
Supported CWL Settings 9,10,11,12,14,16,18 nCK
Rev. 1.2 / Jul.2017 42

Speed Bin Table Notes
Absolute Specification
- VDDQ = VDD = 1.20V +/- 0.06 V
- VPP = 2.5V +0.25/-0.125 V
- The values defined with above-mentioned table are DLL ON case.
- DDR4-1600, 1866, 2133 and 2400 Speed Bin Tables are valid only when Geardown Mode is disabled.
1. The CL setting and CWL setting result in tCK(avg).MIN and tCK(avg).MAX requirements. When making
a selection of tCK(avg), both need to be fulfilled: Requirements from CL setting as well as require-
ments from CWL setting.
2. tCK(avg).MIN limits: Since CAS Latency is not purely analog - data and strobe output are synchronized
by the DLL - all possible intermediate frequencies may not be guaranteed. CL in clock cycle is calcu-
lated from tAA following rounding algorithm defined in DDR4 Device Operation(Rounding Algorithms)
3. tCK(avg).MAX limits: Calculate tCK(avg) = tAA.MAX / CL SELECTED and round the resulting tCK(avg)
down to the next valid speed bin (i.e. 1.5ns or 1.25ns or 1.071 ns or 0.938 ns or 0.833 ns). This result
is tCK(avg).MAX corresponding to CL SELECTED.
4. ‘Reserved’ settings are not allowed. User must program a different value.
5. 'Optional' settings allow certain devices in the industry to support this setting, however, it is not a
mandatory feature. Refer to supplier's data sheet and/or the DIMM SPD information if and how this
setting is supported.
6. Any DDR4-1866 speed bin also supports functional operation at lower frequencies as shown in the
table which are not subject to Production Tests but verified by Design/Characterization.
10. DDR4-1600 AC timing apply if DRAM operates at lower than 1600 MT/s data rate.
11. Parameters apply from tCK(avg)min to tCK(avg)max at all standard JEDEC clock period values as
stated in the Speed Bin Tables.
12. CL number in parentheses, it means that these numbers are optional.
13. DDR4 SDRAM supports CL=9 as long as a system meets tAA(min).
14. Each speed bin lists the timing requirements that need to be supported in order for a given DRAM to
be JEDEC compliant. JEDEC compliance does not require support for all speed bins within a given
speed. JEDEC compliance requires meeting the parameters for a least one of the listed speed bins.
Rev. 1.2 / Jul.2017 43

Package Dimensions
Package Dimension(x4/8): 78Ball Fine Pitch Ball Grid Array Outline
7.500  0.100
A1 INDEX MARK
11.000  0.100
1.100  0.100
0.340  0.050
TOP SIDE VIEW
0.800 X 8 = 6.400
2.100  0.100
0.800
0.550  0.100
A1 BALL MARK
9 8 7 3 2 1
A
B
C
D
0.800
E
0.800 X 12 = 9.600
F
G
H
J
K
L
M
N
0.700  0.100
78 x 0.450  0.050
1.600 1.600
BOTTOM
Rev. 1.2 / Jul.2017 44

Package Dimension(x16): 96Ball Fine Pitch Ball Grid Array Outline
A1 INDEX MARK
7.500  0.100
13.000  0.100
1.100  0.100
0.340  0.050
TOP VIEW SIDE VIEW
0.800 X 8 = 6.400
0.800 0.550  0.100
2.100  0.100
9 8 7 3 2 1 A1 BALL MARK
A
B
C
D
E
0.800
0.800 X 15 = 12.000
F
G
H
J
K
L
M
N
P
R
T
0.500  0.100
1.600 1.600
96 x 0.450  0.050
BOTTOM VIEW
Rev. 1.2 / Jul.2017 45

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8Gb DDR4 SDRAM

8Gb DDR4 SDRAM

* SK hynix reserves the right to change products or specifications without notice.

Rev. 1.2 / Jul.2017 1

Revision No. History Draft Date Remark

0.01 Initial Release Oct. 2015 Priliminary

0.1 Updated JEDEC Specification Dec.2015

1.0 Updated 2133Mbps (tCK(min) : 0.938ns->0.937ns) Apr.2016

1.1 Updated IDD Specification (2133/2666Mbps) Jun.2016

1.2 Collected typo Jun.2017

Rev. 1.2 / Jul.2017 2

Device Features and Ordering Information

• Differential Data Strobe (DQS, DQS) • Asynchronous RESET pin supported

Rev. 1.2 / Jul.2017 3

Part No. Configuration Package

H5AN8G6NAFR-*xxC 512M x 16 96ball FBGA

* xx means Speed Bin Grade

Rev. 1.2 / Jul.2017 4

A VDD VSSQ NC DM_n, DBI_n VSSQ VSS A

Rev. 1.2 / Jul.2017 5

Rev. 1.2 / Jul.2017 6

A VDDQ VSSQ DQU0 DQSU_c VSSQ VDDQ A

Rev. 1.2 / Jul.2017 7

Rev. 1.2 / Jul.2017 8

Rev. 1.2 / Jul.2017 9

Rev. 1.2 / Jul.2017 10

Rev. 1.2 / Jul.2017 11

DRAM Component Operating Temperature Range

Symbol Parameter Rating Units Notes

Rev. 1.2 / Jul.2017 12

Rev. 1.2 / Jul.2017 13

Rev. 1.2 / Jul.2017 14

VDD VPP VDDQ

Rev. 1.2 / Jul.2017 15

Rev. 1.2 / Jul.2017 16

Rev. 1.2 / Jul.2017 17

Rev. 1.2 / Jul.2017 18

Rev. 1.2 / Jul.2017 19

Rev. 1.2 / Jul.2017 20

Rev. 1.2 / Jul.2017 21

... repeat pattern 1...4 until nRAS - 1, truncate if necessary

5 5*nRC repeat Sub-Loop 0, use BG[1:0]2 = 1, BA[1:0] = 2 instead

Rev. 1.2 / Jul.2017 22

... repeat pattern 1...4 until nRAS - 1, truncate if necessary

Rev. 1.2 / Jul.2017 23

5 20-23 repeat Sub-Loop 0, use BG[1:0]2 = 1, BA[1:0] = 2 instead

6 24-27 repeat Sub-Loop 0, use BG[1:0]2 = 0, BA[1:0] = 3 instead

Rev. 1.2 / Jul.2017 24

6 24-27 repeat Sub-Loop 0, but ODT = 0 and BG[1:0]2 = 0, BA[1:0] = 3 instead

Rev. 1.2 / Jul.2017 25

3 12-15 repeat Sub-Loop 1, use BG[1:0]2 = 1, BA[1:0] = 3 instead

4 16-19 repeat Sub-Loop 0, use BG[1:0]2 = 0, BA[1:0] = 1 instead

Rev. 1.2 / Jul.2017 26

3 12-15 repeat Sub-Loop 1, use BG[1:0]2 = 1, BA[1:0] = 3 instead

4 16-19 repeat Sub-Loop 0, use BG[1:0]2 = 0, BA[1:0] = 1 instead

Rev. 1.2 / Jul.2017 27

3 15-19 repeat Sub-Loop 1, use BG[1:0]2 = 1, BA[1:0] = 3 instead

Rev. 1.2 / Jul.2017 28