ST72324Jx ST72324Kx: 5V Range 8-Bit Mcu With 8 To 32K Flash, 10-Bit Adc, 4 Timers, Spi, Sci Interface

ST72324Jx ST72324Kx
5V RANGE 8-BIT MCU WITH 8 TO 32K FLASH,

10-BIT ADC, 4 TIMERS, SPI, SCI INTERFACE
NOT FOR NEW DESIGN
■ Memories
– 8 to 32K dual voltage High Density Flash (HD-
Flash) with read-out protection capability. In-
Application Programming and In-Circuit Pro-
gramming for HDFlash devices TQFP32
– 384 to 1K bytes RAM 7x7
– HDFlash endurance: 100 cycles, data reten- TQFP44
tion: 20 years at 55°C 10 x 10
■ Clock, Reset And Supply Management
– Enhanced low voltage supervisor (LVD) for
main supply with programmable reset thresh-
olds and auxiliary voltage detector (AVD) with
interrupt capability
SDIP42 SDIP32
– Clock sources: crystal/ceramic resonator os- 400 mil
cillators, internal RC oscillator, clock security 600 mil
system and bypass for external clock
– PLL for 2x frequency multiplication
– Four Power Saving Modes: Halt, Active-Halt,
Wait and Slow ■ 2 Communication Interfaces
■ Interrupt Management
– SPI synchronous serial interface
– Nested interrupt controller – SCI asynchronous serial interface
– 10 interrupt vectors plus TRAP and RESET ■ 1 Analog Peripheral (low current coupling)
– 9/6 external interrupt lines (on 4 vectors)
– 10-bit ADC with up to 12 robust input ports
■ Up to 32 I/O Ports
– 32/24 multifunctional bidirectional I/O lines
■ Instruction Set
– 22/17 alternate function lines
– 12/10 high sink outputs – 8-bit Data Manipulation
■ 4 Timers – 63 Basic Instructions
– 17 main Addressing Modes
– Main Clock Controller with: Real time base,
Beep and Clock-out capabilities – 8 x 8 Unsigned Multiply Instruction
– Configurable watchdog timer
– 16-bit Timer A with: 1 input capture, 1 output ■ Development Tools
compare, external clock input, PWM and
pulse generator modes – Full hardware/software development package
– 16-bit Timer B with: 2 input captures, 2 output – In-Circuit Testing capability
compares, PWM and pulse generator modes
Device Summary
ST72324J6 ST72324J4 ST72324J2
Features
ST72324K61 ST72324K41 ST72324JK21
Program memory -
Flash 32K Flash 16K Flash 8K
bytes
RAM (stack) - bytes 1024 (256) 512 (256) 384 (256)
Voltage Range 3.8V to 5.5V
Temp. Range up to -40°C to +125°C
Packages SDIP42, TQFP44 10x10,SDIP32, TQFP32 7x7
1For new designs in standard and industrial applications, use ST72324B(J/K) order codes, refer to separate datasheet
April 2008 Rev. 5 1/164

1
Table of Contents
1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3 REGISTER & MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4 FLASH PROGRAM MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.3 STRUCTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.3.1 Read-out Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.4 ICC INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.5 ICP (IN-CIRCUIT PROGRAMMING) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.6 IAP (IN-APPLICATION PROGRAMMING) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.7 RELATED DOCUMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.7.1 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.3 CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6 SUPPLY, RESET AND CLOCK MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.1 PHASE LOCKED LOOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.2 MULTI-OSCILLATOR (MO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6.3 RESET SEQUENCE MANAGER (RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6.3.2 Asynchronous External RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6.3.3 External Power-On RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.3.4 Internal Low Voltage Detector (LVD) RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.3.5 Internal Watchdog RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.4 SYSTEM INTEGRITY MANAGEMENT (SI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.4.1 Low Voltage Detector (LVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.4.2 Auxiliary Voltage Detector (AVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.4.3 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
7 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
7.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
7.2 MASKING AND PROCESSING FLOW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
7.3 INTERRUPTS AND LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
7.4 CONCURRENT & NESTED MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
7.5 INTERRUPT REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
7.6 EXTERNAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
7.6.1 I/O Port Interrupt Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
7.7 EXTERNAL INTERRUPT CONTROL REGISTER (EICR) . . . . . . . . . . . . . . . . . . . . . . . 38
8 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
8.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
. . . . 40
8.2 SLOW MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
8.3 WAIT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
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8.4 ACTIVE-HALT AND HALT MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
8.4.1 ACTIVE-HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
8.4.2 HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
9 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
9.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
9.2 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
9.2.1 Input Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
9.2.2 Output Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
9.2.3 Alternate Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
9.3 I/O PORT IMPLEMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
9.4 LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
9.5 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
9.5.1 I/O Port Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
10 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
10.1 WATCHDOG TIMER (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
10.1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
10.1.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
10.1.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
10.1.4 How to Program the Watchdog Timeout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
10.1.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
10.1.6 Hardware Watchdog Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
10.1.7 Using Halt Mode with the WDG (WDGHALT option) . . . . . . . . . . . . . . . . . . . . . . . 54
10.1.8 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
10.2 MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK AND BEEPER (MCC/RTC) . 56
10.2.1 Programmable CPU Clock Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
10.2.2 Clock-out Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
10.2.3 Real Time Clock Timer (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
10.2.4 Beeper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
10.2.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
10.2.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
10.3 16-BIT TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
10.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
10.3.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
10.3.4 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
10.3.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
10.3.6 Summary of Timer modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
10.4 SERIAL PERIPHERAL INTERFACE (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
10.4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
10.4.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
10.4.3 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
10.4.4 Clock Phase and Clock Polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 .... 83
10.4.5 Error Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
10.4.6 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
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10.4.7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
10.5 SERIAL COMMUNICATIONS INTERFACE (SCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
10.5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
10.5.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
10.5.3 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
10.5.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
10.5.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
10.5.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
10.6 10-BIT A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
10.6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
10.6.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
10.6.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
10.6.4 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
10.6.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
10.6.6 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
11 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
11.1 CPU ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
11.1.1 Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
11.1.2 Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
11.1.3 Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
11.1.4 Indexed (No Offset, Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
11.1.5 Indirect (Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
11.1.6 Indirect Indexed (Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
11.1.7 Relative mode (Direct, Indirect) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
11.2 INSTRUCTION GROUPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
12 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
12.1 PARAMETER CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
12.1.1 Minimum and Maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
12.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
12.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
12.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
12.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
12.2 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
12.2.1 Voltage Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
12.2.2 Current Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
12.2.3 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
12.3 OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
12.3.1 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
12.4 LVD/AVD CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
12.4.1 Operating Conditions with Low Voltage Detector (LVD) . . . . . . . . . . . . . . . . . . . . 119
12.4.2 Auxiliary Voltage Detector (AVD) Thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
12.5 SUPPLY CURRENT CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
12.5.1 CURRENT CONSUMPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 . . . 120
12.5.2 Supply and Clock Managers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
12.5.3 On-Chip Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
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12.6 CLOCK AND TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
12.6.1 General Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
12.6.2 External Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
12.6.3 Crystal and Ceramic Resonator Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
12.6.4 RC Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
12.6.5 PLL Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
12.7 MEMORY CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
12.7.1 RAM and Hardware Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
12.7.2 FLASH Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
12.8 EMC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
12.8.1 Functional EMS (Electro Magnetic Susceptibility) . . . . . . . . . . . . . . . . . . . . . . . . 130
12.8.2 Electro Magnetic Interference (EMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
12.8.3 Absolute Maximum Ratings (Electrical Sensitivity) . . . . . . . . . . . . . . . . . . . . . . . . 132
12.9 I/O PORT PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
12.9.1 General Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
12.9.2 Output Driving Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
12.10 CONTROL PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
12.10.1Asynchronous RESET Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
12.10.2ICCSEL/VPP Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
12.11 TIMER PERIPHERAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
12.11.116-Bit Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
12.12 COMMUNICATION INTERFACE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . 140
12.12.1SPI - Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
12.13 10-BIT ADC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
12.13.1Analog Power Supply and Reference Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
12.13.2General PCB Design Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
12.13.3ADC Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
13 PACKAGE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
13.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
13.2 THERMAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
13.3 SOLDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
14 ST72324 DEVICE CONFIGURATION AND ORDERING INFORMATION . . . . . . . . . . . . . . . 150
14.1 FLASH OPTION BYTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
14.2 FLASH DEVICE ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
14.3 SILICON IDENTIFICATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
14.4 DEVELOPMENT TOOLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
14.4.1 Socket and Emulator Adapter Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
14.5 ST7 APPLICATION NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
15 KNOWN LIMITATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
15.1 ALL DEVICES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
15.1.1 External RC option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
15.1.2 CSS Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
15.1.3 Safe Connection of OSC1/OSC2 Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
15.1.4 Unexpected Reset Fetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 . . . 159
15.1.5 Clearing active interrupts outside interrupt routine . . . . . . . . . . . . . . . . . . . . . . . . 159
15.1.6 External Interrupt Missed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
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15.1.7 16-bit Timer PWM Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
15.1.8 SCI Wrong Break duration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
15.2 FLASH DEVICES ONLY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
15.2.1 Internal RC Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
16 IMPORTANT NOTES ON ST72F324B FLASH DEVICES: . . . . . . . . . . . . . . . . . . . . . . . . . . 162
16.1 RESET PIN LOGIC LEVELS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
16.2 WAKE-UP FROM ACTIVE HALT MODE USING EXTERNAL INTERRUPTS . . . . . . . 162
16.3 PLL JITTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
16.4 ACTIVE HALT POWER CONSUMPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
16.5 TIMER A REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
17 REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
To obtain the most recent version of this datasheet,

please check at www.st.com>products>technical literature>datasheet.
Please also pay special attention to the Section “KNOWN LIMITATIONS” on page 159.
164
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ST72324Jx ST72324Kx
1 INTRODUCTION tion set and are available with FLASH program

memory.
The ST72324 devices are members of the ST7 mi-
crocontroller family designed for the 5V operating Under software control, all devices can be placed
range. in WAIT, SLOW, ACTIVE-HALT or HALT mode,
reducing power consumption when the application
– The 32-pin devices are designed for mid-range is in idle or stand-by state.
applications
The enhanced instruction set and addressing
– The 42/44-pin devices target the same range of modes of the ST7 offer both power and flexibility to
applications requiring more than 24 I/O ports. software developers, enabling the design of highly
For a description of the differences between efficient and compact application code. In addition
ST72324 and ST72324B devices refer to Section to standard 8-bit data management, all ST7 micro-
14.2 on page 152 controllers feature true bit manipulation, 8x8 un-
signed multiplication and indirect addressing
All devices are based on a common industry-
modes.
standard 8-bit core, featuring an enhanced instruc-
Figure 1. Device Block Diagram
8-BIT CORE PROGRAM

ALU MEMORY
(8K - 32K Bytes)
RESET
CONTROL
VPP
RAM
VSS (384 - 1024 Bytes)
VDD LVD
WATCHDOG
OSC1
OSC
OSC2
ADDRESS AND DATA BUS
MCC/RTC/BEEP
PA7:3
PORT A (5 bits on J devices)
PORT F (4 bits on K devices)
PF7:6,4,2:0
(6 bits on J devices)
(5 bits on K devices) TIMER A
PB4:0
PORT B (5 bits on J devices)
BEEP (3 bits on K devices)
PORT E
PE1:0 PORT C
(2 bits)
SCI
TIMER B PC7:0
(8 bits)
PORT D
PD5:0 SPI
(6 bits on J devices)
(2 bits on K devices) 10-BIT ADC
VAREF
VSSA
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2 PIN DESCRIPTION
Figure 2. 42-Pin SDIP and 44-Pin TQFP Package Pinouts
VPP / ICCSEL
PE0 / TDO
PA7 (HS)
PA6 (HS)
PA5 (HS)
PA4 (HS)
RESET
VDD_2
VSS_2
OSC1
OSC2
44 43 42 41 40 39 38 37 36 35 34
RDI / PE1 1 33 VSS_1
PB0 2 32 VDD_1
PB1 3 ei0 31 PA3 (HS)
ei2
PB2 4 30 PC7 / SS / AIN15
PB3 5 29 PC6 / SCK / ICCCLK
(HS) PB4 6 ei3 28 PC5 / MOSI / AIN14
AIN0 / PD0 7 27 PC4 / MISO / ICCDATA
AIN1 / PD1 8 26 PC3 (HS) / ICAP1_B
AIN2 / PD2 9 25 PC2 (HS) / ICAP2_B
AIN3 / PD3 10 ei1 24 PC1 / OCMP1_B / AIN13
AIN4 / PD4 11 23 PC0 / OCMP2_B / AIN12
12 13 14 15 16 17 18 19 20 21 22
EXTCLK_A / (HS) PF7
VAREF
BEEP / (HS) PF1

VSSA
(HS) PF2
ICAP1_A / (HS) PF6
VDD_0
VSS_0
AIN5 / PD5
MCO / AIN8 / PF0
OCMP1_A / AIN10 / PF4
(HS) PB4 1 ei3 42 PB3

AIN0 / PD0 2 41 PB2
AIN1 / PD1 3 ei2 PB1
40
AIN2 / PD2 4 39 PB0
AIN3 / PD3 5 38 PE1 / RDI
AIN4 / PD4 6 37 PE0 / TDO
AIN5 / PD5 7 36 VDD_2
VAREF 8 35 OSC1
VSSA 9 34 OSC2
MCO / AIN8 / PF0 10 33 VSS_2
BEEP / (HS) PF1 11 ei1 32 RESET
(HS) PF2 12 31 VPP / ICCSEL
AIN10 / OCMP1_A / PF4 13 30 PA7 (HS)
ICAP1_A / (HS) PF6 14 29 PA6 (HS)
EXTCLK_A / (HS) PF7 15 28 PA5 (HS)
AIN12 / OCMP2_B / PC0 16 27 PA4 (HS)
AIN13 / OCMP1_B / PC1 17 26 VSS_1
ICAP2_B/ (HS) PC2 18 25 VDD_1
ICAP1_B / (HS) PC3 19 ei0 24 PA3 (HS)
ICCDATA / MISO / PC4 20 23 PC7 / SS / AIN15
AIN14 / MOSI / PC5 21 22 PC6 / SCK / ICCCLK
(HS) 20mA high sink capability
eix associated external interrupt vector
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ST72324Jx ST72324Kx
PIN DESCRIPTION (Cont’d)

Figure 3. 32-Pin SDIP Package Pinout
(HS) PB4 1 PB3

ei3 32
AIN0 / PD0 ei2 PB0
2 31
AIN1 / PD1 3 30 PE1 / RDI
VAREF 4 29 PE0 / TDO
VSSA 5 28 VDD_2
MCO / AIN8 / PF0 6 27 OSC1
ei1
BEEP / (HS) PF1 7 26 OSC2
OCMP1_A / AIN10 / PF4 8 25 VSS_2
ICAP1_A / (HS) PF6 9 24 RESET
EXTCLK_A / (HS) PF7 10 23 VPP / ICCSEL
AIN12 / OCMP2_B / PC0 11 22 PA7 (HS)
AIN13 / OCMP1_B / PC1 12 21 PA6 (HS)
ICAP2_B / (HS) PC2 13 20 PA4 (HS)
ICAP1_B / (HS) PC3 14 ei0 19 PA3 (HS)
ICCDATA/ MISO / PC4 15 18 PC7 / SS / AIN15
AIN14 / MOSI / PC5 16 17 PC6 / SCK / ICCCLK
Figure 4. 32-Pin TQFP 7x7 Package Pinout

PD1 / AIN1
PD0 / AIN0
PE0 / TDO
PE1 / RDI
PB4 (HS)
VDD_2
PB3
PB0
32 31 30 29 28 27 26 25
VAREF 1 24 OSC1
ei3 ei2
VSSA 2 23 OSC2
MCO / AIN8 / PF0 3 22 VSS_2
ei1
BEEP / (HS) PF1 4 21 RESET
OCMP1_A / AIN10 / PF4 5 20 VPP / ICCSEL
ICAP1_A / (HS) PF6 6 19 PA7 (HS)
EXTCLK_A / (HS) PF7 7 18 PA6 (HS)
AIN12 / OCMP2_B / PC0 8 ei0 17 PA4 (HS)
9 10 11 12 13 14 15 16
ICCCLK / SCK / PC6
ICAP2_B / (HS) PC2
ICAP1_B / (HS) PC3
AIN15 / SS / PC7
(HS) PA3
ICCDATA / MISO / PC4
AIN14 / MOSI / PC5
AIN13 / OCMP1_B / PC1

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PIN DESCRIPTION (Cont’d)

For external pin connection guidelines, refer to See “ELECTRICAL CHARACTERISTICS” on page 116.
Legend / Abbreviations for Table 1:
Type: I = input, O = output, S = supply
Input level: A = Dedicated analog input
In/Output level: C = CMOS 0.3VDD/0.7VDD
CT= CMOS 0.3VDD/0.7VDD with input trigger
Output level: HS = 20mA high sink (on N-buffer only)
Port and control configuration:
– Input: float = floating, wpu = weak pull-up, int = interrupt 1), ana = analog ports
– Output: OD = open drain 2), PP = push-pull
Refer to “I/O PORTS” on page 45 for more details on the software configuration of the I/O ports.
The RESET configuration of each pin is shown in bold. This configuration is valid as long as the device is
in reset state.
Table 1. Device Pin Description
Pin n° Level Port
Main
Type
function
TQFP44
TQFP32
Input Output
SDIP42
SDIP32
Output
Pin Name Alternate Function

Input
(after
float
wpu
ana
reset)
OD
PP
int
6 1 30 1 PB4 (HS) I/O CT HS X ei3 X X Port B4

7 2 31 2 PD0/AIN0 I/O CT X X X X X Port D0 ADC Analog Input 0
8 3 32 3 PD1/AIN1 I/O CT X X X X X Port D1 ADC Analog Input 1
9 4 PD2/AIN2 I/O CT X X X X X Port D2 ADC Analog Input 2
13 8 1 4 VAREF S Analog Reference Voltage for ADC
14 9 2 5 VSSA S Analog Ground Voltage
Main clock ADC Analog
15 10 3 6 PF0/MCO/AIN8 I/O CT X ei1 X X X Port F0
out (fCPU) Input 8
16 11 4 7 PF1 (HS)/BEEP I/O CT HS X ei1 X X Port F1 Beep signal output
17 12 PF2 (HS) I/O CT HS X ei1 X X Port F2
Timer A Out-
PF4/OCMP1_A/ ADC Analog
18 13 5 8 I/O CT X X X X X Port F4 put Com-
AIN10 Input 10
pare 1
19 14 6 9 PF6 (HS)/ICAP1_A I/O CT HS X X X X Port F6 Timer A Input Capture 1
PF7 (HS)/ Timer A External Clock
20 15 7 10 I/O CT HS X X X X Port F7
EXTCLK_A Source
21 VDD_0 S Digital Main Supply Voltage
22 VSS_0 S Digital Ground Voltage
Timer B Out-
PC0/OCMP2_B/ ADC Analog
23 16 8 11 I/O CT X X X X X Port C0 put Com-
AIN12 Input 12
pare 2
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ST72324Jx ST72324Kx
Pin n° Level Port

Main
Type
function
TQFP44
TQFP32
Input Output
SDIP42
SDIP32
Output
Pin Name Alternate Function
Input
(after
float
wpu
ana
reset)
OD
PP
int
Timer B Out-
PC1/OCMP1_B/ ADC Analog
24 17 9 12 I/O CT X X X X X Port C1 put Com-
AIN13 Input 13
pare 1
25 18 10 13 PC2 (HS)/ICAP2_B I/O CT HS X X X X Port C2 Timer B Input Capture 2
26 19 11 14 PC3 (HS)/ICAP1_B I/O CT HS X X X X Port C3 Timer B Input Capture 1
SPI Master
PC4/MISO/ICCDA- ICC Data In-
27 20 12 15 I/O CT X X X X Port C4 In / Slave
TA put
Out Data
SPI Master
ADC Analog
28 21 13 16 PC5/MOSI/AIN14 I/O CT X X X X X Port C5 Out / Slave
Input 14
In Data
SPI Serial ICC Clock
29 22 14 17 PC6/SCK/ICCCLK I/O CT X X X X Port C6
Clock Output
SPI Slave
ADC Analog
30 23 15 18 PC7/SS/AIN15 I/O CT X X X X X Port C7 Select (ac-
Input 15
tive low)
31 24 16 19 PA3 (HS) I/O CT HS X ei0 X X Port A3
32 25 VDD_1 S Digital Main Supply Voltage
33 26 VSS_1 S Digital Ground Voltage
34 27 17 20 PA4 (HS) I/O CT HS X X X X Port A4
35 28 PA5 (HS) I/O CT HS X X X X Port A5
36 29 18 21 PA6 (HS) I/O CT HS X T Port A6 1)
37 30 19 22 PA7 (HS) I/O CT HS X T Port A7 1)
Must be tied low. In the flash pro-
gramming mode, this pin acts as the
38 31 20 23 VPP /ICCSEL I
programming voltage input VPP. See
Section 12.10.2 for more details.
39 32 21 24 RESET I/O CT Top priority non maskable interrupt.
40 33 22 25 VSS_2 S Digital Ground Voltage
41 34 23 26 OSC2 O Resonator oscillator inverter output
External clock input or Resonator os-
42 35 24 27 OSC1 I
cillator inverter input
43 36 25 28 VDD_2 S Digital Main Supply Voltage
44 37 26 29 PE0/TDO I/O CT X X X X Port E0 SCI Transmit Data Out
1 38 27 30 PE1/RDI I/O CT X X X X Port E1 SCI Receive Data In
Caution: Negative current
2 39 28 31 PB0 I/O CT X ei2 X X Port B0 injection not allowed on this
pin5)
3 40 PB1 I/O CT X ei2 X X Port B1
4 41 PB2 I/O CT X ei2 X X Port B2
5 42 29 32 PB3 I/O CT X ei2 X X Port B3
Notes:
1. In the interrupt input column, “eiX” defines the associated external interrupt vector. If the weak pull-up
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column (wpu) is merged with the interrupt column (int), then the I/O configuration is pull-up interrupt input,
else the configuration is floating interrupt input.
2. In the open drain output column, “T” defines a true open drain I/O (P-Buffer and protection diode to VDD
are not implemented). See See “I/O PORTS” on page 45. and Section 12.9 I/O PORT PIN CHARACTER-
ISTICS for more details.
3. OSC1 and OSC2 pins connect a crystal/ceramic resonator, or an external source to the on-chip oscil-
lator; see Section 1 INTRODUCTION and Section 12.6 CLOCK AND TIMING CHARACTERISTICS for
more details.
4. On the chip, each I/O port has 8 pads. Pads that are not bonded to external pins are in input pull-up con-
figuration after reset. The configuration of these pads must be kept at reset state to avoid added current
consumption.
5. For details refer to Section 12.9.1 on page 133
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ST72324Jx ST72324Kx
3 REGISTER & MEMORY MAP

As shown in Figure 5, the MCU is capable of ad- The highest address bytes contain the user reset
dressing 64K bytes of memories and I/O registers. and interrupt vectors.
The available memory locations consist of 128 IMPORTANT: Memory locations marked as “Re-
bytes of register locations, up to 1024 bytes of served” must never be accessed. Accessing a re-
RAM and up to 32 Kbytes of user program memo- served area can have unpredictable effects on the
ry. The RAM space includes up to 256 bytes for device.
the stack from 0100h to 01FFh.
Figure 5. Memory Map
0000h 0080h
HW Registers
Short Addressing
(see Table 2)
007Fh RAM (zero page)
0080h 00FFh
0100h
RAM 256 Bytes Stack
(1024,
01FFh
512 or 384 Bytes)
0200h
047Fh 16-bit Addressing
0480h
Reserved RAM
027Fh
7FFFh
8000h or 047Fh
8000h
Program Memory 32 KBytes
(32K, 16K or 8K) C000h
FFDFh 16 KBytes
FFE0h E000h
Interrupt & Reset Vectors 8 Kbytes
(see Table 8) FFFFh
FFFFh
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Table 2. Hardware Register Map
Register Reset
Address Block Register Name Remarks
Label Status
0000h PADR Port A Data Register 00h1) R/W

0001h Port A 2) PADDR Port A Data Direction Register 00h R/W
0002h PAOR Port A Option Register 00h R/W
0003h PBDR Port B Data Register 00h1) R/W

2)
0004h Port B PBDDR Port B Data Direction Register 00h R/W
0005h PBOR Port B Option Register 00h R/W
0006h PCDR Port C Data Register 00h1) R/W

0007h Port C PCDDR Port C Data Direction Register 00h R/W
0008h PCOR Port C Option Register 00h R/W
0009h PDADR Port D Data Register 00h1) R/W

2)
000Ah Port D PDDDR Port D Data Direction Register 00h R/W
000Bh PDOR Port D Option Register 00h R/W
000Ch PEDR Port E Data Register 00h1) R/W

2)
000Dh Port E PEDDR Port E Data Direction Register 00h R/W2)
000Eh PEOR Port E Option Register 00h R/W2)
000Fh PFDR Port F Data Register 00h1) R/W

0010h Port F 2) PFDDR Port F Data Direction Register 00h R/W
0011h PFOR Port F Option Register 00h R/W
0012h
to Reserved Area (15 Bytes)
0020h
0021h SPIDR SPI Data I/O Register xxh R/W

0022h SPI SPICR SPI Control Register 0xh R/W
0023h SPICSR SPI Control/Status Register 00h R/W
0024h ISPR0 Interrupt Software Priority Register 0 FFh R/W

ITC
0028h EICR External Interrupt Control Register 00h R/W
0029h FLASH FCSR Flash Control/Status Register 00h R/W
002Ah WATCHDOG WDGCR Watchdog Control Register 7Fh R/W
002Bh SI SICSR System Integrity Control Status Register xxh R/W
002Ch MCCSR Main Clock Control / Status Register 00h R/W

MCC
002Dh MCCBCR Main Clock Controller: Beep Control Register 00h R/W
002Eh
0030h
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ST72324Jx ST72324Kx
Register Reset
Address Block Register Name Remarks
Label Status
0031h TACR2 Timer A Control Register 2 00h R/W

0032h TACR1 Timer A Control Register 1 00h R/W
0033h TACSR Timer A Control/Status Register3)4) xxxx x0xxb R/W
0034h TAIC1HR Timer A Input Capture 1 High Register xxh Read Only
0035h TAIC1LR Timer A Input Capture 1 Low Register xxh Read Only
0036h TAOC1HR Timer A Output Compare 1 High Register 80h R/W
0037h TAOC1LR Timer A Output Compare 1 Low Register 00h R/W
0038h TIMER A TACHR Timer A Counter High Register FFh Read Only
0039h TACLR Timer A Counter Low Register FCh Read Only
003Ah TAACHR Timer A Alternate Counter High Register FFh Read Only
003Bh TAACLR Timer A Alternate Counter Low Register FCh Read Only
003Ch TAIC2HR Timer A Input Capture 2 High Register3) xxh Read Only
003Dh TAIC2LR Timer A Input Capture 2 Low Register3) xxh Read Only
003Eh TAOC2HR Timer A Output Compare 2 High Register4) 80h R/W
003Fh TAOC2LR Timer A Output Compare 2 Low Register4) 00h R/W
0040h Reserved Area (1 Byte)
0041h TBCR2 Timer B Control Register 2 00h R/W

0042h TBCR1 Timer B Control Register 1 00h R/W
0043h TBCSR Timer B Control/Status Register xxxx x0xxb R/W
0044h TBIC1HR Timer B Input Capture 1 High Register xxh Read Only
0045h TBIC1LR Timer B Input Capture 1 Low Register xxh Read Only
0046h TBOC1HR Timer B Output Compare 1 High Register 80h R/W
0047h TBOC1LR Timer B Output Compare 1 Low Register 00h R/W
0048h TIMER B TBCHR Timer B Counter High Register FFh Read Only
0049h TBCLR Timer B Counter Low Register FCh Read Only
004Ah TBACHR Timer B Alternate Counter High Register FFh Read Only
004Bh TBACLR Timer B Alternate Counter Low Register FCh Read Only
004Ch TBIC2HR Timer B Input Capture 2 High Register xxh Read Only
004Dh TBIC2LR Timer B Input Capture 2 Low Register xxh Read Only
004Eh TBOC2HR Timer B Output Compare 2 High Register 80h R/W
004Fh TBOC2LR Timer B Output Compare 2 Low Register 00h R/W
0050h SCISR SCI Status Register C0h Read Only

0051h SCIDR SCI Data Register xxh R/W
0052h SCIBRR SCI Baud Rate Register 00h R/W
0053h SCICR1 SCI Control Register 1 x000 0000h R/W
SCI
0054h SCICR2 SCI Control Register 2 00h R/W
0055h SCIERPR SCI Extended Receive Prescaler Register 00h R/W
0056h Reserved area ---
0057h SCIETPR SCI Extended Transmit Prescaler Register 00h R/W
0058h
006Fh
0070h ADCCSR Control/Status Register 00h R/W

0071h ADC ADCDRH Data High Register 00h Read Only
0072h ADCDRL Data Low Register 00h Read Only
0073h
Reserved Area (13 Bytes)
007Fh
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ST72324Jx ST72324Kx
Legend: x=undefined, R/W=read/write

Notes:
1. The contents of the I/O port DR registers are readable only in output configuration. In input configura-
tion, the values of the I/O pins are returned instead of the DR register contents.
2. The bits associated with unavailable pins must always keep their reset value.
3. The Timer A Input Capture 2 pin is not available (not bonded).
– In Flash devices:
The TAIC2HR and TAIC2LR registers are not present. Bit 5 of the TACSR register (ICF2) is forced
by hardware to 0. Consequently, the corresponding interrupt cannot be used.
4. The Timer A Output Compare 2 pin is not available (not bonded).
– The TAOC2HR and TAOC2LR Registers are write only, reading them will return undefined values.
Bit 4 of the TACSR register (OCF2) is forced by hardware to 0. Consequently, the corresponding in-
terrupt cannot be used.
Caution: The TAIC2HR and TAIC2LR registers and the ICF2 and OCF2 flags are not present in Flash de-
vices but are present in the emulator. For compatibility with the emulator, it is recommended to perform a
dummy access (read or write) to the TAIC2LR and TAOC2LR registers to clear the interrupt flags.
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4 FLASH PROGRAM MEMORY
4.1 Introduction Depending on the overall Flash memory size in the

microcontroller device, there are up to three user
The ST7 dual voltage High Density Flash sectors (see Table 3). Each of these sectors can
(HDFlash) is a non-volatile memory that can be be erased independently to avoid unnecessary
electrically erased as a single block or by individu- erasing of the whole Flash memory when only a
al sectors and programmed on a Byte-by-Byte ba- partial erasing is required.
sis using an external VPP supply.
The first two sectors have a fixed size of 4 Kbytes
The HDFlash devices can be programmed and (see Figure 6). They are mapped in the upper part
erased off-board (plugged in a programming tool) of the ST7 addressing space so the reset and in-
or on-board using ICP (In-Circuit Programming) or terrupt vectors are located in Sector 0 (F000h-
IAP (In-Application Programming). FFFFh).
The array matrix organisation allows each sector
to be erased and reprogrammed without affecting Table 3. Sectors available in Flash devices
other sectors.
Flash Size (bytes) Available Sectors
4.2 Main Features 4K Sector 0

8K Sectors 0,1
■ Three Flash programming modes:
> 8K Sectors 0,1, 2
– Insertion in a programming tool. In this mode,
all sectors including option bytes can be pro-
grammed or erased. 4.3.1 Read-out Protection
– ICP (In-Circuit Programming). In this mode, all Read-out protection, when selected, provides a
sectors including option bytes can be pro-
grammed or erased without removing the de- protection against Program Memory content ex-
vice from the application board. traction and against write access to Flash memo-
– IAP (In-Application Programming) In this ry. Even if no protection can be considered as to-
mode, all sectors except Sector 0, can be pro- tally unbreakable, the feature provides a very high
grammed or erased without removing the de- level of protection for a general purpose microcon-
vice from the application board and while the troller.
application is running.
■ ICT (In-Circuit Testing) for downloading and In flash devices, this protection is removed by re-
executing user application test patterns in RAM programming the option. In this case, the entire
program memory is first automatically erased.
■ Read-out protection
Read-out protection selection depends on the de-
■ Register Access Security System (RASS) to
prevent accidental programming or erasing vice type:
– In Flash devices it is enabled and removed
through the FMP_R bit in the option byte.
4.3 Structure
– In ROM devices it is enabled by mask option
The Flash memory is organised in sectors and can specified in the Option List.
be used for both code and data storage.
Figure 6. Memory Map and Sector Address
4K 8K 10K 16K 24K 32K 48K 60K FLASH
1000h MEMORY SIZE
3FFFh
7FFFh
9FFFh
SECTOR 2
BFFFh
D7FFh
2 Kbytes 8 Kbytes 16 Kbytes 24 Kbytes 40 Kbytes 52 Kbytes
DFFFh
EFFFh
4 Kbytes SECTOR 1
FFFFh
4 Kbytes SECTOR 0
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FLASH PROGRAM MEMORY (Cont’d)
4.4 ICC Interface – ICCCLK: ICC output serial clock pin

– ICCDATA: ICC input/output serial data pin
ICC needs a minimum of 4 and up to 6 pins to be
connected to the programming tool (see Figure 7). – ICCSEL/VPP: programming voltage
These pins are: – OSC1(or OSCIN): main clock input for exter-
nal source (optional)
– RESET: device reset – VDD: application board power supply (option-
– VSS: device power supply ground al, see Figure 7, Note 3)
Figure 7. Typical ICC Interface
PROGRAMMING TOOL
ICC CONNECTOR
ICC Cable
APPLICATION BOARD
(See Note 3) ICC CONNECTOR

OPTIONAL HE10 CONNECTOR TYPE
IN SOME CASES 9 7 5 3 1
(See Note 4)
10 8 6 4 2
APPLICATION
RESET SOURCE
See Note 2
10kΩ
APPLICATION CL2 CL1

POWER SUPPLY See Note 1
APPLICATION
I/O
RESET
ICCCLK
ICCDATA
OSC1
ICCSEL/VPP
OSC2
VSS
VDD
ST7
Notes:
1. If the ICCCLK or ICCDATA pins are only used sistor>1K, no additional components are needed.
as outputs in the application, no signal isolation is In all cases the user must ensure that no external
necessary. As soon as the Programming Tool is reset is generated by the application during the
plugged to the board, even if an ICC session is not ICC session.
in progress, the ICCCLK and ICCDATA pins are 3. The use of Pin 7 of the ICC connector depends
not available for the application. If they are used as on the Programming Tool architecture. This pin
inputs by the application, isolation such as a serial must be connected when using most ST Program-
resistor has to implemented in case another de- ming Tools (it is used to monitor the application
vice forces the signal. Refer to the Programming power supply). Please refer to the Programming
Tool documentation for recommended resistor val- Tool manual.
ues.
4. Pin 9 has to be connected to the OSC1 or OS-
2. During the ICC session, the programming tool CIN pin of the ST7 when the clock is not available
must control the RESET pin. This can lead to con- in the application or if the selected clock option is
flicts between the programming tool and the appli- not programmed in the option byte. ST7 devices
cation reset circuit if it drives more than 5mA at with multi-oscillator capability need to have OSC2
high level (push pull output or pull-up resistor<1K). grounded in this case.
A schottky diode can be used to isolate the appli-
cation RESET circuit in this case. When using a
classical RC network with R>1K or a reset man-
agement IC with open drain output and pull-up re-
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FLASH PROGRAM MEMORY (Cont’d)
4.5 ICP (In-Circuit Programming) possible to download code from the SPI, SCI, USB
or CAN interface and program it in the Flash. IAP
To perform ICP the microcontroller must be mode can be used to program any of the Flash
switched to ICC (In-Circuit Communication) mode sectors except Sector 0, which is write/erase pro-
by an external controller or programming tool. tected to allow recovery in case errors occur dur-
Depending on the ICP code downloaded in RAM, ing the programming operation.
Flash memory programming can be fully custom-
ized (number of bytes to program, program loca- 4.7 Related Documentation
tions, or selection serial communication interface
for downloading). For details on Flash programming and ICC proto-
When using an STMicroelectronics or third-party col, refer to the ST7 Flash Programming Refer-
programming tool that supports ICP and the spe- ence Manual and to the ST7 ICC Protocol Refer-
cific microcontroller device, the user needs only to ence Manual.
implement the ICP hardware interface on the ap- 4.7.1 Register Description
plication board (see Figure 7). For more details on FLASH CONTROL/STATUS REGISTER (FCSR)
the pin locations, refer to the device pinout de-
scription. Read/Write
Reset Value: 0000 0000 (00h)
4.6 IAP (In-Application Programming)
7 0
This mode uses a BootLoader program previously
stored in Sector 0 by the user (in ICP mode or by
0 0 0 0 0 0 0 0
plugging the device in a programming tool).
This mode is fully controlled by user software. This
allows it to be adapted to the user application, (us- This register is reserved for use by Programming
er-defined strategy for entering programming Tool software. It controls the Flash programming
mode, choice of communications protocol used to and erasing operations.
fetch the data to be stored, etc.). For example, it is
Table 4. Flash Control/Status Register Address and Reset Value
Address Register
7 6 5 4 3 2 1 0
(Hex.) Label
FCSR
0029h
Reset Value 0 0 0 0 0 0 0 0
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5 CENTRAL PROCESSING UNIT
5.1 INTRODUCTION 5.3 CPU REGISTERS

This CPU has a full 8-bit architecture and contains The 6 CPU registers shown in Figure 8 are not
six internal registers allowing efficient 8-bit data present in the memory mapping and are accessed
manipulation. by specific instructions.
Accumulator (A)
5.2 MAIN FEATURES The Accumulator is an 8-bit general purpose reg-
■ Enable executing 63 basic instructions ister used to hold operands and the results of the
arithmetic and logic calculations and to manipulate
■ Fast 8-bit by 8-bit multiply data.
■ 17 main addressing modes (with indirect
Index Registers (X and Y)
addressing mode)
■ Two 8-bit index registers These 8-bit registers are used to create effective
addresses or as temporary storage areas for data
■ 16-bit stack pointer manipulation. (The Cross-Assembler generates a
■ Low power HALT and WAIT modes precede instruction (PRE) to indicate that the fol-
■ Priority maskable hardware interrupts lowing instruction refers to the Y register.)
■ Non-maskable software/hardware interrupts The Y register is not affected by the interrupt auto-
matic procedures.
Program Counter (PC)
The program counter is a 16-bit register containing
the address of the next instruction to be executed
by the CPU. It is made of two 8-bit registers PCL
(Program Counter Low which is the LSB) and PCH
(Program Counter High which is the MSB).
Figure 8. CPU Registers
7 0
ACCUMULATOR
RESET VALUE = XXh
7 0
X INDEX REGISTER
RESET VALUE = XXh
7 0
Y INDEX REGISTER
RESET VALUE = XXh
15 PCH 8 7 PCL 0
PROGRAM COUNTER
RESET VALUE = RESET VECTOR @ FFFEh-FFFFh
7 0
1 1 I1 H I0 N Z C CONDITION CODE REGISTER
RESET VALUE = 1 1 1 X 1 X X X
15 8 7 0
STACK POINTER
RESET VALUE = STACK HIGHER ADDRESS
X = Undefined Value
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CENTRAL PROCESSING UNIT (Cont’d)

Condition Code Register (CC) Bit 1 = Z Zero.
Read/Write This bit is set and cleared by hardware. This bit in-
Reset Value: 111x1xxx dicates that the result of the last arithmetic, logical
or data manipulation is zero.
7 0 0: The result of the last operation is different from
zero.
1 1 I1 H I0 N Z C 1: The result of the last operation is zero.
This bit is accessed by the JREQ and JRNE test
The 8-bit Condition Code register contains the in- instructions.
terrupt masks and four flags representative of the
Bit 0 = C Carry/borrow.
result of the instruction just executed. This register
can also be handled by the PUSH and POP in- This bit is set and cleared by hardware and soft-
structions. ware. It indicates an overflow or an underflow has
occurred during the last arithmetic operation.
These bits can be individually tested and/or con- 0: No overflow or underflow has occurred.
trolled by specific instructions. 1: An overflow or underflow has occurred.
Arithmetic Management Bits This bit is driven by the SCF and RCF instructions
Bit 4 = H Half carry. and tested by the JRC and JRNC instructions. It is
also affected by the “bit test and branch”, shift and
This bit is set by hardware when a carry occurs be- rotate instructions.
tween bits 3 and 4 of the ALU during an ADD or
ADC instructions. It is reset by hardware during Interrupt Management Bits
the same instructions.
Bit 5,3 = I1, I0 Interrupt
0: No half carry has occurred.
1: A half carry has occurred. The combination of the I1 and I0 bits gives the cur-
rent interrupt software priority.
This bit is tested using the JRH or JRNH instruc-
tion. The H bit is useful in BCD arithmetic subrou- Interrupt Software Priority I1 I0
tines. Level 0 (main) 1 0
Bit 2 = N Negative. Level 1 0 1
Level 2 0 0
This bit is set and cleared by hardware. It is repre-
sentative of the result sign of the last arithmetic, Level 3 (= interrupt disable) 1 1
logical or data manipulation. It’s a copy of the re- These two bits are set/cleared by hardware when
sult 7th bit. entering in interrupt. The loaded value is given by
0: The result of the last operation is positive or null. the corresponding bits in the interrupt software pri-
1: The result of the last operation is negative ority registers (IxSPR). They can be also set/
(i.e. the most significant bit is a logic 1). cleared by software with the RIM, SIM, IRET,
This bit is accessed by the JRMI and JRPL instruc- HALT, WFI and PUSH/POP instructions.
tions. See the interrupt management chapter for more
details.
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CENTRAL PROCESSING UNIT (Cont’d)

Stack Pointer (SP) The least significant byte of the Stack Pointer
Read/Write (called S) can be directly accessed by a LD in-
struction.
Reset Value: 01 FFh
Note: When the lower limit is exceeded, the Stack
15 8
Pointer wraps around to the stack upper limit, with-
out indicating the stack overflow. The previously
stored information is then overwritten and there-
0 0 0 0 0 0 0 1 fore lost. The stack also wraps in case of an under-
flow.
7 0
The stack is used to save the return address dur-
ing a subroutine call and the CPU context during
SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0
an interrupt. The user may also directly manipulate
the stack by means of the PUSH and POP instruc-
tions. In the case of an interrupt, the PCL is stored
The Stack Pointer is a 16-bit register which is al- at the first location pointed to by the SP. Then the
ways pointing to the next free location in the stack. other registers are stored in the next locations as
It is then decremented after data has been pushed shown in Figure 9.
onto the stack and incremented before data is
popped from the stack (see Figure 9). – When an interrupt is received, the SP is decre-
mented and the context is pushed on the stack.
Since the stack is 256 bytes deep, the 8 most sig-
nificant bits are forced by hardware. Following an – On return from interrupt, the SP is incremented
MCU Reset, or after a Reset Stack Pointer instruc- and the context is popped from the stack.
tion (RSP), the Stack Pointer contains its reset val- A subroutine call occupies two locations and an in-
ue (the SP7 to SP0 bits are set) which is the stack terrupt five locations in the stack area.
higher address.
Figure 9. Stack Manipulation Example
CALL Interrupt PUSH Y POP Y IRET RET
Subroutine Event or RSP
@ 0100h
SP
SP SP
Y
CC CC CC
A A A
X X X
PCH PCH PCH
SP SP
PCL PCL PCL
PCH PCH PCH PCH PCH
SP
@ 01FFh PCL PCL PCL PCL PCL
Stack Higher Address = 01FFh

Stack Lower Address = 0100h
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6 SUPPLY, RESET AND CLOCK MANAGEMENT

The device includes a range of utility features for 6.1 PHASE LOCKED LOOP
securing the application in critical situations (for
example in case of a power brown-out), and re- If the clock frequency input to the PLL is in the
ducing the number of external components. An range 2 to 4 MHz, the PLL can be used to multiply
overview is shown in Figure 11. the frequency by two to obtain an fOSC2 of 4 to 8
MHz. The PLL is enabled by option byte. If the PLL
For more details, refer to dedicated parametric is disabled, then fOSC2 = fOSC/2.
section.
Caution: The PLL is not recommended for appli-
Main features cations where timing accuracy is required.
■ Optional PLL for multiplying the frequency by 2 Caution: The PLL must not be used with the inter-
(not to be used with internal RC oscillator in nal RC oscillator.
order to respect the max. operating frequency)
■ Reset Sequence Manager (RSM)
■ Multi-Oscillator Clock Management (MO)

Figure 10. PLL Block Diagram
– 5 Crystal/Ceramic resonator oscillators
– 1 Internal RC oscillator PLL x 2 0
■ System Integrity Management (SI) fOSC
fOSC2
– Main supply Low voltage detection (LVD) /2 1
– Auxiliary Voltage detector (AVD) with interrupt
capability for monitoring the main supply PLL OPTION BIT
Figure 11. Clock, Reset and Supply Block Diagram
OSC2 MULTI- fOSC fOSC2 MAIN CLOCK fCPU

CONTROLLER
OSCILLATOR PLL WITH REALTIME
OSC1 (option)
(MO) CLOCK (MCC/RTC)
SYSTEM INTEGRITY MANAGEMENT
RESET SEQUENCE AVD Interrupt Request WATCHDOG

RESET MANAGER SICSR TIMER (WDG)
(RSM) AVD AVD LVD WDG
0 0 0 0
IE F RF RF
LOW VOLTAGE
VSS DETECTOR
VDD (LVD)
AUXILIARY VOLTAGE
DETECTOR
(AVD)
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6.2 MULTI-OSCILLATOR (MO)

The main clock of the ST7 can be generated by Internal RC Oscillator
three different source types coming from the multi- This oscillator allows a low cost solution for the
oscillator block: main clock of the ST7 using only an internal resis-
■ an external source tor and capacitor. Internal RC oscillator mode has
■ 4 crystal or ceramic resonator oscillators the drawback of a lower frequency accuracy and
■ an internal high frequency RC oscillator
should not be used in applications that require ac-
curate timing.
Each oscillator is optimized for a given frequency
range in terms of consumption and is selectable In this mode, the two oscillator pins have to be tied
through the option byte. The associated hardware to ground.
configurations are shown in Table 5. Refer to the In order not to exceed the max. operating frequen-
electrical characteristics section for more details. cy, the internal RC oscillator must not be used with
Caution: The OSC1 and/or OSC2 pins must not the PLL.
be left unconnected. For the purposes of Failure Table 5. ST7 Clock Sources
Mode and Effect Analysis, it should be noted that if
the OSC1 and/or OSC2 pins are left unconnected, Hardware Configuration
the ST7 main oscillator may start and, in this con-
figuration, could generate an fOSC clock frequency
in excess of the allowed maximum (>16MHz.), ST7
External Clock
putting the ST7 in an unsafe/undefined state. The OSC1 OSC2

product behaviour must therefore be considered
undefined when the OSC pins are left unconnect-
ed.
External Clock Source EXTERNAL
SOURCE
In this external clock mode, a clock signal (square,
sinus or triangle) with ~50% duty cycle has to drive
Crystal/Ceramic Resonators
the OSC1 pin while the OSC2 pin is tied to ground.

ST7
Crystal/Ceramic Oscillators OSC1 OSC2
This family of oscillators has the advantage of pro-
ducing a very accurate rate on the main clock of
the ST7. The selection within a list of 4 oscillators
with different frequency ranges has to be done by
option byte in order to reduce consumption (refer CL1 CL2
to Section 14.1 on page 150 for more details on LOAD
the frequency ranges). In this mode of the multi- CAPACITORS
oscillator, the resonator and the load capacitors
have to be placed as close as possible to the oscil-
Internal RC Oscillator
lator pins in order to minimize output distortion and ST7

start-up stabilization time. The loading capaci- OSC1 OSC2
tance values must be adjusted according to the
selected oscillator.
These oscillators are not stopped during the
RESET phase to avoid losing time in the oscillator
start-up phase.
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6.3 RESET SEQUENCE MANAGER (RSM)

6.3.1 Introduction The RESET vector fetch phase duration is 2 clock
The reset sequence manager includes three RE- cycles.
SET sources as shown in Figure 13: Figure 12. RESET Sequence Phases
■ External RESET source pulse
■ Internal LVD RESET (Low Voltage Detection)
■ Internal WATCHDOG RESET RESET

These sources act on the RESET pin and it is al- INTERNAL RESET FETCH
Active Phase
ways kept low during the delay phase. 256 or 4096 CLOCK CYCLES VECTOR
The RESET service routine vector is fixed at ad-

dresses FFFEh-FFFFh in the ST7 memory map.
6.3.2 Asynchronous External RESET pin
The basic RESET sequence consists of 3 phases
as shown in Figure 12: The RESET pin is both an input and an open-drain
output with integrated RON weak pull-up resistor.
■ Active Phase depending on the RESET source
This pull-up has no fixed value but varies in ac-
■ 256 or 4096 CPU clock cycle delay (selected by cordance with the input voltage. It can be pulled
option byte) low by external circuitry to reset the device. See
■ RESET vector fetch Electrical Characteristic section for more details.
The 256 or 4096 CPU clock cycle delay allows the A RESET signal originating from an external
oscillator to stabilise and ensures that recovery source must have a duration of at least th(RSTL)in in
has taken place from the Reset state. The shorter order to be recognized (see Figure 14). This de-
or longer clock cycle delay should be selected by tection is asynchronous and therefore the MCU
option byte to correspond to the stabilization time can enter reset state even in HALT mode.
of the external oscillator used in the application.
Figure 13. Reset Block Diagram
VDD
RON
Filter INTERNAL
RESET
RESET
PULSE WATCHDOG RESET

GENERATOR LVD RESET
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ST72324Jx ST72324Kx
RESET SEQUENCE MANAGER (Cont’d)

The RESET pin is an asynchronous signal which 6.3.4 Internal Low Voltage Detector (LVD)
plays a major role in EMS performance. In a noisy RESET
environment, it is recommended to follow the Two different RESET sequences caused by the in-
guidelines mentioned in the electrical characteris- ternal LVD circuitry can be distinguished:
tics section.
■ Power-On RESET
6.3.3 External Power-On RESET
■ Voltage Drop RESET
If the LVD is disabled by option byte, to start up the
The device RESET pin acts as an output that is
microcontroller correctly, the user must ensure by
pulled low when VDD<VIT+ (rising edge) or
means of an external reset circuit that the reset
signal is held low until VDD is over the minimum VDD<VIT- (falling edge) as shown in Figure 14.
level specified for the selected fOSC frequency. The LVD filters spikes on VDD larger than tg(VDD) to
A proper reset signal for a slow rising VDD supply avoid parasitic resets.
can generally be provided by an external RC net- 6.3.5 Internal Watchdog RESET
work connected to the RESET pin.
The RESET sequence generated by a internal
Watchdog counter overflow is shown in Figure 14.
Starting from the Watchdog counter underflow, the
device RESET pin acts as an output that is pulled
low during at least tw(RSTL)out.
Figure 14. RESET Sequences
VDD
VIT+(LVD)
VIT-(LVD)
LVD EXTERNAL WATCHDOG

RESET RESET RESET
RUN RUN ACTIVE
RUN ACTIVE
RUN
ACTIVE PHASE PHASE PHASE
th(RSTL)in tw(RSTL)out
EXTERNAL
RESET
SOURCE
RESET PIN
WATCHDOG
RESET
WATCHDOG UNDERFLOW
INTERNAL RESET (256 or 4096 TCPU)

VECTOR FETCH
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6.4 SYSTEM INTEGRITY MANAGEMENT (SI)

The System Integrity Management block contains – under full software control
the Low Voltage Detector (LVD) and Auxiliary Volt- – in static safe reset
age Detector (AVD) functions. It is managed by In these conditions, secure operation is always en-
the SICSR register. sured for the application without the need for ex-
6.4.1 Low Voltage Detector (LVD) ternal reset hardware.
The Low Voltage Detector function (LVD) gener- During a Low Voltage Detector Reset, the RESET
ates a static reset when the VDD supply voltage is pin is held low, thus permitting the MCU to reset
below a VIT- reference value. This means that it other devices.
secures the power-up as well as the power-down
keeping the ST7 in reset.
Notes:
The VIT- reference value for a voltage drop is lower
than the VIT+ reference value for power-on in order The LVD allows the device to be used without any
to avoid a parasitic reset when the MCU starts run- external RESET circuitry.
ning and sinks current on the supply (hysteresis). If the medium or low thresholds are selected, the
The LVD Reset circuitry generates a reset when detection may occur outside the specified operat-
VDD is below: ing voltage range. Below 3.8V, device operation is
not guaranteed.
– VIT+ when VDD is rising
– VIT- when VDD is falling The LVD is an optional function which can be se-
lected by option byte.
The LVD function is illustrated in Figure 15.
It is recommended to make sure that the VDD sup-
The voltage threshold can be configured by option ply voltage rises monotonously when the device is
byte to be low, medium or high. exiting from Reset, to ensure the application func-
tions properly.
Provided the minimum VDD value (guaranteed for
the oscillator frequency) is above VIT-, the MCU
can only be in two modes:
Figure 15. Low Voltage Detector vs Reset
VDD
Vhys
VIT+
VIT-
RESET
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SYSTEM INTEGRITY MANAGEMENT (Cont’d)

6.4.2 Auxiliary Voltage Detector (AVD) In the case of a drop in voltage, the AVD interrupt
The Voltage Detector function (AVD) is based on acts as an early warning, allowing software to shut
an analog comparison between a VIT-(AVD) and down safely before the LVD resets the microcon-
VIT+(AVD) reference value and the VDD main sup- troller. See Figure 16.
ply. The VIT- reference value for falling voltage is The interrupt on the rising edge is used to inform
lower than the VIT+ reference value for rising volt- the application that the VDD warning state is over.
age in order to avoid parasitic detection (hystere- If the voltage rise time trv is less than 256 or 4096
sis). CPU cycles (depending on the reset delay select-
The output of the AVD comparator is directly read- ed by option byte), no AVD interrupt will be gener-
able by the application software through a real ated when VIT+(AVD) is reached.
time status bit (AVDF) in the SICSR register. This If trv is greater than 256 or 4096 cycles then:
bit is read only.
– If the AVD interrupt is enabled before the
Caution: The AVD function is active only if the
LVD is enabled through the option byte (see Sec- VIT+(AVD) threshold is reached, then 2 AVD inter-
tion 14.1 on page 150). rupts will be received: the first when the AVDIE
bit is set, and the second when the threshold is
6.4.2.1 Monitoring the VDD Main Supply reached.
The AVD voltage threshold value is relative to the – If the AVD interrupt is enabled after the VIT+(AVD)
selected LVD threshold configured by option byte threshold is reached then only one AVD interrupt
(see will occur.
If the AVD interrupt is enabled, an interrupt is gen-
erated when the voltage crosses the VIT+(AVD) or
VIT-(AVD) threshold (AVDF bit toggles).
Figure 16. Using the AVD to Monitor VDD
VDD
Early Warning Interrupt
(Power has dropped, MCU not
not yet in reset)
Vhyst
VIT+(AVD)
VIT-(AVD)
VIT+(LVD)
VIT-(LVD) trv VOLTAGE RISE TIME
AVDF bit 0 1 RESET VALUE 1 0
AVD INTERRUPT
REQUEST
IF AVDIE bit = 1
INTERRUPT PROCESS INTERRUPT PROCESS
LVD RESET
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6.4.3 Low Power Modes
Mode Description
No effect on SI. AVD interrupt causes the
WAIT
device to exit from Wait mode.
HALT The CRSR register is frozen.
6.4.3.1 Interrupts
The AVD interrupt event generates an interrupt if
the AVDIE bit is set and the interrupt mask in the
CC register is reset (RIM instruction).
Enable Exit Exit
Event
Interrupt Event Control from from
Flag
Bit Wait Halt
AVD event AVDF AVDIE Yes No
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6.4.4 Register Description
SYSTEM INTEGRITY (SI) CONTROL/STATUS REGISTER (SICSR)
Read/Write Bits 3:1 = Reserved, must be kept cleared.
Reset Value: 000x 000x (00h)
Bit 0 = WDGRF Watchdog reset flag
7 0 This bit indicates that the last Reset was generat-
AVD AVD LVD WDG
ed by the Watchdog peripheral. It is set by hard-
0
F RF
0 0 0
RF
ware (watchdog reset) and cleared by software
IE
(writing zero) or an LVD Reset (to ensure a stable
cleared state of the WDGRF flag when CPU
Bit 7 = Reserved, must be kept cleared. starts).
Combined with the LVDRF flag information, the
flag description is given by the following table.
Bit 6 = AVDIE Voltage Detector interrupt enable
This bit is set and cleared by software. It enables RESET Sources LVDRF WDGRF
an interrupt to be generated when the AVDF flag External RESET pin 0 0
changes (toggles). The pending interrupt informa- Watchdog 0 1
tion is automatically cleared when software enters
LVD 1 X
the AVD interrupt routine.
0: AVD interrupt disabled
1: AVD interrupt enabled
Application notes
The LVDRF flag is not cleared when another RE-
Bit 5 = AVDF Voltage Detector flag SET type occurs (external or watchdog), the
This read-only bit is set and cleared by hardware. LVDRF flag remains set to keep trace of the origi-
If the AVDIE bit is set, an interrupt request is gen- nal failure.
erated when the AVDF bit changes value. Refer to In this case, a watchdog reset can be detected by
Figure 16 and to Section 6.4.2.1 for additional de- software while an external reset can not.
tails.
0: VDD over VIT+(AVD) threshold CAUTION: When the LVD is not activated with the
1: VDD under VIT-(AVD) threshold associated option byte, the WDGRF flag can not
be used in the application.
Bit 4 = LVDRF LVD reset flag

This bit indicates that the last Reset was generat-
ed by the LVD block. It is set by hardware (LVD re-
set) and cleared by software (writing zero). See
WDGRF flag description for more details. When
the LVD is disabled by OPTION BYTE, the LVDRF
bit value is undefined.
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7 INTERRUPTS
7.1 INTRODUCTION When an interrupt request has to be serviced:

The ST7 enhanced interrupt management pro- – Normal processing is suspended at the end of
vides the following features: the current instruction execution.
■ Hardware interrupts
– The PC, X, A and CC registers are saved onto
the stack.
■ Software interrupt (TRAP)
■ Nested or concurrent interrupt management

– I1 and I0 bits of CC register are set according to
the corresponding values in the ISPRx registers
with flexible interrupt priority and level of the serviced interrupt vector.
management:
– The PC is then loaded with the interrupt vector of
– Up to 4 software programmable nesting levels the interrupt to service and the first instruction of
– Up to 16 interrupt vectors fixed by hardware the interrupt service routine is fetched (refer to
– 2 non maskable events: RESET, TRAP “Interrupt Mapping” table for vector addresses).
This interrupt management is based on: The interrupt service routine should end with the
– Bit 5 and bit 3 of the CPU CC register (I1:0), IRET instruction which causes the contents of the
saved registers to be recovered from the stack.
– Interrupt software priority registers (ISPRx),
Note: As a consequence of the IRET instruction,
– Fixed interrupt vector addresses located at the the I1 and I0 bits will be restored from the stack
high addresses of the memory map (FFE0h to and the program in the previous level will resume.
FFFFh) sorted by hardware priority order.
This enhanced interrupt controller guarantees full
upward compatibility with the standard (not nest- Table 6. Interrupt Software Priority Levels
ed) ST7 interrupt controller. Interrupt software priority Level I1 I0
Level 0 (main) Low 1 0
7.2 MASKING AND PROCESSING FLOW Level 1 0 1
The interrupt masking is managed by the I1 and I0 Level 2 0 0
bits of the CC register and the ISPRx registers Level 3 (= interrupt disable) High 1 1
which give the interrupt software priority level of
each interrupt vector (see Table 6). The process-
ing flow is shown in Figure 17
Figure 17. Interrupt Processing Flowchart
PENDING Y Y
RESET TRAP
INTERRUPT
Interrupt has the same or a N

N lower software priority
than current one
I1:0
Interrupt has a higher
FETCH NEXT THE INTERRUPT

than current one
software priority
INSTRUCTION STAYS PENDING
Y
“IRET”
RESTORE PC, X, A, CC EXECUTE

FROM STACK INSTRUCTION STACK PC, X, A, CC
LOAD I1:0 FROM INTERRUPT SW REG.
LOAD PC FROM INTERRUPT VECTOR
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INTERRUPTS (Cont’d)
Servicing Pending Interrupts vector is loaded in the PC register and the I1 and
As several interrupts can be pending at the same I0 bits of the CC are set to disable interrupts (level
time, the interrupt to be taken into account is deter- 3). These sources allow the processor to exit
mined by the following two-step process: HALT mode.
■ TRAP (Non Maskable Software Interrupt)
– the highest software priority interrupt is serviced,
This software interrupt is serviced when the TRAP
– if several interrupts have the same software pri-
instruction is executed. It will be serviced accord-
ority then the interrupt with the highest hardware
ing to the flowchart in Figure 17.
priority is serviced first.
■ RESET
Figure 18 describes this decision process.
The RESET source has the highest priority in the
Figure 18. Priority Decision Process ST7. This means that the first current routine has
the highest software priority (level 3) and the high-
PENDING
est hardware priority.
INTERRUPTS
See the RESET chapter for more details.
Maskable Sources
Maskable interrupt vector sources can be serviced
Same Different
SOFTWARE if the corresponding interrupt is enabled and if its
PRIORITY own interrupt software priority (in ISPRx registers)
is higher than the one currently being serviced (I1
and I0 in CC register). If any of these two condi-
HIGHEST SOFTWARE tions is false, the interrupt is latched and thus re-
PRIORITY SERVICED mains pending.
■ External Interrupts
HIGHEST HARDWARE
External interrupts allow the processor to exit from
PRIORITY SERVICED
HALT low power mode. External interrupt sensitiv-
ity is software selectable through the External In-
When an interrupt request is not serviced immedi- terrupt Control register (EICR).
ately, it is latched and then processed when its External interrupt triggered on edge will be latched
software priority combined with the hardware pri- and the interrupt request automatically cleared
ority becomes the highest one. upon entering the interrupt service routine.
If several input pins of a group connected to the
Note 1: The hardware priority is exclusive while same interrupt line are selected simultaneously,
the software one is not. This allows the previous these will be logically ORed.
process to succeed with only one interrupt.
■ Peripheral Interrupts
Note 2: RESET and TRAP can be considered as
having the highest software priority in the decision Usually the peripheral interrupts cause the MCU to
process. exit from HALT mode except those mentioned in
the “Interrupt Mapping” table. A peripheral inter-
Different Interrupt Vector Sources rupt occurs when a specific flag is set in the pe-
Two interrupt source types are managed by the ripheral status registers and if the corresponding
ST7 interrupt controller: the non-maskable type enable bit is set in the peripheral control register.
(RESET,TRAP) and the maskable type (external The general sequence for clearing an interrupt is
or from internal peripherals). based on an access to the status register followed
by a read or write to an associated register.
Non-Maskable Sources Note: The clearing sequence resets the internal
These sources are processed regardless of the latch. A pending interrupt (i.e. waiting for being
state of the I1 and I0 bits of the CC register (see serviced) will therefore be lost if the clear se-
Figure 17). After stacking the PC, X, A and CC quence is executed.
registers (except for RESET), the corresponding
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7.3 INTERRUPTS AND LOW POWER MODES 7.4 CONCURRENT & NESTED MANAGEMENT
All interrupts allow the processor to exit the WAIT The following Figure 19 and Figure 20 show two
low power mode. On the contrary, only external different interrupt management modes. The first is
and other specified interrupts allow the processor called concurrent mode and does not allow an in-
to exit from the HALT modes (see column “Exit terrupt to be interrupted, unlike the nested mode in
from HALT” in “Interrupt Mapping” table). When Figure 20. The interrupt hardware priority is given
several pending interrupts are present while exit- in this order from the lowest to the highest: MAIN,
ing HALT mode, the first one serviced can only be IT4, IT3, IT2, IT1, IT0. The software priority is giv-
an interrupt with exit from HALT mode capability en for each interrupt.
and it is selected through the same decision proc- Warning: A stack overflow may occur without no-
ess shown in Figure 18. tifying the software of the failure.
Note: If an interrupt, that is not able to Exit from
HALT mode, is pending with the highest priority
when exiting HALT mode, this interrupt is serviced
after the first one serviced.
Figure 19. Concurrent Interrupt Management
TRAP
SOFTWARE
I1 I0
IT2
IT1
IT4
IT3
IT0
PRIORITY
LEVEL
HARDWARE PRIORITY
USED STACK = 10 BYTES

TRAP 3 1 1
IT0 3 1 1
IT1 IT1 3 1 1
IT2 3 1 1
IT3 3 1 1
RIM
IT4 3 1 1
MAIN MAIN 3/0
11 / 10 10
Figure 20. Nested Interrupt Management

TRAP
SOFTWARE
I1 I0
IT0
IT2
IT1
IT4
IT3
PRIORITY
LEVEL
USED STACK = 20 BYTES
HARDWARE PRIORITY
TRAP 3 1 1
IT0 3 1 1
IT1 IT1 2 0 0
IT2 IT2 1 0 1
IT3 3 1 1
RIM
IT4 IT4 3 1 1
MAIN MAIN 3/0
11 / 10 10
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7.5 INTERRUPT REGISTER DESCRIPTION
CPU CC REGISTER INTERRUPT BITS

INTERRUPT SOFTWARE PRIORITY REGIS-
Read/Write
TERS (ISPRX)
Reset Value: 111x 1010 (xAh)
Read/Write (bit 7:4 of ISPR3 are read only)
7 0 Reset Value: 1111 1111 (FFh)
7 0
1 1 I1 H I0 N Z C
ISPR0 I1_3 I0_3 I1_2 I0_2 I1_1 I0_1 I1_0 I0_0
Bit 5, 3 = I1, I0 Software Interrupt Priority
These two bits indicate the current interrupt soft- ISPR1 I1_7 I0_7 I1_6 I0_6 I1_5 I0_5 I1_4 I0_4
ware priority.
ISPR2 I1_11 I0_11 I1_10 I0_10 I1_9 I0_9 I1_8 I0_8
Interrupt Software Priority Level I1 I0
Level 0 (main) Low 1 0
ISPR3 1 1 1 1 I1_13 I0_13 I1_12 I0_12
Level 1 0 1
Level 2 0 0
Level 3 (= interrupt disable*) High 1 1 These four registers contain the interrupt software
priority of each interrupt vector.
These two bits are set/cleared by hardware when – Each interrupt vector (except RESET and TRAP)
entering in interrupt. The loaded value is given by has corresponding bits in these registers where
the corresponding bits in the interrupt software pri- its own software priority is stored. This corre-
ority registers (ISPRx). spondance is shown in the following table.
They can be also set/cleared by software with the
Vector address ISPRx bits
RIM, SIM, HALT, WFI, IRET and PUSH/POP in-
structions (see “Interrupt Dedicated Instruction FFFBh-FFFAh I1_0 and I0_0 bits*
Set” table). FFF9h-FFF8h I1_1 and I0_1 bits
*Note: TRAP and RESET events can interrupt a ... ...
level 3 program. FFE1h-FFE0h I1_13 and I0_13 bits
– Each I1_x and I0_x bit value in the ISPRx regis-

ters has the same meaning as the I1 and I0 bits
in the CC register.
– Level 0 can not be written (I1_x=1, I0_x=0). In
this case, the previously stored value is kept. (ex-
ample: previous=CFh, write=64h, result=44h)
The RESET, and TRAP vectors have no software
priorities. When one is serviced, the I1 and I0 bits
of the CC register are both set.
Caution: If the I1_x and I0_x bits are modified
while the interrupt x is executed the following be-
haviour has to be considered: If the interrupt x is
still pending (new interrupt or flag not cleared) and
the new software priority is higher than the previ-
ous one, the interrupt x is re-entered. Otherwise,
the software priority stays unchanged up to the
next interrupt request (after the IRET of the inter-
rupt x).
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Table 7. Dedicated Interrupt Instruction Set

Instruction New Description Function/Example I1 H I0 N Z C
HALT Entering Halt mode 1 0
IRET Interrupt routine return Pop CC, A, X, PC I1 H I0 N Z C
JRM Jump if I1:0=11 (level 3) I1:0=11?
JRNM Jump if I1:0<>11 I1:0<>11?
POP CC Pop CC from the Stack Mem => CC I1 H I0 N Z C
RIM Enable interrupt (level 0 set) Load 10 in I1:0 of CC 1 0
SIM Disable interrupt (level 3 set) Load 11 in I1:0 of CC 1 1
TRAP Software trap Software NMI 1 1
WFI Wait for interrupt 1 0
Note: During the execution of an interrupt routine, the HALT, POPCC, RIM, SIM and WFI instructions change the current
software priority up to the next IRET instruction or one of the previously mentioned instructions.
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Table 8. Interrupt Mapping
Exit
from
Source Register Priority Address
N° Description HALT/
Block Label Order Vector
ACTIVE
HALT1)
RESET Reset yes FFFEh-FFFFh
N/A
TRAP Software interrupt no FFFCh-FFFDh
0 Not used FFFAh-FFFBh
1 MCC/RTC Main clock controller time base interrupt MCCSR Higher yes FFF8h-FFF9h
2 ei0 External interrupt port A3..0 Priority yes FFF6h-FFF7h
3 ei1 External interrupt port F2..0 yes FFF4h-FFF5h
N/A
4 ei2 External interrupt port B3..0 yes FFF2h-FFF3h
5 ei3 External interrupt port B7..4 yes FFF0h-FFF1h
6 Not used FFEEh-FFEFh
7 SPI SPI peripheral interrupts SPICSR yes FFECh-FFEDh
8 TIMER A TIMER A peripheral interrupts TASR no FFEAh-FFEBh
9 TIMER B TIMER B peripheral interrupts TBSR no FFE8h-FFE9h
10 SCI SCI Peripheral interrupts SCISR Lower no FFE6h-FFE7h
11 AVD Auxiliary Voltage detector interrupt SICSR Priority no FFE4h-FFE5h
Notes:
1. In Flash devices only a RESET or MCC/RTC interrupt can be used to wake-up from Active Halt mode.
7.6 EXTERNAL INTERRUPTS

7.6.1 I/O Port Interrupt Sensitivity ■ Falling edge and low level
The external interrupt sensitivity is controlled by ■ Rising edge and high level (only for ei0 and ei2)
the IPA, IPB and ISxx bits of the EICR register To guarantee correct functionality, the sensitivity
(Figure 21). This control allows to have up to 4 fully bits in the EICR register can be modified only
independent external interrupt source sensitivities. when the I1 and I0 bits of the CC register are both
Each external interrupt source can be generated set to 1 (level 3). This means that interrupts must
on four (or five) different events on the pin: be disabled before changing sensitivity.
■ Falling edge The pending interrupts are cleared by writing a dif-
■ Rising edge ferent value in the ISx[1:0], IPA or IPB bits of the
EICR.
■ Falling and rising edge
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Figure 21. External Interrupt Control bits
PORT A3 INTERRUPT EICR
IS20 IS21
PAOR.3
PADDR.3
SENSITIVITY ei0 INTERRUPT SOURCE
PA3
CONTROL
IPA BIT
PORT F [2:0] INTERRUPTS EICR
IS20 IS21
PFOR.2
PFDDR.2
SENSITIVITY PF2
PF2 PF1 ei1 INTERRUPT SOURCE
CONTROL
PF0
PORT B [3:0] INTERRUPTS EICR
IS10 IS11
PBOR.3
PBDDR.3
SENSITIVITY PB3
PB3 ei2 INTERRUPT SOURCE
CONTROL PB2
PB1
PB0
IPB BIT
PORT B4 INTERRUPT EICR
IS10 IS11
PBOR.4
PBDDR.4
SENSITIVITY ei3 INTERRUPT SOURCE
PB4 CONTROL
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7.7 EXTERNAL INTERRUPT CONTROL REGISTER (EICR)

Read/Write Bit 4:3 = IS2[1:0] ei0 and ei1 sensitivity
Reset Value: 0000 0000 (00h) The interrupt sensitivity, defined using the IS2[1:0]
bits, is applied to the following external interrupts:
7 0
IS11 IS10 IPB IS21 IS20 IPA 0 0
- ei0 (port A3..0)

Bit 7:6 = IS1[1:0] ei2 and ei3 sensitivity
The interrupt sensitivity, defined using the IS1[1:0] External Interrupt Sensitivity
bits, is applied to the following external interrupts: IS21 IS20
- ei2 (port B3..0) IPA bit =0 IPA bit =1
Falling edge & Rising edge
External Interrupt Sensitivity 0 0
low level & high level
IS11 IS10
IPB bit =0 IPB bit =1 0 1 Rising edge only Falling edge only
Falling edge & Rising edge 1 0 Falling edge only Rising edge only
0 0
low level & high level 1 1 Rising and falling edge
0 1 Rising edge only Falling edge only
1 0 Falling edge only Rising edge only
1 1 Rising and falling edge
- ei1 (port F2..0)
IS21 IS20 External Interrupt Sensitivity
- ei3 (port B4)
0 0 Falling edge & low level
IS11 IS10 External Interrupt Sensitivity 0 1 Rising edge only
0 0 Falling edge & low level 1 0 Falling edge only
0 1 Rising edge only 1 1 Rising and falling edge
1 0 Falling edge only
1 1 Rising and falling edge
These 2 bits can be written only when I1 and I0 of
the CC register are both set to 1 (level 3).
These 2 bits can be written only when I1 and I0 of
the CC register are both set to 1 (level 3). Bit 2 = IPA Interrupt polarity for port A
This bit is used to invert the sensitivity of the port A
Bit 5 = IPB Interrupt polarity for port B [3:0] external interrupts. It can be set and cleared
This bit is used to invert the sensitivity of the port B by software only when I1 and I0 of the CC register
[3:0] external interrupts. It can be set and cleared are both set to 1 (level 3).
by software only when I1 and I0 of the CC register 0: No sensitivity inversion
are both set to 1 (level 3). 1: Sensitivity inversion
0: No sensitivity inversion
1: Sensitivity inversion
Bits 1:0 = Reserved, must always be kept cleared.
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Table 9. Nested Interrupts Register Map and Reset Values
Address Register
7 6 5 4 3 2 1 0
(Hex.) Label
ei1 ei0 MCC + SI
0024h ISPR0 I1_3 I0_3 I1_2 I0_2 I1_1 I0_1
Reset Value 1 1 1 1 1 1 1 1
SPI ei3 ei2
0025h ISPR1 I1_7 I0_7 I1_6 I0_6 I1_5 I0_5 I1_4 I0_4
Reset Value 1 1 1 1 1 1 1 1
AVD SCI TIMER B TIMER A
0026h ISPR2 I1_11 I0_11 I1_10 I0_10 I1_9 I0_9 I1_8 I0_8
Reset Value 1 1 1 1 1 1 1 1
0027h ISPR3 I1_13 I0_13 I1_12 I0_12

Reset Value 1 1 1 1 1 1 1 1
EICR IS11 IS10 IPB IS21 IS20 IPA
0028h
Reset Value 0 0 0 0 0 0 0 0
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8 POWER SAVING MODES
8.1 INTRODUCTION 8.2 SLOW MODE

To give a large measure of flexibility to the applica- This mode has two targets:
tion in terms of power consumption, four main – To reduce power consumption by decreasing the
power saving modes are implemented in the ST7 internal clock in the device,
(see Figure 22): SLOW, WAIT (SLOW WAIT), AC-
TIVE HALT and HALT. – To adapt the internal clock frequency (fCPU) to
the available supply voltage.
After a RESET the normal operating mode is se-
lected by default (RUN mode). This mode drives SLOW mode is controlled by three bits in the
the device (CPU and embedded peripherals) by MCCSR register: the SMS bit which enables or
means of a master clock which is based on the disables Slow mode and two CPx bits which select
main oscillator frequency divided or multiplied by 2 the internal slow frequency (fCPU).
(fOSC2). In this mode, the master clock frequency (fOSC2)
From RUN mode, the different power saving can be divided by 2, 4, 8 or 16. The CPU and pe-
modes may be selected by setting the relevant ripherals are clocked at this lower frequency
register bits or by calling the specific ST7 software (fCPU).
instruction whose action depends on the oscillator Note: SLOW-WAIT mode is activated when enter-
status. ing the WAIT mode while the device is already in
SLOW mode.
Figure 22. Power Saving Mode Transitions
Figure 23. SLOW Mode Clock Transitions
High
fOSC2/2 fOSC2/4 fOSC2
RUN fCPU
SLOW fOSC2
MCCSR
CP1:0 00 01
WAIT
SMS
SLOW WAIT
NORMAL RUN MODE
NEW SLOW REQUEST
FREQUENCY
ACTIVE HALT REQUEST
HALT
Low
POWER CONSUMPTION
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POWER SAVING MODES (Cont’d)
8.3 WAIT MODE Figure 24. WAIT Mode Flow-chart

WAIT mode places the MCU in a low power con- OSCILLATOR ON
sumption mode by stopping the CPU. PERIPHERALS ON
This power saving mode is selected by calling the WFI INSTRUCTION
CPU OFF
‘WFI’ instruction. I[1:0] BITS 10
All peripherals remain active. During WAIT mode,
the I[1:0] bits of the CC register are forced to ‘10’,
to enable all interrupts. All other registers and
memory remain unchanged. The MCU remains in N
RESET
WAIT mode until an interrupt or RESET occurs,
whereupon the Program Counter branches to the Y
starting address of the interrupt or Reset service N
INTERRUPT
routine.
The MCU will remain in WAIT mode until a Reset Y
or an Interrupt occurs, causing it to wake up. OSCILLATOR ON
Refer to Figure 24. PERIPHERALS OFF
CPU ON
I[1:0] BITS 10
256 OR 4096 CPU CLOCK

CYCLE DELAY
OSCILLATOR ON
PERIPHERALS ON
CPU ON
I[1:0] BITS XX 1)
FETCH RESET VECTOR

OR SERVICE INTERRUPT
Note:
1. Before servicing an interrupt, the CC register is
pushed on the stack. The I[1:0] bits of the CC reg-
ister are set to the current software priority level of
the interrupt routine and recovered when the CC
register is popped.
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8.4 ACTIVE-HALT AND HALT MODES pending on option byte). Otherwise, the ST7 en-
ters HALT mode for the remaining tDELAY period.
ACTIVE-HALT and HALT modes are the two low-
est power consumption modes of the MCU. They Figure 25. ACTIVE-HALT Timing Overview
are both entered by executing the ‘HALT’ instruc-
tion. The decision to enter either in ACTIVE-HALT ACTIVE 256 OR 4096 CPU
or HALT mode is given by the MCC/RTC interrupt RUN HALT CYCLE DELAY 1) RUN
enable flag (OIE bit in MCCSR register).
RESET
MCCSR Power Saving Mode entered when HALT OR
OIE bit instruction is executed HALT INTERRUPT
INSTRUCTION FETCH
0 HALT mode [MCCSR.OIE=1] VECTOR
1 ACTIVE-HALT mode
Figure 26. ACTIVE-HALT Mode Flow-chart
8.4.1 ACTIVE-HALT MODE OSCILLATOR ON
ACTIVE-HALT mode is the lowest power con- HALT INSTRUCTION PERIPHERALS 2) OFF
sumption mode of the MCU with a real time clock (MCCSR.OIE=1) CPU OFF
I[1:0] BITS 10
available. It is entered by executing the ‘HALT’ in-
struction when the OIE bit of the Main Clock Con-
troller Status register (MCCSR) is set (see Section N
RESET
10.2 on page 56 for more details on the MCCSR
register). N Y
INTERRUPT 3)
The MCU can exit ACTIVE-HALT mode on recep- OSCILLATOR ON
tion of either an MCC/RTC interrupt, a specific in- PERIPHERALS OFF
terrupt (see Table 8, “Interrupt Mapping,” on Y
CPU ON
page 36) or a RESET. When exiting ACTIVE- I[1:0] BITS XX 4)
HALT mode by means of an interrupt, no 256 or
4096 CPU cycle delay occurs. The CPU resumes
256 OR 4096 CPU CLOCK
operation by servicing the interrupt or by fetching
CYCLE DELAY
the reset vector which woke it up (see Figure 26).
When entering ACTIVE-HALT mode, the I[1:0] bits
OSCILLATOR ON
in the CC register are forced to ‘10b’ to enable in-
PERIPHERALS ON
terrupts. Therefore, if an interrupt is pending, the
CPU ON
MCU wakes up immediately.
I[1:0] BITS XX 4)
In ACTIVE-HALT mode, only the main oscillator
and its associated counter (MCC/RTC) are run- FETCH RESET VECTOR
ning to keep a wake-up time base. All other periph- OR SERVICE INTERRUPT
erals are not clocked except those which get their
clock supply from another clock generator (such Notes:
as external or auxiliary oscillator). 1. This delay occurs only if the MCU exits ACTIVE-
The safeguard against staying locked in ACTIVE- HALT mode by means of a RESET.
HALT mode is provided by the oscillator interrupt. 2. Peripheral clocked with an external clock source
can still be active.
Note: As soon as the interrupt capability of one of 3. Only the MCC/RTC interrupt and some specific
the oscillators is selected (MCCSR.OIE bit set), interrupts can exit the MCU from ACTIVE-HALT
entering ACTIVE-HALT mode while the Watchdog mode (such as external interrupt). Refer to
is active does not generate a RESET. Table 8, “Interrupt Mapping,” on page 36 for more
This means that the device cannot spend more details.
than a defined delay in this power saving mode. 4. Before servicing an interrupt, the CC register is
CAUTION: When exiting ACTIVE-HALT mode fol- pushed on the stack. The I[1:0] bits of the CC reg-
lowing an interrupt, OIE bit of MCCSR register ister are set to the current software priority level of
must not be cleared before tDELAY after the inter- the interrupt routine and restored when the CC
register is popped.
rupt occurs (tDELAY = 256 or 4096 tCPU delay de-
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8.4.2 HALT MODE Figure 28. HALT Mode Flow-chart
The HALT mode is the lowest power consumption
mode of the MCU. It is entered by executing the HALT INSTRUCTION
‘HALT’ instruction when the OIE bit of the Main (MCCSR.OIE=0)
Clock Controller Status register (MCCSR) is ENABLE
cleared (see Section 10.2 on page 56 for more de- WATCHDOG
tails on the MCCSR register).
0 DISABLE
The MCU can exit HALT mode on reception of ei- WDGHALT 1)
ther a specific interrupt (see Table 8, “Interrupt
1
Mapping,” on page 36) or a RESET. When exiting
HALT mode by means of a RESET or an interrupt, WATCHDOG
the oscillator is immediately turned on and the 256 OSCILLATOR OFF
RESET PERIPHERALS 2) OFF
or 4096 CPU cycle delay is used to stabilize the
CPU OFF
oscillator. After the start up delay, the CPU
I[1:0] BITS 10
resumes operation by servicing the interrupt or by
fetching the reset vector which woke it up (see Fig-
ure 28).
When entering HALT mode, the I[1:0] bits in the N
RESET
CC register are forced to ‘10b’to enable interrupts.
Therefore, if an interrupt is pending, the MCU Y
wakes up immediately. N
INTERRUPT 3)
In HALT mode, the main oscillator is turned off
causing all internal processing to be stopped, in- Y OSCILLATOR ON
cluding the operation of the on-chip peripherals. PERIPHERALS OFF
All peripherals are not clocked except the ones CPU ON
which get their clock supply from another clock I[1:0] BITS XX 4)
generator (such as an external or auxiliary oscilla-
tor). 256 OR 4096 CPU CLOCK
The compatibility of Watchdog operation with CYCLE DELAY
HALT mode is configured by the “WDGHALT” op-
tion bit of the option byte. The HALT instruction
OSCILLATOR ON
when executed while the Watchdog system is en- PERIPHERALS ON
abled, can generate a Watchdog RESET (see CPU ON
Section 14.1 on page 150) for more details. I[1:0] BITS XX 4)
Figure 27. HALT Timing Overview
FETCH RESET VECTOR
256 OR 4096 CPU OR SERVICE INTERRUPT
RUN HALT CYCLE DELAY RUN
Notes:
RESET 1. WDGHALT is an option bit. See option byte sec-
OR tion for more details.
HALT INTERRUPT 2. Peripheral clocked with an external clock source
INSTRUCTION FETCH can still be active.
[MCCSR.OIE=0] VECTOR 3. Only some specific interrupts can exit the MCU
from HALT mode (such as external interrupt). Re-
fer to Table 8, “Interrupt Mapping,” on page 36 for
more details.
4. Before servicing an interrupt, the CC register is
pushed on the stack. The I[1:0] bits of the CC reg-
ister are set to the current software priority level of
the interrupt routine and recovered when the CC
register is popped.
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8.4.2.1 Halt Mode Recommendations – The opcode for the HALT instruction is 0x8E. To
– Make sure that an external event is available to avoid an unexpected HALT instruction due to a
wake up the microcontroller from Halt mode. program counter failure, it is advised to clear all
occurrences of the data value 0x8E from memo-
– When using an external interrupt to wake up the ry. For example, avoid defining a constant in
microcontroller, reinitialize the corresponding I/O ROM with the value 0x8E.
as “Input Pull-up with Interrupt” before executing
the HALT instruction. The main reason for this is – As the HALT instruction clears the interrupt mask
that the I/O may be wrongly configured due to ex- in the CC register to allow interrupts, the user
ternal interference or by an unforeseen logical may choose to clear all pending interrupt bits be-
condition. fore executing the HALT instruction. This avoids
entering other peripheral interrupt routines after
– For the same reason, reinitialize the level sensi- executing the external interrupt routine corre-
tiveness of each external interrupt as a precau- sponding to the wake-up event (reset or external
tionary measure. interrupt).
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9 I/O PORTS
9.1 INTRODUCTION Each pin can independently generate an interrupt

request. The interrupt sensitivity is independently
The I/O ports offer different functional modes: programmable using the sensitivity bits in the
– transfer of data through digital inputs and outputs EICR register.
and for specific pins: Each external interrupt vector is linked to a dedi-
– external interrupt generation cated group of I/O port pins (see pinout description
– alternate signal input/output for the on-chip pe- and interrupt section). If several input pins are se-
ripherals. lected simultaneously as interrupt sources, these
An I/O port contains up to 8 pins. Each pin can be are first detected according to the sensitivity bits in
programmed independently as digital input (with or the EICR register and then logically ORed.
without interrupt generation) or digital output. The external interrupts are hardware interrupts,
which means that the request latch (not accessible
9.2 FUNCTIONAL DESCRIPTION directly by the application) is automatically cleared
when the corresponding interrupt vector is
Each port has 2 main registers: fetched. To clear an unwanted pending interrupt
– Data Register (DR) by software, the sensitivity bits in the EICR register
– Data Direction Register (DDR) must be modified.
and one optional register: 9.2.2 Output Modes
– Option Register (OR) The output configuration is selected by setting the
corresponding DDR register bit. In this case, writ-
Each I/O pin may be programmed using the corre- ing the DR register applies this digital value to the
sponding register bits in the DDR and OR regis- I/O pin through the latch. Then reading the DR reg-
ters: bit X corresponding to pin X of the port. The ister returns the previously stored value.
same correspondence is used for the DR register.
Two different output modes can be selected by
The following description takes into account the software through the OR register: Output push-pull
OR register, (for specific ports which do not pro- and open-drain.
vide this register refer to the I/O Port Implementa-
tion section). The generic I/O block diagram is DR register value and output pin status:
shown in Figure 29 DR Push-pull Open-drain
9.2.1 Input Modes 0 VSS Vss
The input configuration is selected by clearing the 1 VDD Floating
corresponding DDR register bit.
9.2.3 Alternate Functions
In this case, reading the DR register returns the
digital value applied to the external I/O pin. When an on-chip peripheral is configured to use a
pin, the alternate function is automatically select-
Different input modes can be selected by software ed. This alternate function takes priority over the
through the OR register. standard I/O programming.
Notes: When the signal is coming from an on-chip periph-
1. Writing the DR register modifies the latch value
but does not affect the pin status. eral, the I/O pin is automatically configured in out-
2. When switching from input to output mode, the put mode (push-pull or open drain according to the
DR register has to be written first to drive the cor- peripheral).
rect level on the pin as soon as the port is config- When the signal is going to an on-chip peripheral,
ured as an output. the I/O pin must be configured in input mode. In
3. Do not use read/modify/write instructions (BSET this case, the pin state is also digitally readable by
or BRES) to modify the DR register addressing the DR register.
External interrupt function Note: Input pull-up configuration can cause unex-
When an I/O is configured as Input with Interrupt, pected value at the input of the alternate peripheral
an event on this I/O can generate an external inter- input. When an on-chip peripheral use a pin as in-
rupt request to the CPU. put and output, this pin has to be configured in in-
put floating mode.
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I/O PORTS (Cont’d)

Figure 29. I/O Port General Block Diagram
ALTERNATE
REGISTER 1
OUTPUT VDD P-BUFFER
ACCESS
(see table below)
0
ALTERNATE PULL-UP
ENABLE (see table below)
DR VDD
DDR
PULL-UP
PAD
CONDITION
OR
DATA BUS
If implemented
OR SEL
N-BUFFER
DIODES
(see table below)
DDR SEL
ANALOG
INPUT
CMOS
SCHMITT
DR SEL
1 TRIGGER
0
ALTERNATE
INPUT
EXTERNAL
INTERRUPT
SOURCE (eix)
Table 10. I/O Port Mode Options

Diodes
Configuration Mode Pull-Up P-Buffer
to VDD to VSS
Floating with/without Interrupt Off
Input Off
Pull-up with/without Interrupt On
On
Push-pull On On
Off
Output Open Drain (logic level) Off
True Open Drain NI NI NI (see note)
Legend: NI - not implemented Note: The diode to VDD is not implemented in the
Off - implemented not activated true open drain pads. A local protection between
On - implemented and activated the pad and VSS is implemented to protect the de-
vice against positive stress.
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Table 11. I/O Port Configurations
Hardware Configuration
NOT IMPLEMENTED IN DR REGISTER ACCESS

VDD
TRUE OPEN DRAIN
I/O PORTS
RPU PULL-UP
CONDITION DR W
REGISTER DATA BUS
PAD R
INPUT 1)
ALTERNATE INPUT
EXTERNAL INTERRUPT
SOURCE (eix)
INTERRUPT
CONDITION
ANALOG INPUT

TRUE OPEN DRAIN VDD
OPEN-DRAIN OUTPUT 2)
I/O PORTS
RPU
DR R/W
REGISTER DATA BUS
PAD
ALTERNATE ALTERNATE
ENABLE OUTPUT

TRUE OPEN DRAIN VDD
PUSH-PULL OUTPUT 2)
I/O PORTS
RPU
DR R/W
REGISTER DATA BUS
PAD
ALTERNATE ALTERNATE
ENABLE OUTPUT
Notes:
1. When the I/O port is in input configuration and the associated alternate function is enabled as an output,
reading the DR register will read the alternate function output status.
2. When the I/O port is in output configuration and the associated alternate function is enabled as an input,
the alternate function reads the pin status given by the DR register content.
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CAUTION: The alternate function must not be ac- Figure 30. Interrupt I/O Port State Transitions
tivated as long as the pin is configured as input
with interrupt, in order to avoid generating spurious
interrupts. 01 00 10 11
Analog alternate function INPUT INPUT OUTPUT OUTPUT
When the pin is used as an ADC input, the I/O floating/pull-up floating open-drain push-pull
must be configured as floating input. The analog interrupt (reset state)
multiplexer (controlled by the ADC registers)
switches the analog voltage present on the select- XX = DDR, OR
ed pin to the common analog rail which is connect-

ed to the ADC input.
9.4 LOW POWER MODES
It is recommended not to change the voltage level
or loading on any port pin while conversion is in Mode Description
progress. Furthermore it is recommended not to No effect on I/O ports. External interrupts
have clocking pins located close to a selected an- WAIT
cause the device to exit from WAIT mode.
alog pin.
No effect on I/O ports. External interrupts
WARNING: The analog input voltage level must HALT
cause the device to exit from HALT mode.
be within the limits stated in the absolute maxi-
mum ratings.
9.5 INTERRUPTS
9.3 I/O PORT IMPLEMENTATION The external interrupt event generates an interrupt
if the corresponding configuration is selected with
The hardware implementation on each I/O port de- DDR and OR registers and the interrupt mask in
pends on the settings in the DDR and OR registers the CC register is not active (RIM instruction).
and specific feature of the I/O port such as ADC In-
put or true open drain. Enable Exit Exit
Event
Switching these I/O ports from one state to anoth- Interrupt Event Control from from
Flag
er should be done in a sequence that prevents un- Bit Wait Halt
wanted side effects. Recommended safe transi- External interrupt on
tions are illustrated in Figure 30 Other transitions DDRx
selected external - Yes Yes
are potentially risky and should be avoided, since ORx
event
they are likely to present unwanted side-effects
such as spurious interrupt generation.
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9.5.1 I/O Port Implementation
The I/O port register configurations are summa- PA3, PB3, PF2 (without pull-up)
rised as follows.
MODE DDR OR
Standard Ports floating input 0 0
PA5:4, PC7:0, PD5:0, floating interrupt input 0 1
PE1:0, PF7:6, 4 open drain output 1 0
push-pull output 1 1
MODE DDR OR
floating input 0 0
pull-up input 0 1 True Open Drain Ports
open drain output 1 0 PA7:6
MODE DDR
Interrupt Ports floating input 0
PB4, PB2:0, PF1:0 (with pull-up) open drain (high sink ports) 1
MODE DDR OR
floating input 0 0
pull-up interrupt input 0 1
open drain output 1 0
Table 12. Port Configuration

Input Output
Port Pin name
OR = 0 OR = 1 OR = 0 OR = 1
PA7:6 floating true open-drain
Port A PA5:4 floating pull-up open drain push-pull
PA3 floating floating interrupt open drain push-pull
PB3 floating floating interrupt open drain push-pull
Port B
PB4, PB2:0 floating pull-up interrupt open drain push-pull
Port C PC7:0 floating pull-up open drain push-pull
Port D PD5:0 floating pull-up open drain push-pull
Port E PE1:0 floating pull-up open drain push-pull
PF7:6, 4 floating pull-up open drain push-pull
Port F PF2 floating floating interrupt open drain push-pull
PF1:0 floating pull-up interrupt open drain push-pull
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Table 13. I/O Port Register Map and Reset Values
Address Register
7 6 5 4 3 2 1 0
(Hex.) Label
Reset Value
0 0 0 0 0 0 0 0
of all I/O port registers
0000h PADR
0001h PADDR MSB LSB
0002h PAOR
0003h PBDR
0004h PBDDR MSB LSB
0005h PBOR
0006h PCDR
0007h PCDDR MSB LSB
0008h PCOR
0009h PDDR
000Ah PDDDR MSB LSB
000Bh PDOR
000Ch PEDR
000Dh PEDDR MSB LSB
000Eh PEOR
000Fh PFDR
0010h PFDDR MSB LSB
0011h PFOR
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10 ON-CHIP PERIPHERALS
10.1 WATCHDOG TIMER (WDG)

10.1.1 Introduction If the watchdog is activated (the WDGA bit is set)
The Watchdog timer is used to detect the occur- and when the 7-bit timer (bits T[6:0]) rolls over
rence of a software fault, usually generated by ex- from 40h to 3Fh (T6 becomes cleared), it initiates
ternal interference or by unforeseen logical condi- a reset cycle pulling low the reset pin for typically
tions, which causes the application program to 500ns.
abandon its normal sequence. The Watchdog cir- The application program must write in the
cuit generates an MCU reset on expiry of a pro- WDGCR register at regular intervals during normal
grammed time period, unless the program refresh- operation to prevent an MCU reset. This down-
es the counter’s contents before the T6 bit be- counter is free-running: it counts down even if the
comes cleared. watchdog is disabled. The value to be stored in the
10.1.2 Main Features WDGCR register must be between FFh and C0h:
■ Programmable free-running downcounter – The WDGA bit is set (watchdog enabled)
■ Programmable reset – The T6 bit is set to prevent generating an imme-
■ Reset (if watchdog activated) when the T6 bit
diate reset
reaches zero – The T[5:0] bits contain the number of increments
■ Optional reset on HALT instruction which represents the time delay before the
(configurable by option byte) watchdog produces a reset (see Figure 32. Ap-
proximate Timeout Duration). The timing varies
■ Hardware Watchdog selectable by option byte
between a minimum and a maximum value due
to the unknown status of the prescaler when writ-
10.1.3 Functional Description ing to the WDGCR register (see Figure 33).
The counter value stored in the Watchdog Control Following a reset, the watchdog is disabled. Once
register (WDGCR bits T[6:0]), is decremented activated it cannot be disabled, except by a reset.
every 16384 fOSC2 cycles (approx.), and the The T6 bit can be used to generate a software re-
length of the timeout period can be programmed set (the WDGA bit is set and the T6 bit is cleared).
by the user in 64 increments. If the watchdog is activated, the HALT instruction
will generate a Reset.
Figure 31. Watchdog Block Diagram
RESET
fOSC2
MCC/RTC
WATCHDOG CONTROL REGISTER (WDGCR)
DIV 64 WDGA T6 T5 T4 T3 T2 T1 T0
6-BIT DOWNCOUNTER (CNT)
12-BIT MCC
RTC COUNTER WDG PRESCALER
TB[1:0] bits DIV 4
MSB LSB
(MCCSR
11 6 5 0
Register)
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WATCHDOG TIMER (Cont’d)

10.1.4 How to Program the Watchdog Timeout more precision is needed, use the formulae in Fig-
Figure 32 shows the linear relationship between ure 33.
the 6-bit value to be loaded in the Watchdog Coun- Caution: When writing to the WDGCR register, al-
ter (CNT) and the resulting timeout duration in mil- ways write 1 in the T6 bit to avoid generating an
liseconds. This can be used for a quick calculation immediate reset.
without taking the timing variations into account. If
Figure 32. Approximate Timeout Duration
3F
38
30
28
CNT Value (hex.)
20
18
10
08
00
1.5 18 34 50 65 82 98 114 128
Watchdog timeout (ms) @ 8 MHz. fOSC2
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Figure 33. Exact Timeout Duration (tmin and tmax)
WHERE:
tmin0 = (LSB + 128) x 64 x tOSC2
tmax0 = 16384 x tOSC2
tOSC2 = 125ns if fOSC2=8 MHz
CNT = Value of T[5:0] bits in the WDGCR register (6 bits)
MSB and LSB are values from the table below depending on the timebase selected by the TB[1:0] bits
in the MCCSR register
TB1 Bit TB0 Bit Selected MCCSR
MSB LSB
(MCCSR Reg.) (MCCSR Reg.) Timebase
0 0 2ms 4 59
0 1 4ms 8 53
1 0 10ms 20 35
1 1 25ms 49 54
To calculate the minimum Watchdog Timeout (tmin):
IF CNT < MSB

------------- THEN t min = t min0 + 16384 × CNT × t osc2
4
ELSE t min = t min0 + 16384 × ⎛⎝ CNT – 4CNT

----------------- ⎞ + ( 192 + LSB ) × 64 × -----------------
4CNT
× t osc2
MSB ⎠ MSB
To calculate the maximum Watchdog Timeout (tmax):
IF CNT ≤ MSB
------------- THEN t max = t max0 + 16384 × CNT × t osc2
4
ELSE t max = t max0 + 16384 × ⎛⎝ CNT – 4CNT

----------------- ⎞ + ( 192 + LSB ) × 64 × -----------------
4CNT
× t osc2
MSB ⎠ MSB
Note: In the above formulae, division results must be rounded down to the next integer value.
Example:
With 2ms timeout selected in MCCSR register
Min. Watchdog Max. Watchdog
Value of T[5:0] Bits in
Timeout (ms) Timeout (ms)
WDGCR Register (Hex.)
tmin tmax
00 1.496 2.048
3F 128 128.552
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Mode Description
SLOW No effect on Watchdog.
WAIT No effect on Watchdog.
OIE bit in WDGHALT bit
MCCSR in Option
register Byte
No Watchdog reset is generated. The MCU enters Halt mode. The Watch-
dog counter is decremented once and then stops counting and is no longer
able to generate a watchdog reset until the MCU receives an external inter-
rupt or a reset.
0 0
If an external interrupt is received, the Watchdog restarts counting after 256
HALT or 4096 CPU clocks. If a reset is generated, the Watchdog is disabled (reset
state) unless Hardware Watchdog is selected by option byte. For applica-
tion recommendations see Section 10.1.7 below.
0 1 A reset is generated.
No reset is generated. The MCU enters Active Halt mode. The Watchdog
counter is not decremented. It stop counting. When the MCU receives an
1 x oscillator interrupt or external interrupt, the Watchdog restarts counting im-
mediately. When the MCU receives a reset the Watchdog restarts counting
after 256 or 4096 CPU clocks.
10.1.6 Hardware Watchdog Option 10.1.9 Register Description

If Hardware Watchdog is selected by option byte, CONTROL REGISTER (WDGCR)
the watchdog is always active and the WDGA bit in Read/Write
the WDGCR is not used. Refer to the Option Byte
description. Reset Value: 0111 1111 (7Fh)
10.1.7 Using Halt Mode with the WDG 7 0
(WDGHALT option)
WDGA T6 T5 T4 T3 T2 T1 T0
The following recommendation applies if Halt
mode is used when the watchdog is enabled.
– Before executing the HALT instruction, refresh Bit 7 = WDGA Activation bit.
the WDG counter, to avoid an unexpected WDG This bit is set by software and only cleared by
reset immediately after waking up the microcon- hardware after a reset. When WDGA = 1, the
troller. watchdog can generate a reset.
10.1.8 Interrupts 0: Watchdog disabled
1: Watchdog enabled
None.
Note: This bit is not used if the hardware watch-
dog option is enabled by option byte.
Bit 6:0 = T[6:0] 7-bit counter (MSB to LSB).
These bits contain the value of the watchdog
counter. It is decremented every 16384 fOSC2 cy-
cles (approx.). A reset is produced when it rolls
over from 40h to 3Fh (T6 becomes cleared).
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Table 14. Watchdog Timer Register Map and Reset Values

Address Register
7 6 5 4 3 2 1 0
(Hex.) Label
WDGCR WDGA T6 T5 T4 T3 T2 T1 T0
002Ah
Reset Value 0 1 1 1 1 1 1 1
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10.2 MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK AND BEEPER (MCC/RTC)
The Main Clock Controller consists of three differ- external devices. It is controlled by the MCO bit in
ent functions: the MCCSR register.
■ a programmable CPU clock prescaler CAUTION: When selected, the clock out pin sus-
■ a clock-out signal to supply external devices
pends the clock during ACTIVE-HALT mode.
■ a real time clock timer with interrupt capability
10.2.3 Real Time Clock Timer (RTC)
Each function can be used independently and si- The counter of the real time clock timer allows an
multaneously. interrupt to be generated based on an accurate
real time clock. Four different time bases depend-
10.2.1 Programmable CPU Clock Prescaler ing directly on fOSC2 are available. The whole
The programmable CPU clock prescaler supplies functionality is controlled by four bits of the MCC-
the clock for the ST7 CPU and its internal periph- SR register: TB[1:0], OIE and OIF.
erals. It manages SLOW power saving mode (See When the RTC interrupt is enabled (OIE bit set),
Section 8.2 SLOW MODE for more details). the ST7 enters ACTIVE-HALT mode when the
The prescaler selects the fCPU main clock frequen- HALT instruction is executed. See Section 8.4 AC-
cy and is controlled by three bits in the MCCSR TIVE-HALT AND HALT MODES for more details.
register: CP[1:0] and SMS. 10.2.4 Beeper
10.2.2 Clock-out Capability The beep function is controlled by the MCCBCR
The clock-out capability is an alternate function of register. It can output three selectable frequencies
an I/O port pin that outputs the fCPU clock to drive on the BEEP pin (I/O port alternate function).
Figure 34. Main Clock Controller (MCC/RTC) Block Diagram
BC1 BC0
MCCBCR
BEEP
BEEP SIGNAL
SELECTION
MCO
12-BIT MCC RTC TO

DIV 64
COUNTER WATCHDOG
TIMER
MCO CP1 CP0 SMS TB1 TB0 OIE OIF
MCCSR MCC/RTC INTERRUPT

fOSC2
DIV 2, 4, 8, 16 1
fCPU CPU CLOCK
TO CPU AND
0 PERIPHERALS
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MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK (Cont’d)

Mode Description
Bit 6:5 = CP[1:0] CPU clock prescaler
These bits select the CPU clock prescaler which is
No effect on MCC/RTC peripheral. applied in the different slow modes. Their action is
WAIT MCC/RTC interrupt cause the device to exit conditioned by the setting of the SMS bit. These
from WAIT mode. two bits are set and cleared by software
No effect on MCC/RTC counter (OIE bit is
ACTIVE- set), the registers are frozen. fCPU in SLOW mode CP1 CP0
HALT MCC/RTC interrupt cause the device to exit fOSC2 / 2 0 0
from ACTIVE-HALT mode.
fOSC2 / 4 0 1
MCC/RTC counter and registers are frozen.
MCC/RTC operation resumes when the fOSC2 / 8 1 0
HALT
MCU is woken up by an interrupt with “exit fOSC2 / 16 1 1
from HALT” capability.
10.2.6 Interrupts Bit 4 = SMS Slow mode select

The MCC/RTC interrupt event generates an inter- This bit is set and cleared by software.
rupt if the OIE bit of the MCCSR register is set and 0: Normal mode. fCPU = fOSC2
the interrupt mask in the CC register is not active 1: Slow mode. fCPU is given by CP1, CP0
(RIM instruction). See Section 8.2 SLOW MODE and Section 10.2
MAIN CLOCK CONTROLLER WITH REAL TIME
Enable Exit Exit CLOCK AND BEEPER (MCC/RTC) for more de-
Event tails.
Flag
Bit Wait Halt
Time base overflow Bit 3:2 = TB[1:0] Time base control
OIF OIE Yes No 1)
event
These bits select the programmable divider time
Note: base. They are set and cleared by software.
The MCC/RTC interrupt wakes up the MCU from Time Base
Counter
ACTIVE-HALT mode, not from HALT mode. TB1 TB0
Prescaler f
OSC2 =4MHz fOSC2=8MHz
16000 4ms 2ms 0 0

10.2.7 Register Description 32000 8ms 4ms 0 1
MCC CONTROL/STATUS REGISTER (MCCSR) 80000 20ms 10ms 1 0

200000 50ms 25ms 1 1
Read/Write
Reset Value: 0000 0000 (00h) A modification of the time base is taken into ac-
count at the end of the current period (previously
7 0 set) to avoid an unwanted time shift. This allows to
use this time base as a real time clock.
MCO CP1 CP0 SMS TB1 TB0 OIE OIF
Bit 1 = OIE Oscillator interrupt enable
Bit 7 = MCO Main clock out selection This bit set and cleared by software.
This bit enables the MCO alternate function on the 0: Oscillator interrupt disabled
PF0 I/O port. It is set and cleared by software. 1: Oscillator interrupt enabled
0: MCO alternate function disabled (I/O pin free for This interrupt can be used to exit from ACTIVE-
general-purpose I/O) HALT mode.
1: MCO alternate function enabled (fCPU on I/O When this bit is set, calling the ST7 software HALT
port) instruction enters the ACTIVE-HALT power saving
Note: To reduce power consumption, the MCO mode.
function is not active in ACTIVE-HALT mode.
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MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK (Cont’d)

Bit 0 = OIF Oscillator interrupt flag MCC BEEP CONTROL REGISTER (MCCBCR)
This bit is set by hardware and cleared by software Read/Write
reading the MCCSR register. It indicates when set
that the main oscillator has reached the selected Reset Value: 0000 0000 (00h)
elapsed time (TB1:0).
0: Timeout not reached 7 0
1: Timeout reached
0 0 0 0 0 0 BC1 BC0
CAUTION: The BRES and BSET instructions
must not be used on the MCCSR register to avoid
unintentionally clearing the OIF bit. Bit 7:2 = Reserved, must be kept cleared.
Bit 1:0 = BC[1:0] Beep control

These 2 bits select the PF1 pin beep capability.
BC1 BC0 Beep mode with fOSC2=8MHz
0 0 Off
0 1 ~2-KHz
Output
1 0 ~1-KHz Beep signal
~50% duty cycle
1 1 ~500-Hz
The beep output signal is available in ACTIVE-

HALT mode but has to be disabled to reduce the
consumption.
Table 15. Main Clock Controller Register Map and Reset Values
Address Register
7 6 5 4 3 2 1 0
(Hex.) Label
SICSR AVDIE AVDF LVDRF WDGRF
002Bh
Reset Value 0 0 0 x 0 0 0 x
MCCSR MCO CP1 CP0 SMS TB1 TB0 OIE OIF
002Ch
Reset Value 0 0 0 0 0 0 0 0
MCCBCR BC1 BC0
002Dh
Reset Value 0 0 0 0 0 0 0 0
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10.3 16-BIT TIMER

10.3.1 Introduction When reading an input signal on a non-bonded
The timer consists of a 16-bit free-running counter pin, the value will always be ‘1’.
driven by a programmable prescaler. 10.3.3 Functional Description
It may be used for a variety of purposes, including 10.3.3.1 Counter
pulse length measurement of up to two input sig- The main block of the Programmable Timer is a
nals (input capture) or generation of up to two out- 16-bit free running upcounter and its associated
put waveforms (output compare and PWM). 16-bit registers. The 16-bit registers are made up
Pulse lengths and waveform periods can be mod- of two 8-bit registers called high & low.
ulated from a few microseconds to several milli- Counter Register (CR):
seconds using the timer prescaler and the CPU
clock prescaler. – Counter High Register (CHR) is the most sig-
nificant byte (MS Byte).
Some ST7 devices have two on-chip 16-bit timers.
They are completely independent, and do not – Counter Low Register (CLR) is the least sig-
share any resources. They are synchronized after nificant byte (LS Byte).
a MCU reset as long as the timer clock frequen- Alternate Counter Register (ACR)
cies are not modified. – Alternate Counter High Register (ACHR) is
This description covers one or two 16-bit timers. In the most significant byte (MS Byte).
ST7 devices with two timers, register names are – Alternate Counter Low Register (ACLR) is the
prefixed with TA (Timer A) or TB (Timer B). least significant byte (LS Byte).
10.3.2 Main Features These two read-only 16-bit registers contain the
same value but with the difference that reading the
■ Programmable prescaler: fCPU divided by 2, 4 or 8.
ACLR register does not clear the TOF bit (Timer
■ Overflow status flag and maskable interrupt overflow flag), located in the Status register, (SR),
■ External clock input (must be at least 4 times (see note at the end of paragraph titled 16-bit read
slower than the CPU clock speed) with the choice sequence).
of active edge Writing in the CLR register or ACLR register resets
■ 1 or 2 Output Compare functions each with: the free running counter to the FFFCh value.
Both counters have a reset value of FFFCh (this is
– 2 dedicated 16-bit registers
the only value which is reloaded in the 16-bit tim-
– 2 dedicated programmable signals er). The reset value of both counters is also
– 2 dedicated status flags FFFCh in One Pulse mode and PWM mode.
– 1 dedicated maskable interrupt
■ 1 or 2 Input Capture functions each with: The timer clock depends on the clock control bits
– 2 dedicated 16-bit registers of the CR2 register, as illustrated in Table 16 Clock
Control Bits. The value in the counter register re-
– 2 dedicated active edge selection signals peats every 131072, 262144 or 524288 CPU clock
– 2 dedicated status flags cycles depending on the CC[1:0] bits.
The timer frequency can be fCPU/2, fCPU/4, fCPU/8
– 1 dedicated maskable interrupt
or an external frequency.
■ Pulse width modulation mode (PWM)
■ One pulse mode

Caution: In Flash devices, Timer A functionality
■ Reduced Power Mode
has the following restrictions:
■ 5 alternate functions on I/O ports (ICAP1, ICAP2,
– TAOC2HR and TAOC2LR registers are write
OCMP1, OCMP2, EXTCLK)*
only
– Input Capture 2 is not implemented
The Block Diagram is shown in Figure 35.
– The corresponding interrupts cannot be used
*Note: Some timer pins may not be available (not (ICF2, OCF2 forced by hardware to zero)
bonded) in some ST7 devices. Refer to the device
pin out description.
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16-BIT TIMER (Cont’d)

Figure 35. Timer Block Diagram
ST7 INTERNAL BUS
fCPU
MCU-PERIPHERAL INTERFACE
8 high 8 low
8-bit 8 8 8 8 8 8 8 8
buffer
high
high
high
high
low
low
low
low
EXEDG
16
1/2 OUTPUT OUTPUT INPUT INPUT

COUNTER
COMPARE COMPARE CAPTURE CAPTURE
1/4
REGISTER REGISTER REGISTER REGISTER REGISTER
1/8
1 2 1 2
EXTCLK ALTERNATE
pin COUNTER
16 16
REGISTER
16
CC[1:0]
TIMER INTERNAL BUS
16 16
OVERFLOW
OUTPUT COMPARE EDGE DETECT ICAP1
DETECT
CIRCUIT CIRCUIT1 pin
CIRCUIT
6 EDGE DETECT ICAP2

CIRCUIT2 pin
LATCH1 OCMP1
pin
ICF1 OCF1 TOF ICF2 OCF2 TIMD 0 0
(Control/Status Register) LATCH2 OCMP2
CSR pin
ICIE OCIE TOIE FOLV2 FOLV1 OLVL2 IEDG1 OLVL1 OC1E OC2E OPM PWM CC1 CC0 IEDG2 EXEDG
(Control Register 1) CR1 (Control Register 2) CR2
(See note)
TIMER INTERRUPT Note: If IC, OC and TO interrupt requests have separate vectors
then the last OR is not present (See device Interrupt Vector Table)
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16-bit read sequence: (from either the Counter Clearing the overflow interrupt request is done in
Register or the Alternate Counter Register). two steps:
Beginning of the sequence 1. Reading the SR register while the TOF bit is set.
2. An access (read or write) to the CLR register.
Read LS Byte Notes: The TOF bit is not cleared by accesses to
At t0 MS Byte is buffered ACLR register. The advantage of accessing the
ACLR register rather than the CLR register is that
Other it allows simultaneous use of the overflow function
instructions and reading the free running counter at random
times (for example, to measure elapsed time) with-
Read Returns the buffered out the risk of clearing the TOF bit erroneously.
At t0 +∆t LS Byte LS Byte value at t0 The timer is not affected by WAIT mode.
Sequence completed In HALT mode, the counter stops counting until the
mode is exited. Counting then resumes from the
The user must read the MS Byte first, then the LS previous count (MCU awakened by an interrupt) or
Byte value is buffered automatically. from the reset count (MCU awakened by a Reset).
This buffered value remains unchanged until the
16-bit read sequence is completed, even if the 10.3.3.2 External Clock
user reads the MS Byte several times.
The external clock (where available) is selected if
After a complete reading sequence, if only the CC0=1 and CC1=1 in the CR2 register.
CLR register or ACLR register are read, they re-
The status of the EXEDG bit in the CR2 register
turn the LS Byte of the count value at the time of
determines the type of level transition on the exter-
the read.
nal clock pin EXTCLK that will trigger the free run-
Whatever the timer mode used (input capture, out- ning counter.
put compare, one pulse mode or PWM mode) an
The counter is synchronized with the falling edge
overflow occurs when the counter rolls over from
of the internal CPU clock.
FFFFh to 0000h then:
A minimum of four falling edges of the CPU clock
– The TOF bit of the SR register is set.
must occur between two consecutive active edges
– A timer interrupt is generated if: of the external clock; thus the external clock fre-
– TOIE bit of the CR1 register is set and quency must be less than a quarter of the CPU
clock frequency.
– I bit of the CC register is cleared.
If one of these conditions is false, the interrupt re-
mains pending to be issued as soon as they are
both true.
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Figure 36. Counter Timing Diagram, internal clock divided by 2
CPU CLOCK
INTERNAL RESET
TIMER CLOCK
FFFD FFFE FFFF 0000 0001 0002 0003

COUNTER REGISTER
TIMER OVERFLOW FLAG (TOF)
CPU CLOCK
INTERNAL RESET
TIMER CLOCK
COUNTER REGISTER FFFC FFFD 0000 0001
CPU CLOCK
INTERNAL RESET
TIMER CLOCK
COUNTER REGISTER FFFC FFFD 0000
Note: The MCU is in reset state when the internal reset signal is high, when it is low the MCU is running.
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10.3.3.3 Input Capture When an input capture occurs:
In this section, the index, i, may be 1 or 2 because – ICFi bit is set.
there are 2 input capture functions in the 16-bit – The ICiR register contains the value of the free
timer. running counter on the active transition on the
The two 16-bit input capture registers (IC1R and ICAPi pin (see Figure 40).
IC2R) are used to latch the value of the free run- – A timer interrupt is generated if the ICIE bit is set
ning counter after a transition is detected on the and the I bit is cleared in the CC register. Other-
ICAPi pin (see figure 5). wise, the interrupt remains pending until both
MS Byte LS Byte conditions become true.
ICiR ICiHR ICiLR Clearing the Input Capture interrupt request (i.e.
clearing the ICFi bit) is done in two steps:
ICiR register is a read-only register. 1. Reading the SR register while the ICFi bit is set.
The active transition is software programmable 2. An access (read or write) to the ICiLR register.
through the IEDGi bit of Control Registers (CRi).
Timing resolution is one count of the free running
counter: (fCPU/CC[1:0]). Notes:
1. After reading the ICiHR register, transfer of
input capture data is inhibited and ICFi will
Procedure: never be set until the ICiLR register is also
To use the input capture function select the follow- read.
ing in the CR2 register: 2. The ICiR register contains the free running
– Select the timer clock (CC[1:0]) (see Table 16 counter value which corresponds to the most
Clock Control Bits). recent input capture.
– Select the edge of the active transition on the 3. The 2 input capture functions can be used
ICAP2 pin with the IEDG2 bit (the ICAP2 pin together even if the timer also uses the 2 output
must be configured as floating input or input with compare functions.
pull-up without interrupt if this configuration is 4. In One pulse Mode and PWM mode only Input
available). Capture 2 can be used.
And select the following in the CR1 register: 5. The alternate inputs (ICAP1 & ICAP2) are
– Set the ICIE bit to generate an interrupt after an always directly connected to the timer. So any
input capture coming from either the ICAP1 pin transitions on these pins activates the input
or the ICAP2 pin capture function.
– Select the edge of the active transition on the Moreover if one of the ICAPi pins is configured
ICAP1 pin with the IEDG1 bit (the ICAP1pin must as an input and the second one as an output,
be configured as floating input or input with pull- an interrupt can be generated if the user tog-
up without interrupt if this configuration is availa- gles the output pin and if the ICIE bit is set.
ble). This can be avoided if the input capture func-
tion i is disabled by reading the ICiHR (see note
1).
6. The TOF bit can be used with interrupt genera-
tion in order to measure events that go beyond
the timer range (FFFFh).
7. In Flash devices, the ICAP2 registers
(TAIC2HR, TAIC2LR) are not available on
Timer A. The corresponding interrupts cannot
be used (ICF2 is forced by hardware to 0).
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Figure 39. Input Capture Block Diagram
ICAP1 (Control Register 1) CR1

pin
EDGE DETECT EDGE DETECT ICIE IEDG1
ICAP2 CIRCUIT2 CIRCUIT1
pin (Status Register) SR
IC2R Register IC1R Register ICF1 ICF2 0 0 0
(Control Register 2) CR2

16-BIT
16-BIT FREE RUNNING CC1 CC0 IEDG2
COUNTER
Figure 40. Input Capture Timing Diagram
TIMER CLOCK
COUNTER REGISTER FF01 FF02 FF03
ICAPi PIN
ICAPi FLAG
ICAPi REGISTER FF03
Note: The rising edge is the active edge.
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10.3.3.4 Output Compare – The OCMPi pin takes OLVLi bit value (OCMPi
In this section, the index, i, may be 1 or 2 because pin latch is forced low during reset).
there are 2 output compare functions in the 16-bit – A timer interrupt is generated if the OCIE bit is
timer. set in the CR1 register and the I bit is cleared in
This function can be used to control an output the CC register (CC).
waveform or indicate when a period of time has
elapsed. The OCiR register value required for a specific tim-
When a match is found between the Output Com- ing application can be calculated using the follow-
pare register and the free running counter, the out- ing formula:
put compare function:
– Assigns pins with a programmable value if the ∆t * fCPU
OCiE bit is set ∆ OCiR =
PRESC
– Sets a flag in the status register
Where:
– Generates an interrupt if enabled
∆t = Output compare period (in seconds)
Two 16-bit registers Output Compare Register 1
(OC1R) and Output Compare Register 2 (OC2R) fCPU = CPU clock frequency (in hertz)
contain the value to be compared to the counter PRESC = Timer prescaler factor (2, 4 or 8 de-
register each timer clock cycle. pending on CC[1:0] bits, see Table 16
MS Byte LS Byte
Clock Control Bits)
OCiR OCiHR OCiLR
If the timer clock is an external clock, the formula
These registers are readable and writable and are is:
not affected by the timer hardware. A reset event
changes the OCiR value to 8000h. ∆ OCiR = ∆t * fEXT
Timing resolution is one count of the free running Where:
counter: (fCPU/CC[1:0]).
∆t = Output compare period (in seconds)
fEXT = External timer clock frequency (in hertz)
Procedure:
To use the output compare function, select the fol-
lowing in the CR2 register: Clearing the output compare interrupt request (i.e.
clearing the OCFi bit) is done by:
– Set the OCiE bit if an output is needed then the
OCMPi pin is dedicated to the output compare i 1. Reading the SR register while the OCFi bit is
signal. set.
– Select the timer clock (CC[1:0]) (see Table 16 2. An access (read or write) to the OCiLR register.
Clock Control Bits). The following procedure is recommended to pre-
And select the following in the CR1 register: vent the OCFi bit from being set between the time
it is read and the write to the OCiR register:
– Select the OLVLi bit to applied to the OCMPi pins
after the match occurs. – Write to the OCiHR register (further compares
are inhibited).
– Set the OCIE bit to generate an interrupt if it is
needed. – Read the SR register (first step of the clearance
of the OCFi bit, which may be already set).
When a match is found between OCRi register
and CR register: – Write to the OCiLR register (enables the output
compare function and clears the OCFi bit).
– OCFi bit is set.
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Notes: 6. In Flash devices, the TAOC2HR, TAOC2LR
1. After a processor write cycle to the OCiHR reg- registers are “write only” in Timer A. The corre-
ister, the output compare function is inhibited sponding event cannot be generated (OCF2 is
until the OCiLR register is also written. forced by hardware to 0).
2. If the OCiE bit is not set, the OCMPi pin is a Forced Compare Output capability
general I/O port and the OLVLi bit will not When the FOLVi bit is set by software, the OLVLi
appear when a match is found but an interrupt bit is copied to the OCMPi pin. The OLVi bit has to
could be generated if the OCIE bit is set. be toggled in order to toggle the OCMPi pin when
3. When the timer clock is fCPU/2, OCFi and it is enabled (OCiE bit=1). The OCFi bit is then not
OCMPi are set while the counter value equals set by hardware, and thus no interrupt request is
the OCiR register value (see Figure 42 on page generated.
67). This behaviour is the same in OPM or The FOLVLi bits have no effect in both one pulse
PWM mode. mode and PWM mode.
When the timer clock is fCPU/4, fCPU/8 or in
external clock mode, OCFi and OCMPi are set
while the counter value equals the OCiR regis-
ter value plus 1 (see Figure 43 on page 67).
4. The output compare functions can be used both
for generating external events on the OCMPi
pins even if the input capture mode is also
used.
5. The value in the 16-bit OCiR register and the
OLVi bit should be changed after each suc-
cessful comparison in order to control an output
waveform or establish a new elapsed timeout.
Figure 41. Output Compare Block Diagram
16 BIT FREE RUNNING OC1E OC2E CC1 CC0

COUNTER
16-bit
OUTPUT COMPARE Latch
OCIE FOLV2 FOLV1 OLVL2 OLVL1 OCMP1
CIRCUIT 1
Pin
16-bit 16-bit
Latch
2
OCMP2
OC1R Register Pin
OCF1 OCF2 0 0 0
OC2R Register
(Status Register) SR
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Figure 42. Output Compare Timing Diagram, fTIMER =fCPU/2
INTERNAL CPU CLOCK
TIMER CLOCK
COUNTER REGISTER 2ECF 2ED0 2ED1 2ED2 2ED3 2ED4
OUTPUT COMPARE REGISTER i (OCRi) 2ED3
OUTPUT COMPARE FLAG i (OCFi)
OCMPi PIN (OLVLi=1)
Figure 43. Output Compare Timing Diagram, fTIMER =fCPU/4
INTERNAL CPU CLOCK
TIMER CLOCK
COUNTER REGISTER 2ECF 2ED0 2ED1 2ED2 2ED3 2ED4
OUTPUT COMPARE REGISTER i (OCRi) 2ED3
COMPARE REGISTER i LATCH
OUTPUT COMPARE FLAG i (OCFi)
OCMPi PIN (OLVLi=1)
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10.3.3.5 One Pulse Mode Clearing the Input Capture interrupt request (i.e.
One Pulse mode enables the generation of a clearing the ICFi bit) is done in two steps:
pulse when an external event occurs. This mode is 1. Reading the SR register while the ICFi bit is set.
selected via the OPM bit in the CR2 register. 2. An access (read or write) to the ICiLR register.
The one pulse mode uses the Input Capture1 The OC1R register value required for a specific
function and the Output Compare1 function. timing application can be calculated using the fol-
Procedure: lowing formula:
To use one pulse mode: t * fCPU -5
OCiR Value =
1. Load the OC1R register with the value corre- PRESC
sponding to the length of the pulse (see the for- Where:
mula in the opposite column). t = Pulse period (in seconds)
2. Select the following in the CR1 register: fCPU = CPU clock frequency (in hertz)
– Using the OLVL1 bit, select the level to be ap-
plied to the OCMP1 pin after the pulse. PRESC = Timer prescaler factor (2, 4 or 8 depend-
ing on the CC[1:0] bits, see Table 16
– Using the OLVL2 bit, select the level to be ap- Clock Control Bits)
plied to the OCMP1 pin during the pulse. If the timer clock is an external clock the formula is:
– Select the edge of the active transition on the OCiR = t * fEXT -5
ICAP1 pin with the IEDG1 bit (the ICAP1 pin
must be configured as floating input). Where:
3. Select the following in the CR2 register: t = Pulse period (in seconds)
– Set the OC1E bit, the OCMP1 pin is then ded- fEXT = External timer clock frequency (in hertz)
icated to the Output Compare 1 function.
– Set the OPM bit.
When the value of the counter is equal to the value
– Select the timer clock CC[1:0] (see Table 16 of the contents of the OC1R register, the OLVL1
Clock Control Bits). bit is output on the OCMP1 pin, (See Figure 44).
Notes:
One pulse mode cycle 1. The OCF1 bit cannot be set by hardware in one
pulse mode but the OCF2 bit can generate an
ICR1 = Counter Output Compare interrupt.
When
event occurs OCMP1 = OLVL2 2. When the Pulse Width Modulation (PWM) and
on ICAP1 Counter is reset One Pulse Mode (OPM) bits are both set, the
to FFFCh PWM mode is the only active one.
3. If OLVL1=OLVL2 a continuous signal will be
ICF1 bit is set
seen on the OCMP1 pin.
When 4. The ICAP1 pin can not be used to perform input
Counter capture. The ICAP2 pin can be used to perform
= OC1R OCMP1 = OLVL1
input capture (ICF2 can be set and IC2R can be
loaded) but the user must take care that the
counter is reset each time a valid edge occurs
Then, on a valid event on the ICAP1 pin, the coun- on the ICAP1 pin and ICF1 can also generates
ter is initialized to FFFCh and OLVL2 bit is loaded interrupt if ICIE is set.
on the OCMP1 pin, the ICF1 bit is set and the val-
ue FFFDh is loaded in the IC1R register. 5. When one pulse mode is used OC1R is dedi-
cated to this mode. Nevertheless OC2R and
Because the ICF1 bit is set when an active edge OCF2 can be used to indicate a period of time
occurs, an interrupt can be generated if the ICIE has been elapsed but cannot generate an out-
bit is set. put waveform because the level OLVL2 is dedi-
cated to the one pulse mode.
6. In Flash devices, Timer A OCF2 bit is forced by
hardware to 0.
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Figure 44. One Pulse Mode Timing Example
IC1R 01F8 2ED3
01F8 FFFC FFFD FFFE 2ED0 2ED1 2ED2 FFFC FFFD

COUNTER
2ED3
ICAP1
OCMP1 OLVL2 OLVL1 OLVL2

compare1
Note: IEDG1=1, OC1R=2ED0h, OLVL1=0, OLVL2=1
Figure 45. Pulse Width Modulation Mode Timing Example with 2 Output Compare Functions
COUNTER 34E2 FFFC FFFD FFFE 2ED0 2ED1 2ED2 34E2 FFFC
OLVL2 OLVL1 OLVL2

OCMP1
compare2 compare1 compare2
Note: OC1R=2ED0h, OC2R=34E2, OLVL1=0, OLVL2= 1
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10.3.3.6 Pulse Width Modulation Mode If OLVL1=1 and OLVL2=0 the length of the posi-
Pulse Width Modulation (PWM) mode enables the tive pulse is the difference between the OC2R and
generation of a signal with a frequency and pulse OC1R registers.
length determined by the value of the OC1R and If OLVL1=OLVL2 a continuous signal will be seen
OC2R registers. on the OCMP1 pin.
Pulse Width Modulation mode uses the complete The OCiR register value required for a specific tim-
Output Compare 1 function plus the OC2R regis- ing application can be calculated using the follow-
ter, and so this functionality can not be used when ing formula:
PWM mode is activated. t * fCPU - 5
OCiR Value =
In PWM mode, double buffering is implemented on PRESC
the output compare registers. Any new values writ-
ten in the OC1R and OC2R registers are taken Where:
into account only at the end of the PWM period t = Signal or pulse period (in seconds)
(OC2) to avoid spikes on the PWM output pin fCPU = CPU clock frequency (in hertz)
(OCMP1).
PRESC = Timer prescaler factor (2, 4 or 8 depend-
Procedure ing on CC[1:0] bits, see Table 16)
To use pulse width modulation mode: If the timer clock is an external clock the formula is:
1. Load the OC2R register with the value corre- OCiR = t * fEXT -5
sponding to the period of the signal using the Where:
formula in the opposite column.
t = Signal or pulse period (in seconds)
2. Load the OC1R register with the value corre-
sponding to the period of the pulse if (OLVL1=0 fEXT = External timer clock frequency (in hertz)
and OLVL2=1) using the formula in the oppo- The Output Compare 2 event causes the counter
site column. to be initialized to FFFCh (See Figure 45)
3. Select the following in the CR1 register: Notes:
– Using the OLVL1 bit, select the level to be ap- 1. After a write instruction to the OCiHR register,
plied to the OCMP1 pin after a successful the output compare function is inhibited until the
comparison with the OC1R register. OCiLR register is also written.
– Using the OLVL2 bit, select the level to be ap- 2. The OCF1 and OCF2 bits cannot be set by
plied to the OCMP1 pin after a successful hardware in PWM mode therefore the Output
comparison with the OC2R register. Compare interrupt is inhibited.
4. Select the following in the CR2 register: 3. The ICF1 bit is set by hardware when the coun-
– Set OC1E bit: the OCMP1 pin is then dedicat- ter reaches the OC2R value and can produce a
ed to the output compare 1 function. timer interrupt if the ICIE bit is set and the I bit is
cleared.
– Set the PWM bit.
4. In PWM mode the ICAP1 pin can not be used
– Select the timer clock (CC[1:0]) (see Table 16
Clock Control Bits). to perform input capture because it is discon-
nected to the timer. The ICAP2 pin can be used
Pulse Width Modulation cycle to perform input capture (ICF2 can be set and
IC2R can be loaded) but the user must take
care that the counter is reset each period and
When ICF1 can also generates interrupt if ICIE is set.
Counter OCMP1 = OLVL1
= OC1R 5. When the Pulse Width Modulation (PWM) and
One Pulse Mode (OPM) bits are both set, the
PWM mode is the only active one.
When OCMP1 = OLVL2 6. In Flash devices, the TAOC2HR, TAOC2LR
Counter Counter is reset registers in Timer A are “write only”. A read
= OC2R to FFFCh operation returns an undefined value.
ICF1 bit is set 7. In Flash devices, the ICAP2 registers
(TAIC2HR, TAIC2LR) are not available in Timer A.
The ICF2 bit is forced by hardware to 0.
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Mode Description
No effect on 16-bit Timer.
WAIT
Timer interrupts cause the device to exit from WAIT mode.
16-bit Timer registers are frozen.
In HALT mode, the counter stops counting until Halt mode is exited. Counting resumes from the previous
count when the MCU is woken up by an interrupt with “exit from HALT mode” capability or from the counter
HALT reset value when the MCU is woken up by a RESET.
If an input capture event occurs on the ICAPi pin, the input capture detection circuitry is armed. Consequent-
ly, when the MCU is woken up by an interrupt with “exit from HALT mode” capability, the ICFi bit is set, and
the counter value present when exiting from HALT mode is captured into the ICiR register.
10.3.5 Interrupts
Enable Exit Exit
Event
Flag
Bit Wait Halt
Input Capture 1 event/Counter reset in PWM mode ICF1 Yes No
ICIE
Input Capture 2 event ICF2* Yes No
Output Compare 1 event (not available in PWM mode) OCF1 Yes No
OCIE
Output Compare 2 event (not available in PWM mode) OCF2* Yes No
Timer Overflow event TOF TOIE Yes No
Note: The 16-bit Timer interrupt events are connected to the same interrupt vector (see Interrupts chap-
ter). These events generate an interrupt if the corresponding Enable Control Bit is set and the interrupt
mask in the CC register is reset (RIM instruction).
* In Flash devices, the ICF2 and OCF2 bits are forced by hardware to 0 in Timer A, hence there is no in-
terrupt event for these flags.
10.3.6 Summary of Timer modes
TIMER RESOURCES
MODES
Input Capture 1 Input Capture 2 Output Compare 1 Output Compare 2
Input Capture (1 and/or 2) Yes Yes2)5) Yes Yes4)
5)
Output Compare (1 and/or 2) Yes Yes Yes Yes4)
Not
One Pulse Mode No No Partially 2)
Recommended1)5)
Not
PWM Mode No No No
Recommended3)5)
1) See note 4 in Section 10.3.3.5 One Pulse Mode

2) See note 5 and 6 in Section 10.3.3.5 One Pulse Mode
3) See note 4 in Section 10.3.3.6 Pulse Width Modulation Mode
4) In Flash devices, the TAOC2HR, TAOC2LR registers are write only in Timer A. Output Compare 2
event cannot be generated, OCF2 is forced by hardware to 0.
5) In Flash devices, Input Capture 2 is not implemented in Timer A. ICF2 bit is forced by hardware to 0.
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10.3.7 Register Description Bit 4 = FOLV2 Forced Output Compare 2.
Each Timer is associated with three control and This bit is set and cleared by software.
status registers, and with six pairs of data registers 0: No effect on the OCMP2 pin.
(16-bit values) relating to the two input captures, 1: Forces the OLVL2 bit to be copied to the
the two output compares, the counter and the al- OCMP2 pin, if the OC2E bit is set and even if
ternate counter. there is no successful comparison.
CONTROL REGISTER 1 (CR1) Bit 3 = FOLV1 Forced Output Compare 1.

This bit is set and cleared by software.
Read/Write 0: No effect on the OCMP1 pin.
Reset Value: 0000 0000 (00h) 1: Forces OLVL1 to be copied to the OCMP1 pin, if
7 0 the OC1E bit is set and even if there is no suc-
cessful comparison.
ICIE OCIE TOIE FOLV2 FOLV1 OLVL2 IEDG1 OLVL1
Bit 2 = OLVL2 Output Level 2.
Bit 7 = ICIE Input Capture Interrupt Enable. This bit is copied to the OCMP2 pin whenever a
0: Interrupt is inhibited. successful comparison occurs with the OC2R reg-
1: A timer interrupt is generated whenever the ister and OCxE is set in the CR2 register. This val-
ICF1 or ICF2 bit of the SR register is set. ue is copied to the OCMP1 pin in One Pulse Mode
and Pulse Width Modulation mode.
Bit 6 = OCIE Output Compare Interrupt Enable.

0: Interrupt is inhibited. Bit 1 = IEDG1 Input Edge 1.
1: A timer interrupt is generated whenever the This bit determines which type of level transition
OCF1 or OCF2 bit of the SR register is set. on the ICAP1 pin will trigger the capture.
0: A falling edge triggers the capture.
1: A rising edge triggers the capture.
Bit 5 = TOIE Timer Overflow Interrupt Enable.
0: Interrupt is inhibited.
1: A timer interrupt is enabled whenever the TOF Bit 0 = OLVL1 Output Level 1.
bit of the SR register is set. The OLVL1 bit is copied to the OCMP1 pin when-
ever a successful comparison occurs with the
OC1R register and the OC1E bit is set in the CR2
register.
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CONTROL REGISTER 2 (CR2) Bit 4 = PWM Pulse Width Modulation.
Read/Write 0: PWM mode is not active.
1: PWM mode is active, the OCMP1 pin outputs a
Reset Value: 0000 0000 (00h) programmable cyclic signal; the length of the
7 0
pulse depends on the value of OC1R register;
the period depends on the value of OC2R regis-
ter.
OC1E OC2E OPM PWM CC1 CC0 IEDG2 EXEDG
Bit 3, 2 = CC[1:0] Clock Control.

Bit 7 = OC1E Output Compare 1 Pin Enable.
The timer clock mode depends on these bits:
This bit is used only to output the signal from the
timer on the OCMP1 pin (OLV1 in Output Com- Table 16. Clock Control Bits
pare mode, both OLV1 and OLV2 in PWM and
one-pulse mode). Whatever the value of the OC1E Timer Clock CC1 CC0
bit, the Output Compare 1 function of the timer re- fCPU / 4 0 0
mains active. fCPU / 2 0 1
0: OCMP1 pin alternate function disabled (I/O pin fCPU / 8 1 0
free for general-purpose I/O).
1: OCMP1 pin alternate function enabled. External Clock (where
1 1
available)
Bit 6 = OC2E Output Compare 2 Pin Enable.

This bit is used only to output the signal from the Note: If the external clock pin is not available, pro-
timer on the OCMP2 pin (OLV2 in Output Com- gramming the external clock configuration stops
pare mode). Whatever the value of the OC2E bit, the counter.
the Output Compare 2 function of the timer re-
mains active. Bit 1 = IEDG2 Input Edge 2.
0: OCMP2 pin alternate function disabled (I/O pin This bit determines which type of level transition
free for general-purpose I/O). on the ICAP2 pin will trigger the capture.
1: OCMP2 pin alternate function enabled. 0: A falling edge triggers the capture.
Note: In Flash devices, this bit is not available for 1: A rising edge triggers the capture.
Timer A. It must be kept at its reset value.
Bit 0 = EXEDG External Clock Edge.
Bit 5 = OPM One Pulse Mode. This bit determines which type of level transition
0: One Pulse Mode is not active. on the external clock pin EXTCLK will trigger the
1: One Pulse Mode is active, the ICAP1 pin can be counter register.
used to trigger one pulse on the OCMP1 pin; the 0: A falling edge triggers the counter register.
active transition is given by the IEDG1 bit. The 1: A rising edge triggers the counter register.
length of the generated pulse depends on the
contents of the OC1R register.
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CONTROL/STATUS REGISTER (CSR)
Read Only (except bit 2 R/W) Bit 4 = ICF2 Input Capture Flag 2.
Reset Value: xxxx x0xx (xxh) 0: No input capture (reset value).
1: An input capture has occurred on the ICAP2
7 0 pin. To clear this bit, first read the SR register,
then read or write the low byte of the IC2R
ICF1 OCF1 TOF ICF2 OCF2 TIMD 0 0
(IC2LR) register.
Note: In Flash devices, this bit is not available for
Bit 7 = ICF1 Input Capture Flag 1. Timer A and is forced by hardware to 0.
0: No input capture (reset value).
1: An input capture has occurred on the ICAP1 pin Bit 3 = OCF2 Output Compare Flag 2.
or the counter has reached the OC2R value in 0: No match (reset value).
PWM mode. To clear this bit, first read the SR 1: The content of the free running counter has
register, then read or write the low byte of the matched the content of the OC2R register. To
IC1R (IC1LR) register. clear this bit, first read the SR register, then read
or write the low byte of the OC2R (OC2LR) reg-
Bit 6 = OCF1 Output Compare Flag 1. ister.
0: No match (reset value). Note: In Flash devices, this bit is not available for
1: The content of the free running counter has Timer A and is forced by hardware to 0.
matched the content of the OC1R register. To
clear this bit, first read the SR register, then read
or write the low byte of the OC1R (OC1LR) reg- Bit 2 = TIMD Timer disable.
ister. This bit is set and cleared by software. When set, it
freezes the timer prescaler and counter and disa-
bled the output functions (OCMP1 and OCMP2
Bit 5 = TOF Timer Overflow Flag. pins) to reduce power consumption. Access to the
0: No timer overflow (reset value). timer registers is still available, allowing the timer
1: The free running counter rolled over from FFFFh configuration to be changed, or the counter reset,
to 0000h. To clear this bit, first read the SR reg- while it is disabled.
ister, then read or write the low byte of the CR 0: Timer enabled
(CLR) register. 1: Timer prescaler, counter and outputs disabled
Note: Reading or writing the ACLR register does
not clear TOF. Bits 1:0 = Reserved, must be kept cleared.
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INPUT CAPTURE 1 HIGH REGISTER (IC1HR) OUTPUT COMPARE 1 HIGH REGISTER
Read Only (OC1HR)
Reset Value: Undefined Read/Write
This is an 8-bit read only register that contains the Reset Value: 1000 0000 (80h)
high part of the counter value (transferred by the This is an 8-bit register that contains the high part
input capture 1 event). of the value to be compared to the CHR register.
7 0 7 0
MSB LSB MSB LSB
INPUT CAPTURE 1 LOW REGISTER (IC1LR) OUTPUT COMPARE 1 LOW REGISTER

Read Only (OC1LR)
Reset Value: Undefined Read/Write
This is an 8-bit read only register that contains the Reset Value: 0000 0000 (00h)
low part of the counter value (transferred by the in- This is an 8-bit register that contains the low part of
put capture 1 event). the value to be compared to the CLR register.
7 0 7 0
MSB LSB MSB LSB
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OUTPUT COMPARE 2 HIGH REGISTER
(OC2HR) COUNTER HIGH REGISTER (CHR)
Read/Write Read Only
Reset Value: 1000 0000 (80h) Reset Value: 1111 1111 (FFh)
This is an 8-bit register that contains the high part This is an 8-bit register that contains the high part
of the value to be compared to the CHR register. of the counter value.
7 0 7 0
MSB LSB MSB LSB
Note: In Flash devices, the Timer A OC2HR regis-

ter is write-only.
COUNTER LOW REGISTER (CLR)
Read Only
OUTPUT COMPARE 2 LOW REGISTER Reset Value: 1111 1100 (FCh)
(OC2LR)
This is an 8-bit register that contains the low part of
Read/Write the counter value. A write to this register resets the
Reset Value: 0000 0000 (00h) counter. An access to this register after accessing
This is an 8-bit register that contains the low part of the CSR register clears the TOF bit.
the value to be compared to the CLR register.
7 0
7 0
MSB LSB
MSB LSB
Note: In Flash devices, the Timer A OC2LR regis-

ter is write-only.
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ALTERNATE COUNTER HIGH REGISTER INPUT CAPTURE 2 HIGH REGISTER (IC2HR)

(ACHR) Read Only
Read Only Reset Value: Undefined
Reset Value: 1111 1111 (FFh) This is an 8-bit read only register that contains the
This is an 8-bit register that contains the high part high part of the counter value (transferred by the
of the counter value. Input Capture 2 event).
7 0 7 0
MSB LSB MSB LSB
Note: In Flash devices, this register is not imple-

ALTERNATE COUNTER LOW REGISTER mented for Timer A.
(ACLR)
Read Only INPUT CAPTURE 2 LOW REGISTER (IC2LR)
Reset Value: 1111 1100 (FCh) Read Only
This is an 8-bit register that contains the low part of Reset Value: Undefined
the counter value. A write to this register resets the This is an 8-bit read only register that contains the
counter. An access to this register after an access low part of the counter value (transferred by the In-
to CSR register does not clear the TOF bit in the put Capture 2 event).
CSR register.
7 0
7 0
MSB LSB
MSB LSB
Note: In Flash devices, this register is not imple-

mented for Timer A.
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Table 17. 16-Bit Timer Register Map and Reset Values
Address Register
7 6 5 4 3 2 1 0
(Hex.) Label
Timer A: 32 CR1 ICIE OCIE TOIE FOLV21 FOLV1 OLVL2 IEDG1 OLVL1
Timer B: 42 Reset Value 0 0 0 0 0 0 0 0
Timer A: 31 CR2 OC1E OC2E1 OPM PWM CC1 CC0 IEDG21 EXEDG
Timer A: 33 CSR ICF1 OCF1 TOF ICF22 OCF22 TIMD - -
Timer B: 43 Reset Value x x x x x 0 x x
Timer A: 34 IC1HR MSB LSB
Timer B: 44 Reset Value x x x x x x x x
Timer A: 35 IC1LR MSB LSB
Timer B: 45 Reset Value x x x x x x x x
Timer A: 36 OC1HR MSB LSB
Timer A: 37 OC1LR MSB LSB
Timer A: 3E3 OC2HR MSB LSB
Timer B: 4E Reset Value 1 0 0 0 0 0 0 0
Timer A: 3F3 OC2LR MSB LSB
Timer B: 4F Reset Value 0 0 0 0 0 0 0 0
Timer A: 38 CHR MSB LSB
Timer A: 39 CLR MSB LSB
Timer A: 3A ACHR MSB LSB
Timer B: 4A Reset Value 1 1 1 1 1 1 1 1
Timer A: 3B ACLR MSB LSB
Timer B: 4B Reset Value 1 1 1 1 1 1 0 0
Timer A: 3C4 IC2HR MSB LSB
Timer B: 4C Reset Value x x x x x x x x
Timer A: 3D4 IC2LR MSB LSB
Timer B: 4D Reset Value x x x x x x x x
1
In Flash devices, these bits are not used in Timer A and must be kept cleared.
2 In Flash devices, these bits are forced by hardware to 0 in Timer A
3
In Flash devices, the TAOC2HR and TAOC2LR Registers are write only, reading them will return unde-
fined values
4
In Flash devices, the TAIC2HR and TAIC2LR registers are not present.
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10.4 SERIAL PERIPHERAL INTERFACE (SPI)

10.4.1 Introduction Note: In slave mode, continuous transmission is
The Serial Peripheral Interface (SPI) allows full- not possible at maximum frequency due to the
duplex, synchronous, serial communication with software overhead for clearing status flags and to
external devices. An SPI system may consist of a initiate the next transmission sequence.
master and one or more slaves however the SPI 10.4.3 General Description
interface can not be a master in a multi-master Figure 46 shows the serial peripheral interface
system. (SPI) block diagram. There are 3 registers:
10.4.2 Main Features – SPI Control Register (SPICR)
■ Full duplex synchronous transfers (on 3 lines)
– SPI Control/Status Register (SPICSR)
■ Simplex synchronous transfers (on 2 lines)
– SPI Data Register (SPIDR)
■ Master or slave operation
The SPI is connected to external devices through
■ Six master mode frequencies (fCPU/4 max.)
4 pins:
■ fCPU/2 max. slave mode frequency (see note)
– MISO: Master In / Slave Out data
■ SS Management by software or hardware
– MOSI: Master Out / Slave In data
■ Programmable clock polarity and phase
– SCK: Serial Clock out by SPI masters and in-
■ End of transfer interrupt flag
put by SPI slaves
■ Write collision, Master Mode Fault and Overrun
flags
Figure 46. Serial Peripheral Interface Block Diagram
Data/Address Bus
SPIDR Read
Interrupt
request
Read Buffer
MOSI
7 SPICSR 0
MISO 8-Bit Shift Register
SPIF WCOL OVR MODF 0 SOD SSM SSI
Write
SOD
bit 1
SS
SPI 0
SCK STATE
CONTROL
7 SPICR 0
SPIE SPE SPR2 MSTR CPOL CPHA SPR1 SPR0

MASTER
CONTROL
SERIAL CLOCK
GENERATOR
SS
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SERIAL PERIPHERAL INTERFACE (Cont’d)

– SS: Slave select: The communication is always initiated by the mas-
This input signal acts as a ‘chip select’ to let ter. When the master device transmits data to a
the SPI master communicate with slaves indi- slave device via MOSI pin, the slave device re-
vidually and to avoid contention on the data sponds by sending data to the master device via
lines. Slave SS inputs can be driven by stand- the MISO pin. This implies full duplex communica-
ard I/O ports on the master MCU. tion with both data out and data in synchronized
10.4.3.1 Functional Description with the same clock signal (which is provided by
the master device via the SCK pin).
A basic example of interconnections between a
single master and a single slave is illustrated in To use a single data line, the MISO and MOSI pins
Figure 47. must be connected at each node (in this case only
simplex communication is possible).
The MOSI pins are connected together and the
MISO pins are connected together. In this way Four possible data/clock timing relationships may
data is transferred serially between master and be chosen (see Figure 50) but master and slave
slave (most significant bit first). must be programmed with the same timing mode.
Figure 47. Single Master/ Single Slave Application
MASTER SLAVE
MSBit LSBit MSBit LSBit
MISO MISO
8-BIT SHIFT REGISTER 8-BIT SHIFT REGISTER
MOSI MOSI
SPI
SCK SCK
CLOCK
GENERATOR
SS SS
+5V
Not used if SS is managed
by software
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10.4.3.2 Slave Select Management In Slave Mode:
As an alternative to using the SS pin to control the There are two cases depending on the data/clock
Slave Select signal, the application can choose to timing relationship (see Figure 48):
manage the Slave Select signal by software. This If CPHA=1 (data latched on 2nd clock edge):
is configured by the SSM bit in the SPICSR regis-
ter (see Figure 49) – SS internal must be held low during the entire
transmission. This implies that in single slave
In software management, the external SS pin is applications the SS pin either can be tied to
free for other application uses and the internal SS VSS, or made free for standard I/O by manag-
signal level is driven by writing to the SSI bit in the ing the SS function by software (SSM= 1 and
SSI=0 in the in the SPICSR register)
SPICSR register.
If CPHA=0 (data latched on 1st clock edge):
In Master mode:
– SS internal must be held low during byte
– SS internal must be held high continuously transmission and pulled high between each
byte to allow the slave to write to the shift reg-
ister. If SS is not pulled high, a Write Collision
error will occur when the slave writes to the
shift register (see Section 10.4.5.3).
Figure 48. Generic SS Timing Diagram
MOSI/MISO Byte 1 Byte 2 Byte 3
Master SS
Slave SS
(if CPHA=0)
Slave SS
(if CPHA=1)
Figure 49. Hardware/Software Slave Select Management
SSM bit
SSI bit 1
SS internal
SS external pin 0
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10.4.3.3 Master Mode Operation Note: While the SPIF bit is set, all writes to the
In master mode, the serial clock is output on the SPIDR register are inhibited until the SPICSR reg-
SCK pin. The clock frequency, polarity and phase ister is read.
are configured by software (refer to the description 10.4.3.5 Slave Mode Operation
of the SPICSR register). In slave mode, the serial clock is received on the
Note: The idle state of SCK must correspond to SCK pin from the master device.
the polarity selected in the SPICSR register (by To operate the SPI in slave mode:
pulling up SCK if CPOL=1 or pulling down SCK if
CPOL=0). 1. Write to the SPICSR register to perform the fol-
lowing actions:
To operate the SPI in master mode, perform the
following steps in order (if the SPICSR register is – Select the clock polarity and clock phase by
configuring the CPOL and CPHA bits (see
not written first, the SPICR register setting (MSTR Figure 50).
bit) may be not taken into account): Note: The slave must have the same CPOL
1. Write to the SPICR register: and CPHA settings as the master.
– Manage the SS pin as described in Section
– Select the clock frequency by configuring the 10.4.3.2 and Figure 48. If CPHA=1 SS must
SPR[2:0] bits. be held low continuously. If CPHA=0 SS must
– Select the clock polarity and clock phase by be held low during byte transmission and
configuring the CPOL and CPHA bits. Figure pulled up between each byte to let the slave
50 shows the four possible configurations. write in the shift register.
Note: The slave must have the same CPOL 2. Write to the SPICR register to clear the MSTR
and CPHA settings as the master.
bit and set the SPE bit to enable the SPI I/O
2. Write to the SPICSR register: functions.
– Either set the SSM bit and set the SSI bit or 10.4.3.6 Slave Mode Transmit Sequence
clear the SSM bit and tie the SS pin high for
the complete byte transmit sequence. When software writes to the SPIDR register, the
3. Write to the SPICR register: data byte is loaded into the 8-bit shift register and
– Set the MSTR and SPE bits then shifted out serially to the MISO pin most sig-
Note: MSTR and SPE bits remain set only if nificant bit first.
SS is high). The transmit sequence begins when the slave de-
The transmit sequence begins when software vice receives the clock signal and the most signifi-
writes a byte in the SPIDR register. cant bit of the data on its MOSI pin.
10.4.3.4 Master Mode Transmit Sequence When data transfer is complete:
When software writes to the SPIDR register, the – The SPIF bit is set by hardware
data byte is loaded into the 8-bit shift register and
– An interrupt request is generated if SPIE bit is
then shifted out serially to the MOSI pin most sig-
set and interrupt mask in the CCR register is
nificant bit first.
cleared.
When data transfer is complete: Clearing the SPIF bit is performed by the following
– The SPIF bit is set by hardware software sequence:
– An interrupt request is generated if the SPIE 1. An access to the SPICSR register while the
bit is set and the interrupt mask in the CCR SPIF bit is set.
register is cleared.
2. A write or a read to the SPIDR register.
Clearing the SPIF bit is performed by the following
Notes: While the SPIF bit is set, all writes to the
software sequence:
SPIDR register are inhibited until the SPICSR reg-
1. An access to the SPICSR register while the ister is read.
SPIF bit is set
The SPIF bit can be cleared during a second
2. A read to the SPIDR register. transmission; however, it must be cleared before
the second SPIF bit in order to prevent an Overrun
condition (see Section 10.4.5.2).
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10.4.4 Clock Phase and Clock Polarity Figure 50, shows an SPI transfer with the four
Four possible timing relationships may be chosen combinations of the CPHA and CPOL bits. The di-
by software, using the CPOL and CPHA bits (See agram may be interpreted as a master or slave
Figure 50). timing diagram where the SCK pin, the MISO pin,
the MOSI pin are directly connected between the
Note: The idle state of SCK must correspond to master and the slave device.
the polarity selected in the SPICSR register (by
pulling up SCK if CPOL=1 or pulling down SCK if Note: If CPOL is changed at the communication
CPOL=0). byte boundaries, the SPI must be disabled by re-
setting the SPE bit.
The combination of the CPOL clock polarity and
CPHA (clock phase) bits selects the data capture
clock edge
Figure 50. Data Clock Timing Diagram
CPHA =1
SCK
(CPOL = 1)
SCK
(CPOL = 0)
MISO MSBit Bit 6 Bit 5 Bit 4 Bit3 Bit 2 Bit 1 LSBit

(from master)
MOSI MSBit Bit 6 Bit 5 Bit 4 Bit3 Bit 2 Bit 1 LSBit

(from slave)
SS
(to slave)
CAPTURE STROBE
CPHA =0
SCK
(CPOL = 1)
SCK
(CPOL = 0)
MISO MSBit Bit 6 Bit 5 Bit 4 Bit3 Bit 2 Bit 1 LSBit

(from master)
MOSI MSBit Bit 6 Bit 5 Bit 4 Bit3 Bit 2 Bit 1 LSBit

(from slave)
SS
(to slave)
CAPTURE STROBE
Note: This figure should not be used as a replacement for parametric information.
Refer to the Electrical Characteristics chapter.
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10.4.5 Error Flags not cleared the SPIF bit issued from the previously
10.4.5.1 Master Mode Fault (MODF) transmitted byte.
Master mode fault occurs when the master device When an Overrun occurs:
has its SS pin pulled low. – The OVR bit is set and an interrupt request is
When a Master mode fault occurs: generated if the SPIE bit is set.
– The MODF bit is set and an SPI interrupt re- In this case, the receiver buffer contains the byte
quest is generated if the SPIE bit is set. sent after the SPIF bit was last cleared. A read to
the SPIDR register returns this byte. All other
– The SPE bit is reset. This blocks all output bytes are lost.
from the device and disables the SPI periph-
eral. The OVR bit is cleared by reading the SPICSR
register.
– The MSTR bit is reset, thus forcing the device
into slave mode. 10.4.5.3 Write Collision Error (WCOL)
Clearing the MODF bit is done through a software A write collision occurs when the software tries to
sequence: write to the SPIDR register while a data transfer is
taking place with an external device. When this
1. A read access to the SPICSR register while the happens, the transfer continues uninterrupted;
MODF bit is set. and the software write will be unsuccessful.
2. A write to the SPICR register. Write collisions can occur both in master and slave
Notes: To avoid any conflicts in an application mode. See also Section 10.4.3.2 Slave Select
with multiple slaves, the SS pin must be pulled Management.
high during the MODF bit clearing sequence. The Note: a “read collision” will never occur since the
SPE and MSTR bits may be restored to their orig- received data byte is placed in a buffer in which
inal state during or after this clearing sequence. access is always synchronous with the MCU oper-
Hardware does not allow the user to set the SPE ation.
and MSTR bits while the MODF bit is set except in The WCOL bit in the SPICSR register is set if a
the MODF bit clearing sequence. write collision occurs.
10.4.5.2 Overrun Condition (OVR) No SPI interrupt is generated when the WCOL bit
An overrun condition occurs, when the master de- is set (the WCOL bit is a status flag only).
vice has sent a data byte and the slave device has Clearing the WCOL bit is done through a software
sequence (see Figure 51).
Figure 51. Clearing the WCOL bit (Write Collision Flag) Software Sequence
Clearing sequence after SPIF = 1 (end of a data byte transfer)
Read SPICSR
1st Step
RESULT
2nd Step Read SPIDR SPIF =0
WCOL=0
Clearing sequence before SPIF = 1 (during a data byte transfer)
Read SPICSR
1st Step
RESULT Note: Writing to the SPIDR regis-
ter instead of reading it does not
2nd Step Read SPIDR WCOL=0 reset the WCOL bit
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10.4.5.4 Single Master Systems Note: To prevent a bus conflict on the MISO line
A typical single master system may be configured, the master allows only one active slave device
using an MCU as the master and four MCUs as during a transmission.
slaves (see Figure 52). For more security, the slave device may respond
The master device selects the individual slave de- to the master with the received data byte. Then the
vices by using four pins of a parallel port to control master will receive the previous byte back from the
the four SS pins of the slave devices. slave device if all MISO and MOSI pins are con-
nected and the slave has not written to its SPIDR
The SS pins are pulled high during reset since the register.
master device ports will be forced to be inputs at
that time, thus disabling the slave devices. Other transmission security methods can use
ports for handshake lines or data bytes with com-
mand fields.
Figure 52. Single Master / Multiple Slave Configuration
SS SS SS SS
SCK SCK SCK SCK
Slave Slave Slave Slave
MCU MCU MCU MCU
MOSI MISO MOSI MISO MOSI MISO MOSI MISO
MOSI MISO
SCK
Ports
Master
MCU
5V SS
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10.4.6 Low Power Modes Note: When waking up from Halt mode, if the SPI
remains in Slave mode, it is recommended to per-
Mode Description
form an extra communications cycle to bring the
No effect on SPI. SPI from Halt mode state to normal state. If the
WAIT SPI interrupt events cause the device to exit SPI exits from Slave mode, it returns to normal
from WAIT mode. state immediately.
SPI registers are frozen.
In HALT mode, the SPI is inactive. SPI oper-
Caution: The SPI can wake up the ST7 from Halt
ation resumes when the MCU is woken up by
mode only if the Slave Select signal (external SS
an interrupt with “exit from HALT mode” ca- pin or the SSI bit in the SPICSR register) is low
pability. The data received is subsequently when the ST7 enters Halt mode. So if Slave selec-
HALT read from the SPIDR register when the soft- tion is configured as external (see Section
ware is running (interrupt vector fetching). If 10.4.3.2), make sure the master drives a low level
several data are received before the wake- on the SS pin when the slave enters Halt mode.
up event, then an overrun error is generated. 10.4.7 Interrupts
This error can be detected after the fetch of
the interrupt routine that woke up the device. Enable Exit Exit
Event
Flag
Bit Wait Halt
10.4.6.1 Using the SPI to wakeup the MCU from
Halt mode SPI End of Transfer
SPIF Yes Yes
Event
In slave configuration, the SPI is able to wakeup Master Mode Fault SPIE
the ST7 device from HALT mode through a SPIF MODF Yes No
Event
interrupt. The data received is subsequently read
Overrun Error OVR Yes No
from the SPIDR register when the software is run-
ning (interrupt vector fetch). If multiple data trans-
Note: The SPI interrupt events are connected to
fers have been performed before software clears
the same interrupt vector (see Interrupts chapter).
the SPIF bit, then the OVR bit is set by hardware.
They generate an interrupt if the corresponding
Enable Control Bit is set and the interrupt mask in
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CONTROL REGISTER (SPICR)
Read/Write Bit 3 = CPOL Clock Polarity.
Reset Value: 0000 xxxx (0xh) This bit is set and cleared by software. This bit de-
termines the idle state of the serial Clock. The
7 0
CPOL bit affects both the master and slave
modes.
SPIE SPE SPR2 MSTR CPOL CPHA SPR1 SPR0
0: SCK pin has a low level idle state
1: SCK pin has a high level idle state
Note: If CPOL is changed at the communication
Bit 7 = SPIE Serial Peripheral Interrupt Enable. byte boundaries, the SPI must be disabled by re-
This bit is set and cleared by software. setting the SPE bit.
0: Interrupt is inhibited
1: An SPI interrupt is generated whenever Bit 2 = CPHA Clock Phase.
SPIF=1, MODF=1 or OVR=1 in the SPICSR This bit is set and cleared by software.
register 0: The first clock transition is the first data capture
edge.
Bit 6 = SPE Serial Peripheral Output Enable. 1: The second clock transition is the first capture
This bit is set and cleared by software. It is also edge.
cleared by hardware when, in master mode, SS=0 Note: The slave must have the same CPOL and
(see Section 10.4.5.1 Master Mode Fault CPHA settings as the master.
(MODF)). The SPE bit is cleared by reset, so the
SPI peripheral is not initially connected to the ex-
ternal pins. Bits 1:0 = SPR[1:0] Serial Clock Frequency.
0: I/O pins free for general purpose I/O These bits are set and cleared by software. Used
1: SPI I/O pin alternate functions enabled with the SPR2 bit, they select the baud rate of the
SPI serial clock SCK output by the SPI in master
mode.
Bit 5 = SPR2 Divider Enable. Note: These 2 bits have no effect in slave mode.
This bit is set and cleared by software and is
cleared by reset. It is used with the SPR[1:0] bits to Table 18. SPI Master mode SCK Frequency
set the baud rate. Refer to Table 18 SPI Master
mode SCK Frequency. Serial Clock SPR2 SPR1 SPR0
0: Divider by 2 enabled fCPU/4 1 0 0
1: Divider by 2 disabled
fCPU/8 0 0 0
Note: This bit has no effect in slave mode.
fCPU/16 0 0 1
fCPU/32 1 1 0
Bit 4 = MSTR Master Mode.
This bit is set and cleared by software. It is also fCPU/64 0 1 0
cleared by hardware when, in master mode, SS=0 fCPU/128 0 1 1
(see Section 10.4.5.1 Master Mode Fault
(MODF)).
0: Slave mode
1: Master mode. The function of the SCK pin
changes from an input to an output and the func-
tions of the MISO and MOSI pins are reversed.
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CONTROL/STATUS REGISTER (SPICSR) Bit 3 = Reserved, must be kept cleared.
Read/Write (some bits Read Only)
Reset Value: 0000 0000 (00h)
Bit 2 = SOD SPI Output Disable.
7 0 This bit is set and cleared by software. When set, it
disables the alternate function of the SPI output
SPIF WCOL OVR MODF - SOD SSM SSI (MOSI in master mode / MISO in slave mode)
0: SPI output enabled (if SPE=1)
1: SPI output disabled
Bit 7 = SPIF Serial Peripheral Data Transfer Flag
(Read only).
This bit is set by hardware when a transfer has Bit 1 = SSM SS Management.
been completed. An interrupt is generated if This bit is set and cleared by software. When set, it
SPIE=1 in the SPICR register. It is cleared by a disables the alternate function of the SPI SS pin
software sequence (an access to the SPICSR and uses the SSI bit value instead. See Section
register followed by a write or a read to the 10.4.3.2 Slave Select Management.
SPIDR register). 0: Hardware management (SS managed by exter-
0: Data transfer is in progress or the flag has been nal pin)
cleared. 1: Software management (internal SS signal con-
1: Data transfer between the device and an exter- trolled by SSI bit. External SS pin free for gener-
nal device has been completed. al-purpose I/O)
Note: While the SPIF bit is set, all writes to the
SPIDR register are inhibited until the SPICSR reg- Bit 0 = SSI SS Internal Mode.
ister is read. This bit is set and cleared by software. It acts as a
‘chip select’ by controlling the level of the SS slave
select signal when the SSM bit is set.
Bit 6 = WCOL Write Collision status (Read only). 0: Slave selected
This bit is set by hardware when a write to the 1: Slave deselected
SPIDR register is done during a transmit se-
quence. It is cleared by a software sequence (see
Figure 51). DATA I/O REGISTER (SPIDR)
0: No write collision occurred Read/Write
1: A write collision has been detected Reset Value: Undefined
7 0
Bit 5 = OVR SPI Overrun error (Read only).
This bit is set by hardware when the byte currently D7 D6 D5 D4 D3 D2 D1 D0
being received in the shift register is ready to be
transferred into the SPIDR register while SPIF = 1
(See Section 10.4.5.2). An interrupt is generated if The SPIDR register is used to transmit and receive
SPIE = 1 in SPICR register. The OVR bit is cleared data on the serial bus. In a master device, a write
by software reading the SPICSR register. to this register will initiate transmission/reception
0: No overrun error of another byte.
1: Overrun error detected Notes: During the last clock cycle the SPIF bit is
set, a copy of the received data byte in the shift
register is moved to a buffer. When the user reads
Bit 4 = MODF Mode Fault flag (Read only). the serial peripheral data I/O register, the buffer is
This bit is set by hardware when the SS pin is actually being read.
pulled low in master mode (see Section 10.4.5.1
Master Mode Fault (MODF)). An SPI interrupt can While the SPIF bit is set, all writes to the SPIDR
be generated if SPIE=1 in the SPICSR register. register are inhibited until the SPICSR register is
This bit is cleared by a software sequence (An ac- read.
cess to the SPICR register while MODF=1 fol- Warning: A write to the SPIDR register places
lowed by a write to the SPICR register). data directly into the shift register for transmission.
0: No master mode fault detected
A read to the SPIDR register returns the value lo-
1: A fault in master mode has been detected
cated in the buffer and not the content of the shift
register (see Figure 46).
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Table 19. SPI Register Map and Reset Values
Address Register
7 6 5 4 3 2 1 0
(Hex.) Label
SPIDR MSB LSB
0021h
Reset Value x x x x x x x x
SPICR SPIE SPE SPR2 MSTR CPOL CPHA SPR1 SPR0
0022h
Reset Value 0 0 0 0 x x x x
SPICSR SPIF WCOL OR MODF SOD SSM SSI
0023h
Reset Value 0 0 0 0 0 0 0 0
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10.5 SERIAL COMMUNICATIONS INTERFACE (SCI)

10.5.1 Introduction 10.5.3 General Description
The Serial Communications Interface (SCI) offers The interface is externally connected to another
a flexible means of full-duplex data exchange with device by two pins (see Figure 2.):
external equipment requiring an industry standard – TDO: Transmit Data Output. When the transmit-
NRZ asynchronous serial data format. The SCI of- ter and the receiver are disabled, the output pin
fers a very wide range of baud rates using two returns to its I/O port configuration. When the
baud rate generator systems. transmitter and/or the receiver are enabled and
10.5.2 Main Features nothing is to be transmitted, the TDO pin is at
■ Full duplex, asynchronous communications high level.
■ NRZ standard format (Mark/Space) – RDI: Receive Data Input is the serial data input.
■ Dual baud rate generator systems
Oversampling techniques are used for data re-
covery by discriminating between valid incoming
■ Independently programmable transmit and data and noise.
receive baud rates up to 500K baud
Through these pins, serial data is transmitted and
■ Programmable data word length (8 or 9 bits)
received as frames comprising:
■ Receive buffer full, Transmit buffer empty and
– An Idle Line prior to transmission or reception
End of Transmission flags
■ Two receiver wake-up modes:
– A start bit
– Address bit (MSB) – A data word (8 or 9 bits) least significant bit first
– Idle line – A Stop bit indicating that the frame is complete
■ Muting function for multiprocessor configurations This interface uses two types of baud rate generator:
■ Separate enable bits for Transmitter and – A conventional type for commonly-used baud
Receiver rates
■ Four error detection flags: – An extended type with a prescaler offering a very
– Overrun error wide range of baud rates even with non-standard
oscillator frequencies
– Noise error
– Frame error
– Parity error
■ Five interrupt sources with flags:
– Transmit data register empty

– Transmission complete
– Receive data register full
– Idle line received
– Overrun error detected
■ Parity control:
– Transmits parity bit

– Checks parity of received data byte
■ Reduced power consumption mode
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SERIAL COMMUNICATIONS INTERFACE (Cont’d)

Figure 53. SCI Block Diagram
Write Read (DATA REGISTER) DR
Transmit Data Register (TDR) Received Data Register (RDR)
TDO
Transmit Shift Register Received Shift Register
RDI
CR1
R8 T8 SCID M WAKE PCE PS PIE
WAKE
TRANSMIT UP RECEIVER RECEIVER
CONTROL UNIT CONTROL CLOCK
CR2 SR
TIE TCIE RIE ILIE TE RE RWU SBK TDRE TC RDRF IDLE OR NF FE PE
SCI
INTERRUPT
CONTROL
TRANSMITTER
CLOCK
TRANSMITTER RATE
CONTROL
fCPU
/16 /PR
BRR
SCP1 SCP0 SCT2 SCT1 SCT0 SCR2 SCR1SCR0
RECEIVER RATE
CONTROL
CONVENTIONAL BAUD RATE GENERATOR
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10.5.4 Functional Description 10.5.4.1 Serial Data Format
The block diagram of the Serial Control Interface, Word length may be selected as being either 8 or 9
is shown in Figure 1. It contains six dedicated reg- bits by programming the M bit in the SCICR1 reg-
isters: ister (see Figure 1.).
– Two control registers (SCICR1 & SCICR2) The TDO pin is in low state during the start bit.
– A status register (SCISR) The TDO pin is in high state during the stop bit.
– A baud rate register (SCIBRR) An Idle character is interpreted as an entire frame
– An extended prescaler receiver register (SCIER- of “1”s followed by the start bit of the next frame
PR) which contains data.
– An extended prescaler transmitter register (SCI- A Break character is interpreted on receiving “0”s
ETPR) for some multiple of the frame period. At the end of
the last break frame the transmitter inserts an ex-
Refer to the register descriptions in Section 0.1.7 tra “1” bit to acknowledge the start bit.
for the definitions of each bit.
Transmission and reception are driven by their
own baud rate generator.
Figure 54. Word Length Programming
9-bit Word length (M bit is set)

Possible Next Data Frame
Parity
Data Frame Bit Next
Start Stop Start
Bit Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Bit8 Bit
Bit
Start
Idle Frame Bit
Break Frame Extra Start

‘1’ Bit
8-bit Word length (M bit is reset)

Possible Next Data Frame
Data Frame Parity
Bit Next
Start Stop Start
Bit Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Bit
Bit
Start
Idle Frame Bit
Break Frame Extra Start

‘1’ Bit
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10.5.4.2 Transmitter When a frame transmission is complete (after the
The transmitter can send data words of either 8 or stop bit) the TC bit is set and an interrupt is gener-
9 bits depending on the M bit status. When the M ated if the TCIE is set and the I bit is cleared in the
bit is set, word length is 9 bits and the 9th bit (the CCR register.
MSB) has to be stored in the T8 bit in the SCICR1 Clearing the TC bit is performed by the following
register. software sequence:
Character Transmission 1. An access to the SCISR register
During an SCI transmission, data shifts out least 2. A write to the SCIDR register
significant bit first on the TDO pin. In this mode, Note: The TDRE and TC bits are cleared by the
the SCIDR register consists of a buffer (TDR) be- same software sequence.
tween the internal bus and the transmit shift regis-
ter (see Figure 1.). Break Characters
Procedure Setting the SBK bit loads the shift register with a
break character. The break frame length depends
– Select the M bit to define the word length. on the M bit (see Figure 2.).
– Select the desired baud rate using the SCIBRR As long as the SBK bit is set, the SCI send break
and the SCIETPR registers. frames to the TDO pin. After clearing this bit by
– Set the TE bit to assign the TDO pin to the alter- software the SCI insert a logic 1 bit at the end of
nate function and to send a idle frame as first the last break frame to guarantee the recognition
transmission. of the start bit of the next frame.
– Access the SCISR register and write the data to Idle Characters
send in the SCIDR register (this sequence clears Setting the TE bit drives the SCI to send an idle
the TDRE bit). Repeat this sequence for each frame before the first data frame.
data to be transmitted.
Clearing and then setting the TE bit during a trans-
Clearing the TDRE bit is always performed by the mission sends an idle frame after the current word.
following software sequence:
Note: Resetting and setting the TE bit causes the
1. An access to the SCISR register data in the TDR register to be lost. Therefore the
2. A write to the SCIDR register best time to toggle the TE bit is when the TDRE bit
The TDRE bit is set by hardware and it indicates: is set, that is, before writing the next byte in the
SCIDR.
– The TDR register is empty.
– The data transfer is beginning.
– The next data can be written in the SCIDR regis-
ter without overwriting the previous data.
This flag generates an interrupt if the TIE bit is set
and the I bit is cleared in the CCR register.
When a transmission is taking place, a write in-
struction to the SCIDR register stores the data in
the TDR register and which is copied in the shift
register at the end of the current transmission.
When no transmission is taking place, a write in-
struction to the SCIDR register places the data di-
rectly in the shift register, the data transmission
starts, and the TDRE bit is immediately set.
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10.5.4.3 Receiver RDR register as long as the RDRF bit is not
The SCI can receive data words of either 8 or 9 cleared.
bits. When the M bit is set, word length is 9 bits When an overrun error occurs:
and the MSB is stored in the R8 bit in the SCICR1 – The OR bit is set.
register.
– The RDR content is not lost.
Character reception
– The shift register is overwritten.
During a SCI reception, data shifts in least signifi-
cant bit first through the RDI pin. In this mode, the – An interrupt is generated if the RIE bit is set and
SCIDR register consists or a buffer (RDR) be- the I bit is cleared in the CCR register.
tween the internal bus and the received shift regis- The OR bit is reset by an access to the SCISR reg-
ter (see Figure 1.). ister followed by a SCIDR register read operation.
Procedure Noise Error
– Select the M bit to define the word length. Oversampling techniques are used for data recov-
– Select the desired baud rate using the SCIBRR ery by discriminating between valid incoming data
and the SCIERPR registers. and noise. Normal data bits are considered valid if
three consecutive samples (8th, 9th, 10th) have
– Set the RE bit, this enables the receiver which the same bit value, otherwise the NF flag is set. In
begins searching for a start bit. the case of start bit detection, the NF flag is set on
When a character is received: the basis of an algorithm combining both valid
– The RDRF bit is set. It indicates that the content edge detection and three samples (8th, 9th, 10th).
of the shift register is transferred to the RDR. Therefore, to prevent the NF flag getting set during
start bit reception, there should be a valid edge de-
– An interrupt is generated if the RIE bit is set and tection as well as three valid samples.
the I bit is cleared in the CCR register.
When noise is detected in a frame:
– The error flags can be set if a frame error, noise
or an overrun error has been detected during re- – The NF flag is set at the rising edge of the RDRF
ception. bit.
Clearing the RDRF bit is performed by the following – Data is transferred from the Shift register to the
software sequence done by: SCIDR register.
1. An access to the SCISR register – No interrupt is generated. However this bit rises
at the same time as the RDRF bit which itself
2. A read to the SCIDR register. generates an interrupt.
The RDRF bit must be cleared before the end of the The NF flag is reset by a SCISR register read op-
reception of the next character to avoid an overrun eration followed by a SCIDR register read opera-
error. tion.
Break Character During reception, if a false start bit is detected (e.g.
When a break character is received, the SCI han- 8th, 9th, 10th samples are 011,101,110), the
dles it as a framing error. frame is discarded and the receiving sequence is
Idle Character not started for this frame. There is no RDRF bit set
for this frame and the NF flag is set internally (not
When a idle frame is detected, there is the same accessible to the user). This NF flag is accessible
procedure as a data received character plus an in- along with the RDRF bit when a next valid frame is
terrupt if the ILIE bit is set and the I bit is cleared in received.
the CCR register.
Note: If the application Start Bit is not long enough
Overrun Error to match the above requirements, then the NF
An overrun error occurs when a character is re- Flag may get set due to the short Start Bit. In this
ceived when RDRF has not been reset. Data can case, the NF flag may be ignored by the applica-
not be transferred from the shift register to the tion software when the first valid byte is received.
See also Section 0.1.4.10 .
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Figure 55. SCI Baud Rate and Extended Prescaler Block Diagram
TRANSMITTER
CLOCK
EXTENDED PRESCALER TRANSMITTER RATE CONTROL
SCIETPR
EXTENDED TRANSMITTER PRESCALER REGISTER
SCIERPR
EXTENDED RECEIVER PRESCALER REGISTER
RECEIVER
CLOCK
EXTENDED PRESCALER RECEIVER RATE CONTROL
EXTENDED PRESCALER
fCPU
TRANSMITTER RATE
CONTROL
/16 /PR
SCIBRR
SCP1 SCP0 SCT2 SCT1 SCT0 SCR2 SCR1SCR0
RECEIVER RATE
CONTROL
CONVENTIONAL BAUD RATE GENERATOR
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Framing Error Note: the extended prescaler is activated by set-
A framing error is detected when: ting the SCIETPR or SCIERPR register to a value
other than zero. The baud rates are calculated as
– The stop bit is not recognized on reception at the follows:
expected time, following either a de-synchroni-
zation or excessive noise. fCPU fCPU
– A break is received. Tx = Rx =
16*ETPR*(PR*TR) 16*ERPR*(PR*RR)
When the framing error is detected:
– the FE bit is set by hardware
with:
– Data is transferred from the Shift register to the
SCIDR register. ETPR = 1,..,255 (see SCIETPR register)
– No interrupt is generated. However this bit rises ERPR = 1,.. 255 (see SCIERPR register)
at the same time as the RDRF bit which itself 10.5.4.6 Receiver Muting and Wake-up Feature
generates an interrupt. In multiprocessor configurations it is often desira-
The FE bit is reset by a SCISR register read oper- ble that only the intended message recipient
ation followed by a SCIDR register read operation. should actively receive the full message contents,
10.5.4.4 Conventional Baud Rate Generation thus reducing redundant SCI service overhead for
all non addressed receivers.
The baud rate for the receiver and transmitter (Rx
and Tx) are set independently and calculated as The non addressed devices may be placed in
follows: sleep mode by means of the muting function.
Setting the RWU bit by software puts the SCI in
fCPU fCPU
Tx = Rx = sleep mode:
(16*PR)*TR (16*PR)*RR All the reception status bits can not be set.
with: All the receive interrupts are inhibited.
PR = 1, 3, 4 or 13 (see SCP[1:0] bits) A muted receiver may be awakened by one of the
following two ways:
TR = 1, 2, 4, 8, 16, 32, 64,128
– by Idle Line detection if the WAKE bit is reset,
(see SCT[2:0] bits)
– by Address Mark detection if the WAKE bit is set.
RR = 1, 2, 4, 8, 16, 32, 64,128
Receiver wakes-up by Idle Line detection when
(see SCR[2:0] bits) the Receive line has recognized an Idle Frame.
All these bits are in the SCIBRR register. Then the RWU bit is reset by hardware but the
IDLE bit is not set.
Example: If fCPU is 8 MHz (normal mode) and if
PR = 13 and TR = RR = 1, the transmit and re- Receiver wakes-up by Address Mark detection
ceive baud rates are 38400 baud. when it received a “1” as the most significant bit of
a word, thus indicating that the message is an ad-
Note: The baud rate registers MUST NOT be
dress. The reception of this particular word wakes
changed while the transmitter or the receiver is en-
up the receiver, resets the RWU bit and sets the
abled.
RDRF bit, which allows the receiver to receive this
10.5.4.5 Extended Baud Rate Generation word normally and to use it as an address word.
The extended prescaler option gives a very fine CAUTION: In Mute mode, do not write to the
tuning on the baud rate, using a 255 value prescal- SCICR2 register. If the SCI is in Mute mode during
er, whereas the conventional Baud Rate Genera- the read operation (RWU = 1) and a address mark
tor retains industry standard software compatibili- wake up event occurs (RWU is reset) before the
ty. write operation, the RWU bit is set again by this
The extended baud rate generator block diagram write operation. Consequently the address byte is
is described in the Figure 3. lost and the SCI is not woken up from Mute mode.
The output clock rate sent to the transmitter or to
the receiver is the output from the 16 divider divid-
ed by a factor ranging from 1 to 255 set in the SCI-
ERPR or the SCIETPR register.
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10.5.4.7 Parity Control even number of “1s” if even parity is selected
Parity control (generation of parity bit in transmis- (PS = 0) or an odd number of “1s” if odd parity is
sion and parity checking in reception) can be ena- selected (PS = 1). If the parity check fails, the PE
bled by setting the PCE bit in the SCICR1 register. flag is set in the SCISR register and an interrupt is
Depending on the frame length defined by the M generated if PIE is set in the SCICR1 register.
bit, the possible SCI frame formats are as listed in 10.5.4.8 SCI Clock Tolerance
Table 1. During reception, each bit is sampled 16 times.
Table 20. Frame Formats The majority of the 8th, 9th and 10th samples is
considered as the bit value. For a valid bit detec-
M bit PCE bit SCI frame tion, all the three samples should have the same
0 0 | SB | 8 bit data | STB | value otherwise the noise flag (NF) is set. For ex-
0 1 | SB | 7-bit data | PB | STB | ample: If the 8th, 9th and 10th samples are 0, 1
and 1 respectively, then the bit value is “1”, but the
1 0 | SB | 9-bit data | STB |
Noise Flag bit is set because the three samples
1 1 | SB | 8-bit data PB | STB | values are not the same.
Legend: SB = Start Bit, STB = Stop Bit,
Consequently, the bit length must be long enough
PB = Parity Bit
so that the 8th, 9th and 10th samples have the de-
Note: In case of wake up by an address mark, the sired bit value. This means the clock frequency
MSB bit of the data is taken into account and not should not vary more than 6/16 (37.5%) within one
the parity bit bit. The sampling clock is resynchronized at each
Even parity: the parity bit is calculated to obtain start bit, so that when receiving 10 bits (one start
an even number of “1s” inside the frame made of bit, 1 data byte, 1 stop bit), the clock deviation
the 7 or 8 LSB bits (depending on whether M is must not exceed 3.75%.
equal to 0 or 1) and the parity bit. Note: The internal sampling clock of the microcon-
Example: data = 00110101; 4 bits set => parity bit troller samples the pin value on every falling edge.
is 0 if even parity is selected (PS bit = 0). Therefore, the internal sampling clock and the time
the application expects the sampling to take place
Odd parity: the parity bit is calculated to obtain an may be out of sync. For example: If the baud rate
odd number of “1s” inside the frame made of the 7 is 15.625 Kbaud (bit length is 64µs), then the 8th,
or 8 LSB bits (depending on whether M is equal to 9th and 10th samples are at 28µs, 32µs and 36µs
0 or 1) and the parity bit. respectively (the first sample starting ideally at
Example: data = 00110101; 4 bits set => parity bit 0µs). But if the falling edge of the internal clock oc-
is 1 if odd parity is selected (PS bit = 1). curs just before the pin value changes, the sam-
Transmission mode: If the PCE bit is set then the ples would then be out of sync by ~4us. This
MSB bit of the data written in the data register is means the entire bit length must be at least 40µs
not transmitted but is changed by the parity bit. (36µs for the 10th sample + 4µs for synchroniza-
tion with the internal sampling clock).
Reception mode: If the PCE bit is set then the in-
terface checks if the received data byte has an
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10.5.4.9 Clock Deviation Causes 10.5.4.10 Noise Error Causes
The causes which contribute to the total deviation See also description of Noise error in Section
are: 0.1.4.3 .
– DTRA: Deviation due to transmitter error (Local Start bit
oscillator error of the transmitter or the trans- The noise flag (NF) is set during start bit reception
mitter is transmitting at a different baud rate). if one of the following conditions occurs:
– DQUANT: Error due to the baud rate quantiza- 1. A valid falling edge is not detected. A falling
tion of the receiver. edge is considered to be valid if the 3 consecu-
– DREC: Deviation of the local oscillator of the tive samples before the falling edge occurs are
receiver: This deviation can occur during the detected as '1' and, after the falling edge
reception of one complete SCI message as- occurs, during the sampling of the 16 samples,
suming that the deviation has been compen- if one of the samples numbered 3, 5 or 7 is
sated at the beginning of the message. detected as a “1”.
– DTCL: Deviation due to the transmission line 2. During sampling of the 16 samples, if one of the
(generally due to the transceivers) samples numbered 8, 9 or 10 is detected as a
All the deviations of the system should be added “1”.
and compared to the SCI clock tolerance: Therefore, a valid Start Bit must satisfy both the
DTRA + DQUANT + DREC + DTCL < 3.75% above conditions to prevent the Noise Flag getting
set.
Data Bits
The noise flag (NF) is set during normal data bit re-
ception if the following condition occurs:
– During the sampling of 16 samples, if all three
samples numbered 8, 9 and10 are not the same.
The majority of the 8th, 9th and 10th samples is
considered as the bit value.
Therefore, a valid Data Bit must have samples 8, 9
and 10 at the same value to prevent the Noise
Flag getting set.
Figure 56. Bit Sampling in Reception Mode
RDI LINE
sampled values
Sample
clock 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
6/16
7/16 7/16
One bit time
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10.5.5 Low Power Modes 10.5.6 Interrupts
Mode Description The SCI interrupt events are connected to the
No effect on SCI. same interrupt vector.
WAIT SCI interrupts cause the device to exit from These events generate an interrupt if the corre-
Wait mode. sponding Enable Control Bit is set and the inter-
SCI registers are frozen.
rupt mask in the CC register is reset (RIM instruc-
tion).
HALT In Halt mode, the SCI stops transmitting/re-
ceiving until Halt mode is exited. Enable Exit Exit
Event
Flag
Bit Wait Halt
Transmit Data Register
TDRE TIE Yes No
Empty
Transmission Com-
TC TCIE Yes No
plete
Received Data Ready
RDRF Yes No
to be Read
RIE
Overrun Error Detect-
OR Yes No
ed
Idle Line Detected IDLE ILIE Yes No
Parity Error PE PIE Yes No
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10.5.7 Register Description Note: The IDLE bit is not set again until the RDRF
STATUS REGISTER (SCISR) bit has been set itself (that is, a new idle line oc-
Read Only curs).
Reset Value: 1100 0000 (C0h)
7 0 Bit 3 = OR Overrun error.
This bit is set by hardware when the word currently
being received in the shift register is ready to be
TDRE TC RDRF IDLE OR NF FE PE
transferred into the RDR register while RDRF = 1.
An interrupt is generated if RIE = 1 in the SCICR2
Bit 7 = TDRE Transmit data register empty. register. It is cleared by a software sequence (an
This bit is set by hardware when the content of the access to the SCISR register followed by a read to
TDR register has been transferred into the shift the SCIDR register).
register. An interrupt is generated if the TIE bit = 1 0: No Overrun error
in the SCICR2 register. It is cleared by a software 1: Overrun error is detected
sequence (an access to the SCISR register fol- Note: When this bit is set RDR register content is
lowed by a write to the SCIDR register). not lost but the shift register is overwritten.
0: Data is not transferred to the shift register
1: Data is transferred to the shift register
Note: Data is not transferred to the shift register Bit 2 = NF Noise flag.
unless the TDRE bit is cleared. This bit is set by hardware when noise is detected
on a received frame. It is cleared by a software se-
quence (an access to the SCISR register followed
Bit 6 = TC Transmission complete. by a read to the SCIDR register).
This bit is set by hardware when transmission of a 0: No noise is detected
frame containing Data is complete. An interrupt is 1: Noise is detected
generated if TCIE = 1 in the SCICR2 register. It is Note: This bit does not generate interrupt as it ap-
cleared by a software sequence (an access to the pears at the same time as the RDRF bit which it-
SCISR register followed by a write to the SCIDR self generates an interrupt.
register).
0: Transmission is not complete
1: Transmission is complete Bit 1 = FE Framing error.
Note: TC is not set after the transmission of a Pre- This bit is set by hardware when a de-synchroniza-
amble or a Break. tion, excessive noise or a break character is de-
tected. It is cleared by a software sequence (an
access to the SCISR register followed by a read to
Bit 5 = RDRF Received data ready flag. the SCIDR register).
This bit is set by hardware when the content of the 0: No Framing error is detected
RDR register has been transferred to the SCIDR 1: Framing error or break character is detected
register. An interrupt is generated if RIE = 1 in the
SCICR2 register. It is cleared by a software se- Note: This bit does not generate interrupt as it ap-
quence (an access to the SCISR register followed pears at the same time as the RDRF bit which it-
by a read to the SCIDR register). self generates an interrupt. If the word currently
0: Data is not received being transferred causes both frame error and
1: Received data is ready to be read overrun error, it will be transferred and only the OR
bit will be set.
Bit 4 = IDLE Idle line detect.
This bit is set by hardware when a Idle Line is de- Bit 0 = PE Parity error.
tected. An interrupt is generated if the ILIE = 1 in This bit is set by hardware when a parity error oc-
the SCICR2 register. It is cleared by a software se- curs in receiver mode. It is cleared by a software
quence (an access to the SCISR register followed sequence (a read to the status register followed by
by a read to the SCIDR register). an access to the SCIDR data register). An inter-
0: No Idle Line is detected rupt is generated if PIE = 1 in the SCICR1 register.
1: Idle Line is detected 0: No parity error
1: Parity error
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CONTROL REGISTER 1 (SCICR1)
Read/Write Bit 3 = WAKE Wake-Up method.
Reset Value: x000 0000 (x0h) This bit determines the SCI Wake-Up method, it is
set or cleared by software.
7 0 0: Idle Line
1: Address Mark
R8 T8 SCID M WAKE PCE PS PIE
Bit 2 = PCE Parity control enable.

Bit 7 = R8 Receive data bit 8. This bit selects the hardware parity control (gener-
This bit is used to store the 9th bit of the received ation and detection). When the parity control is en-
word when M = 1. abled, the computed parity is inserted at the MSB
position (9th bit if M = 1; 8th bit if M = 0) and parity
is checked on the received data. This bit is set and
Bit 6 = T8 Transmit data bit 8. cleared by software. Once it is set, PCE is active
This bit is used to store the 9th bit of the transmit- after the current byte (in reception and in transmis-
ted word when M = 1. sion).
0: Parity control disabled
1: Parity control enabled
Bit 5 = SCID Disabled for low power consumption
When this bit is set the SCI prescalers and outputs
are stopped and the end of the current byte trans- Bit 1 = PS Parity selection.
fer in order to reduce power consumption.This bit This bit selects the odd or even parity when the
is set and cleared by software. parity generation/detection is enabled (PCE bit
0: SCI enabled set). It is set and cleared by software. The parity is
1: SCI prescaler and outputs disabled selected after the current byte.
0: Even parity
1: Odd parity
Bit 4 = M Word length.
This bit determines the word length. It is set or
cleared by software. Bit 0 = PIE Parity interrupt enable.
0: 1 Start bit, 8 Data bits, 1 Stop bit This bit enables the interrupt capability of the hard-
1: 1 Start bit, 9 Data bits, 1 Stop bit ware parity control when a parity error is detected
(PE bit set). It is set and cleared by software.
0: Parity error interrupt disabled
Note: The M bit must not be modified during a data
1: Parity error interrupt enabled.
transfer (both transmission and reception).
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CONTROL REGISTER 2 (SCICR2) Notes:
Read/Write – During transmission, a “0” pulse on the TE bit
Reset Value: 0000 0000 (00h) (“0” followed by “1”) sends a preamble (idle line)
after the current word.
7 0 – When TE is set there is a 1 bit-time delay before
the transmission starts.
TIE TCIE RIE ILIE TE RE RWU SBK
CAUTION: The TDO pin is free for general pur-
pose I/O only when the TE and RE bits are both
Bit 7 = TIE Transmitter interrupt enable. cleared (or if TE is never set).
1: An SCI interrupt is generated whenever Bit 2 = RE Receiver enable.
TDRE=1 in the SCISR register This bit enables the receiver. It is set and cleared
by software.
0: Receiver is disabled
Bit 6 = TCIE Transmission complete interrupt ena- 1: Receiver is enabled and begins searching for a
ble start bit
1: An SCI interrupt is generated whenever TC=1 in Bit 1 = RWU Receiver wake-up.
the SCISR register This bit determines if the SCI is in mute mode or
not. It is set and cleared by software and can be
cleared by hardware when a wake-up sequence is
Bit 5 = RIE Receiver interrupt enable. recognized.
This bit is set and cleared by software. 0: Receiver in Active mode
0: Interrupt is inhibited 1: Receiver in Mute mode
1: An SCI interrupt is generated whenever OR=1
or RDRF=1 in the SCISR register Note: Before selecting Mute mode (setting the
RWU bit), the SCI must receive some data first,
otherwise it cannot function in Mute mode with
Bit 4 = ILIE Idle line interrupt enable. wake-up by idle line detection.
0: Interrupt is inhibited Bit 0 = SBK Send break.
1: An SCI interrupt is generated whenever IDLE=1 This bit set is used to send break characters. It is
in the SCISR register. set and cleared by software.
0: No break character is transmitted
Bit 3 = TE Transmitter enable. 1: Break characters are transmitted
This bit enables the transmitter. It is set and Note: If the SBK bit is set to “1” and then to “0”, the
cleared by software. transmitter sends a BREAK word at the end of the
0: Transmitter is disabled current word.
1: Transmitter is enabled
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DATA REGISTER (SCIDR) Bits 5:3 = SCT[2:0] SCI Transmitter rate divisor
Read/Write These 3 bits, in conjunction with the SCP1 & SCP0
bits define the total division applied to the bus
Reset Value: Undefined clock to yield the transmit rate clock in convention-
Contains the Received or Transmitted data char- al Baud Rate Generator mode.
acter, depending on whether it is read from or writ-
TR dividing factor SCT2 SCT1 SCT0
ten to.
1 0 0 0
7 0
2 0 0 1
4 0 1 0
DR7 DR6 DR5 DR4 DR3 DR2 DR1 DR0
8 0 1 1
The Data register performs a double function (read 16 1 0 0
and write) since it is composed of two registers, 32 1 0 1
one for transmission (TDR) and one for reception 64 1 1 0
(RDR).
128 1 1 1
The TDR register provides the parallel interface
between the internal bus and the output shift reg-
ister (see Figure 1.). Bits 2:0 = SCR[2:0] SCI Receiver rate divisor.
The RDR register provides the parallel interface These 3 bits, in conjunction with the SCP[1:0] bits
between the input shift register and the internal define the total division applied to the bus clock to
bus (see Figure 1.). yield the receive rate clock in conventional Baud
Rate Generator mode.
BAUD RATE REGISTER (SCIBRR) RR Dividing factor SCR2 SCR1 SCR0
Read/Write 1 0 0 0
Reset Value: 0000 0000 (00h) 2 0 0 1
4 0 1 0
7 0
8 0 1 1
SCP1 SCP0 SCT2 SCT1 SCT0 SCR2 SCR1 SCR0 16 1 0 0
32 1 0 1
Bits 7:6 = SCP[1:0] First SCI Prescaler 64 1 1 0
These 2 prescaling bits allow several standard 128 1 1 1
clock division ranges:
PR Prescaling factor SCP1 SCP0
1 0 0
3 0 1
4 1 0
13 1 1
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EXTENDED RECEIVE PRESCALER DIVISION EXTENDED TRANSMIT PRESCALER DIVISION
REGISTER (SCIERPR) REGISTER (SCIETPR)
Read/Write Read/Write
Reset Value: 0000 0000 (00h) Reset Value:0000 0000 (00h)
Allows setting of the Extended Prescaler rate divi- Allows setting of the External Prescaler rate divi-
sion factor for the receive circuit. sion factor for the transmit circuit.
7 0 7 0
ERPR ERPR ERPR ERPR ERPR ERPR ERPR ERPR ETPR ETPR ETPR ETPR ETPR ETPR ETPR ETPR
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
Bits 7:0 = ERPR[7:0] 8-bit Extended Receive Bits 7:0 = ETPR[7:0] 8-bit Extended Transmit
Prescaler Register. Prescaler Register.
The extended Baud Rate Generator is activated The extended Baud Rate Generator is activated
when a value different from 00h is stored in this when a value different from 00h is stored in this
register. Therefore the clock frequency issued register. Therefore the clock frequency issued
from the 16 divider (see Figure 3.) is divided by the from the 16 divider (see Figure 3.) is divided by the
binary factor set in the SCIERPR register (in the binary factor set in the SCIETPR register (in the
range 1 to 255). range 1 to 255).
The extended baud rate generator is not used af- The extended baud rate generator is not used af-
ter a reset. ter a reset.
Table 21. Baudrate Selection
Conditions
Baud
Symbol Parameter Accuracy vs Standard Unit
fCPU Prescaler Rate
Standard
Conventional Mode
TR (or RR)=128, PR=13 300 ~300.48
TR (or RR)= 32, PR=13 1200 ~1201.92
TR (or RR)= 16, PR=13 2400 ~2403.84
~0.16% TR (or RR)= 8, PR=13 4800 ~4807.69
fTx TR (or RR)= 4, PR=13 9600 ~9615.38
Communication frequency 8 MHz TR (or RR)= 16, PR= 3 10400 ~10416.67 Hz
fRx
TR (or RR)= 2, PR=13 19200 ~19230.77
TR (or RR)= 1, PR=13 38400 ~38461.54
Extended Mode
~0.79% ETPR (or ERPR) = 35, 14400 ~14285.71
TR (or RR)= 1, PR=1
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SERIAL COMMUNICATION INTERFACE (Cont’d)

Table 22. SCI Register Map and Reset Values
Address Register
7 6 5 4 3 2 1 0
(Hex.) Label
SCISR TDRE TC RDRF IDLE OR NF FE PE
0050h
Reset Value 1 1 0 0 0 0 0 0
SCIDR MSB LSB
0051h
Reset Value x x x x x x x x
SCIBRR SCP1 SCP0 SCT2 SCT1 SCT0 SCR2 SCR1 SCR0
0052h
Reset Value 0 0 0 0 0 0 0 0
SCICR1 R8 T8 SCID M WAKE PCE PS PIE
0053h
Reset Value x 0 0 0 0 0 0 0
SCICR2 TIE TCIE RIE ILIE TE RE RWU SBK
0054h
Reset Value 0 0 0 0 0 0 0 0
SCIERPR MSB LSB
0055h
Reset Value 0 0 0 0 0 0 0 0
SCIPETPR MSB LSB
0057h
Reset Value 0 0 0 0 0 0 0 0
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10.6 10-BIT A/D CONVERTER (ADC)
10.6.1 Introduction 10.6.2 Main Features

The on-chip Analog to Digital Converter (ADC) pe- ■ 10-bit conversion
ripheral is a 10-bit, successive approximation con- ■ Up to 16 channels with multiplexed input
verter with internal sample and hold circuitry. This ■ Linear successive approximation
peripheral has up to 16 multiplexed analog input
■ Data register (DR) which contains the results
channels (refer to device pin out description) that
allow the peripheral to convert the analog voltage ■ Conversion complete status flag
levels from up to 16 different sources. ■ On/off bit (to reduce consumption)
The result of the conversion is stored in a 10-bit The block diagram is shown in Figure 57.
Data Register. The A/D converter is controlled
through a Control/Status Register.
Figure 57. ADC Block Diagram
fCPU DIV 4 0
fADC
DIV 2 1
EOC SPEED ADON 0 CH3 CH2 CH1 CH0 ADCCSR
AIN0
AIN1
ANALOG TO DIGITAL
ANALOG
MUX CONVERTER
AINx
ADCDRH D9 D8 D7 D6 D5 D4 D3 D2
ADCDRL 0 0 0 0 0 0 D1 D0
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10-BIT A/D CONVERTER (ADC) (Cont’d)

10.6.3 Functional Description
The conversion is monotonic, meaning that the re- To read the 10 bits, perform the following steps:
sult never decreases if the analog input does not 1. Poll the EOC bit
and never increases if the analog input does not.
2. Read the ADCDRL register
If the input voltage (VAIN) is greater than VAREF
(high-level voltage reference) then the conversion 3. Read the ADCDRH register. This clears EOC
result is FFh in the ADCDRH register and 03h in automatically.
the ADCDRL register (without overflow indication). Note: The data is not latched, so both the low and
If the input voltage (VAIN) is lower than VSSA (low- the high data register must be read before the next
level voltage reference) then the conversion result conversion is complete, so it is recommended to
in the ADCDRH and ADCDRL registers is 00 00h. disable interrupts while reading the conversion re-
sult.
The A/D converter is linear and the digital result of
the conversion is stored in the ADCDRH and AD- To read only 8 bits, perform the following steps:
CDRL registers. The accuracy of the conversion is 1. Poll the EOC bit
described in the Electrical Characteristics Section. 2. Read the ADCDRH register. This clears EOC
RAIN is the maximum recommended impedance automatically.
for an analog input signal. If the impedance is too
10.6.3.3 Changing the conversion channel
high, this will result in a loss of accuracy due to
leakage and sampling not being completed in the The application can change channels during con-
alloted time. version. When software modifies the CH[3:0] bits
in the ADCCSR register, the current conversion is
10.6.3.1 A/D Converter Configuration
stopped, the EOC bit is cleared, and the A/D con-
The analog input ports must be configured as inverter starts converting the newly selected chan-
put, no pull-up, no interrupt. Refer to the «I/O nel.
ports» chapter. Using these pins as analog inputs
does not affect the ability of the port to be read as
a logic input. Note: The A/D converter may be disabled by re-
setting the ADON bit. This feature allows reduced
In the ADCCSR register:
power consumption when no conversion is need-
– Select the CS[3:0] bits to assign the analog ed.
channel to convert.
10.6.3.2 Starting the Conversion Mode Description
In the ADCCSR register: WAIT No effect on A/D Converter
– Set the ADON bit to enable the A/D converter A/D Converter disabled.
and to start the conversion. From this time on, After wakeup from Halt mode, the A/D
the ADC performs a continuous conversion of Converter requires a stabilization time
the selected channel. HALT
tSTAB (see Electrical Characteristics)
before accurate conversions can be
When a conversion is complete: performed.
– The EOC bit is set by hardware.
– The result is in the ADCDR registers.
A read to the ADCDRH resets the EOC bit. 10.6.5 Interrupts
None.
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10-BIT A/D CONVERTER (ADC) (Cont’d)

CONTROL/STATUS REGISTER (ADCCSR) Bit 3:0 = CH[3:0] Channel Selection
Read/Write (Except bit 7 read only) These bits are set and cleared by software. They
select the analog input to convert.
Reset Value: 0000 0000 (00h)
Channel Pin* CH3 CH2 CH1 CH0
7 0 AIN0 0 0 0 0
AIN1 0 0 0 1
EOC SPEED ADON 0 CH3 CH2 CH1 CH0 AIN2 0 0 1 0
AIN3 0 0 1 1
Bit 7 = EOC End of Conversion AIN4 0 1 0 0
This bit is set by hardware. It is cleared by hard- AIN5 0 1 0 1
ware when software reads the ADCDRH register AIN6 0 1 1 0
or writes to any bit of the ADCCSR register. AIN7 0 1 1 1
0: Conversion is not complete AIN8 1 0 0 0
1: Conversion complete AIN9 1 0 0 1
AIN10 1 0 1 0
Bit 6 = SPEED ADC clock selection AIN11 1 0 1 1
This bit is set and cleared by software. AIN12 1 1 0 0
0: fADC = fCPU/4 AIN13 1 1 0 1
1: fADC = fCPU/2 AIN14 1 1 1 0
AIN15 1 1 1 1
Bit 5 = ADON A/D Converter on *The number of channels is device dependent. Refer to
This bit is set and cleared by software. the device pinout description.
0: Disable ADC and stop conversion
1: Enable ADC and start conversion
DATA REGISTER (ADCDRH)
Bit 4 = Reserved. Must be kept cleared. Read Only
Reset Value: 0000 0000 (00h)
7 0
D9 D8 D7 D6 D5 D4 D3 D2
Bit 7:0 = D[9:2] MSB of Converted Analog Value
DATA REGISTER (ADCDRL)

Read Only
Reset Value: 0000 0000 (00h)
7 0
0 0 0 0 0 0 D1 D0
Bit 7:2 = Reserved. Forced by hardware to 0.
Bit 1:0 = D[1:0] LSB of Converted Analog Value
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10-BIT A/D CONVERTER (Cont’d)

Table 23. ADC Register Map and Reset Values
Address Register
7 6 5 4 3 2 1 0
(Hex.) Label
ADCCSR EOC SPEED ADON CH3 CH2 CH1 CH0

0070h
Reset Value 0 0 0 0 0 0 0 0
ADCDRH D9 D8 D7 D6 D5 D4 D3 D2
0071h
Reset Value 0 0 0 0 0 0 0 0
ADCDRL D1 D0
0072h
Reset Value 0 0 0 0 0 0 0 0
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11 INSTRUCTION SET
11.1 CPU ADDRESSING MODES so, most of the addressing modes may be subdi-
vided in two sub-modes called long and short:
The CPU features 17 different addressing modes
which can be classified in 7 main groups: – Long addressing mode is more powerful be-
cause it can use the full 64 Kbyte address space,
Addressing Mode Example however it uses more bytes and more CPU cy-
Inherent nop cles.
Immediate ld A,#$55 – Short addressing mode is less powerful because
it can generally only access page zero (0000h -
Direct ld A,$55
00FFh range), but the instruction size is more
Indexed ld A,($55,X) compact, and faster. All memory to memory in-
Indirect ld A,([$55],X) structions use short addressing modes only
Relative jrne loop (CLR, CPL, NEG, BSET, BRES, BTJT, BTJF,
INC, DEC, RLC, RRC, SLL, SRL, SRA, SWAP)
Bit operation bset byte,#5
The ST7 Assembler optimizes the use of long and
short addressing modes.
The CPU Instruction set is designed to minimize
the number of bytes required per instruction: To do
Table 24. CPU Addressing Mode Overview
Pointer Pointer Size Length
Mode Syntax Destination Address (Hex.) (Bytes)
(Hex.)
Inherent nop +0
Immediate ld A,#$55 +1
Short Direct ld A,$10 00..FF +1
Long Direct ld A,$1000 0000..FFFF +2
No Offset Direct Indexed ld A,(X) 00..FF +0
Short Direct Indexed ld A,($10,X) 00..1FE +1
Long Direct Indexed ld A,($1000,X) 0000..FFFF +2
Short Indirect ld A,[$10] 00..FF 00..FF byte +2
Long Indirect ld A,[$10.w] 0000..FFFF 00..FF word +2
Short Indirect Indexed ld A,([$10],X) 00..1FE 00..FF byte +2
Long Indirect Indexed ld A,([$10.w],X) 0000..FFFF 00..FF word +2
Relative Direct jrne loop PC+/-127 +1
Relative Indirect jrne [$10] PC+/-127 00..FF byte +2
Bit Direct bset $10,#7 00..FF +1
Bit Indirect bset [$10],#7 00..FF 00..FF byte +2
Bit Direct Relative btjt $10,#7,skip 00..FF +2
Bit Indirect Relative btjt [$10],#7,skip 00..FF 00..FF byte +3
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INSTRUCTION SET OVERVIEW (Cont’d)

11.1.1 Inherent 11.1.3 Direct
All Inherent instructions consist of a single byte. In Direct instructions, the operands are referenced
The opcode fully specifies all the required informa- by their memory address.
tion for the CPU to process the operation. The direct addressing mode consists of two sub-
Inherent Instruction Function modes:
NOP No operation Direct (short)
TRAP S/W Interrupt The address is a byte, thus requires only one byte
Wait For Interrupt (Low Pow-
after the opcode, but only allows 00 - FF address-
WFI
er Mode)
ing space.
Halt Oscillator (Lowest Power Direct (long)
HALT
Mode) The address is a word, thus allowing 64 Kbyte ad-
RET Sub-routine Return dressing space, but requires 2 bytes after the op-
code.
IRET Interrupt Sub-routine Return
SIM Set Interrupt Mask (level 3)
RIM Reset Interrupt Mask (level 0)
11.1.4 Indexed (No Offset, Short, Long)
SCF Set Carry Flag In this mode, the operand is referenced by its
memory address, which is defined by the unsigned
RCF Reset Carry Flag addition of an index register (X or Y) with an offset.
RSP Reset Stack Pointer
The indirect addressing mode consists of three
LD Load sub-modes:
CLR Clear Indexed (No Offset)
PUSH/POP Push/Pop to/from the stack There is no offset, (no extra byte after the opcode),
INC/DEC Increment/Decrement and allows 00 - FF addressing space.
TNZ Test Negative or Zero Indexed (Short)
CPL, NEG 1 or 2 Complement The offset is a byte, thus requires only one byte af-
MUL Byte Multiplication ter the opcode and allows 00 - 1FE addressing
SLL, SRL, SRA, RLC,
space.
Shift and Rotate Operations Indexed (long)
RRC
SWAP Swap Nibbles The offset is a word, thus allowing 64 Kbyte ad-
dressing space and requires 2 bytes after the op-
code.
11.1.2 Immediate
Immediate instructions have two bytes, the first
byte contains the opcode, the second byte con- 11.1.5 Indirect (Short, Long)
tains the operand value. The required data byte to do the operation is found
Immediate Instruction Function
by its memory address, located in memory (point-
er).
LD Load
The pointer address follows the opcode. The indi-
CP Compare rect addressing mode consists of two sub-modes:
BCP Bit Compare Indirect (short)
AND, OR, XOR Logical Operations
The pointer address is a byte, the pointer size is a
ADC, ADD, SUB, SBC Arithmetic Operations byte, thus allowing 00 - FF addressing space, and
requires 1 byte after the opcode.
Indirect (long)
word, thus allowing 64 Kbyte addressing space,
and requires 1 byte after the opcode.
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11.1.6 Indirect Indexed (Short, Long) 11.1.7 Relative mode (Direct, Indirect)
This is a combination of indirect and short indexed This addressing mode is used to modify the PC
addressing modes. The operand is referenced by register value, by adding an 8-bit signed offset to
its memory address, which is defined by the unit.
signed addition of an index register value (X or Y)
with a pointer value located in memory. The point- Available Relative
er address follows the opcode. Direct/Indirect Function
Instructions
The indirect indexed addressing mode consists of
two sub-modes: JRxx Conditional Jump
CALLR Call Relative
Indirect Indexed (Short)
byte, thus allowing 00 - 1FE addressing space,
and requires 1 byte after the opcode. The relative addressing mode consists of two sub-
modes:
Indirect Indexed (Long) Relative (Direct)
The pointer address is a byte, the pointer size is a The offset is following the opcode.
word, thus allowing 64 Kbyte addressing space, Relative (Indirect)
and requires 1 byte after the opcode. The offset is defined in memory, which address
Table 25. Instructions Supporting Direct, follows the opcode.
Indexed, Indirect and Indirect Indexed
Addressing Modes
Long and Short
Function
Instructions
LD Load
CP Compare
AND, OR, XOR Logical Operations
Arithmetic Additions/Sub-
ADC, ADD, SUB, SBC
stractions operations
BCP Bit Compare
Short Instructions
Function
Only
CLR Clear
INC, DEC Increment/Decrement
TNZ Test Negative or Zero
CPL, NEG 1 or 2 Complement
BSET, BRES Bit Operations
Bit Test and Jump Opera-
BTJT, BTJF
tions
SLL, SRL, SRA, RLC, Shift and Rotate Opera-
RRC tions
SWAP Swap Nibbles
CALL, JP Call or Jump subroutine
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11.2 INSTRUCTION GROUPS

The ST7 family devices use an Instruction Set be subdivided into 13 main groups as illustrated in
consisting of 63 instructions. The instructions may the following table:
Load and Transfer LD CLR

Stack operation PUSH POP RSP
Increment/Decrement INC DEC
Compare and Tests CP TNZ BCP
Logical operations AND OR XOR CPL NEG
Bit Operation BSET BRES
Conditional Bit Test and Branch BTJT BTJF
Arithmetic operations ADC ADD SUB SBC MUL
Shift and Rotates SLL SRL SRA RLC RRC SWAP SLA
Unconditional Jump or Call JRA JRT JRF JP CALL CALLR NOP RET
Conditional Branch JRxx
Interruption management TRAP WFI HALT IRET
Condition Code Flag modification SIM RIM SCF RCF
Using a pre-byte
The instructions are described with one to four op- These prebytes enable instruction in Y as well as
codes. indirect addressing modes to be implemented.
In order to extend the number of available op- They precede the opcode of the instruction in X or
codes for an 8-bit CPU (256 opcodes), three differ- the instruction using direct addressing mode. The
ent prebyte opcodes are defined. These prebytes prebytes are:
modify the meaning of the instruction they pre- PDY 90 Replace an X based instruction
cede. using immediate, direct, indexed, or inherent ad-
The whole instruction becomes: dressing mode by a Y one.
PC-2 End of previous instruction PIX 92 Replace an instruction using di-
rect, direct bit, or direct relative addressing mode
PC-1 Prebyte to an instruction using the corresponding indirect
PC opcode addressing mode.
PC+1 Additional word (0 to 2) according It also changes an instruction using X indexed ad-
to the number of bytes required to compute the ef- dressing mode to an instruction using indirect X in-
fective address dexed addressing mode.
PIY 91 Replace an instruction using X in-
direct indexed addressing mode by a Y one.
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Mnemo Description Function/Example Dst Src I1 H I0 N Z C

ADC Add with Carry A=A+M+C A M H N Z C
ADD Addition A=A+M A M H N Z C
AND Logical And A=A.M A M N Z
BCP Bit compare A, Memory tst (A . M) A M N Z
BRES Bit Reset bres Byte, #3 M
BSET Bit Set bset Byte, #3 M
BTJF Jump if bit is false (0) btjf Byte, #3, Jmp1 M C
BTJT Jump if bit is true (1) btjt Byte, #3, Jmp1 M C
CALL Call subroutine
CALLR Call subroutine relative
CLR Clear reg, M 0 1
CP Arithmetic Compare tst(Reg - M) reg M N Z C
CPL One Complement A = FFH-A reg, M N Z 1
DEC Decrement dec Y reg, M N Z
HALT Halt 1 0
IRET Interrupt routine return Pop CC, A, X, PC I1 H I0 N Z C
INC Increment inc X reg, M N Z
JP Absolute Jump jp [TBL.w]
JRA Jump relative always
JRT Jump relative
JRF Never jump jrf *
JRIH Jump if ext. INT pin = 1 (ext. INT pin high)
JRIL Jump if ext. INT pin = 0 (ext. INT pin low)
JRH Jump if H = 1 H = 1?
JRNH Jump if H = 0 H = 0?
JRM Jump if I1:0 = 11 I1:0 = 11?
JRNM Jump if I1:0 <> 11 I1:0 <> 11?
JRMI Jump if N = 1 (minus) N = 1?
JRPL Jump if N = 0 (plus) N = 0?
JREQ Jump if Z = 1 (equal) Z = 1?
JRNE Jump if Z = 0 (not equal) Z = 0?
JRC Jump if C = 1 C = 1?
JRNC Jump if C = 0 C = 0?
JRULT Jump if C = 1 Unsigned <
JRUGE Jump if C = 0 Jmp if unsigned >=
JRUGT Jump if (C + Z = 0) Unsigned >
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Mnemo Description Function/Example Dst Src I1 H I0 N Z C

JRULE Jump if (C + Z = 1) Unsigned <=
LD Load dst <= src reg, M M, reg N Z
MUL Multiply X,A = X * A A, X, Y X, Y, A 0 0
NEG Negate (2's compl) neg $10 reg, M N Z C
NOP No Operation
OR OR operation A=A+M A M N Z
pop reg reg M
POP Pop from the Stack
pop CC CC M I1 H I0 N Z C
PUSH Push onto the Stack push Y M reg, CC
RCF Reset carry flag C=0 0
RET Subroutine Return
RIM Enable Interrupts I1:0 = 10 (level 0) 1 0
RLC Rotate left true C C <= A <= C reg, M N Z C
RRC Rotate right true C C => A => C reg, M N Z C
RSP Reset Stack Pointer S = Max allowed
SBC Substract with Carry A=A-M-C A M N Z C
SCF Set carry flag C=1 1
SIM Disable Interrupts I1:0 = 11 (level 3) 1 1
SLA Shift left Arithmetic C <= A <= 0 reg, M N Z C
SLL Shift left Logic C <= A <= 0 reg, M N Z C
SRL Shift right Logic 0 => A => C reg, M 0 Z C
SRA Shift right Arithmetic A7 => A => C reg, M N Z C
SUB Substraction A=A-M A M N Z C
SWAP SWAP nibbles A7-A4 <=> A3-A0 reg, M N Z
TNZ Test for Neg & Zero tnz lbl1 N Z
TRAP S/W trap S/W interrupt 1 1
WFI Wait for Interrupt 1 0
XOR Exclusive OR A = A XOR M A M N Z
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12 ELECTRICAL CHARACTERISTICS
12.1 PARAMETER CONDITIONS

Unless otherwise specified, all voltages are re-
ferred to VSS. 12.1.5 Pin input voltage
12.1.1 Minimum and Maximum values The input voltage measurement on a pin of the de-
Unless otherwise specified the minimum and max- vice is described in Figure 59.
imum values are guaranteed in the worst condi-
tions of ambient temperature, supply voltage and Figure 59. Pin input voltage
frequencies by tests in production on 100% of the
devices with an ambient temperature at TA=25°C
and TA=TAmax (given by the selected temperature
range). ST7 PIN
Data based on characterization results, design

simulation and/or technology characteristics are VIN
indicated in the table footnotes and are not tested
in production. Based on characterization, the min-
imum and maximum values refer to sample tests
and represent the mean value plus or minus three
times the standard deviation (mean±3Σ).
12.1.2 Typical values
Unless otherwise specified, typical data are based
on TA=25°C, VDD=5V. They are given only as de-
sign guidelines and are not tested.
12.1.3 Typical curves
Unless otherwise specified, all typical curves are
given only as design guidelines and are not tested.
12.1.4 Loading capacitor
The loading conditions used for pin parameter
measurement are shown in Figure 58.
Figure 58. Pin loading conditions
ST7 PIN
CL
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12.2 ABSOLUTE MAXIMUM RATINGS

Stresses above those listed as “absolute maxi- tions is not implied. Exposure to maximum rating
mum ratings” may cause permanent damage to conditions for extended periods may affect device
the device. This is a stress rating only and func- reliability.
tional operation of the device under these condi-
12.2.1 Voltage Characteristics
Symbol Ratings Maximum value Unit
VDD - VSS Supply voltage 6.5
VPP - VSS Programming Voltage 13
V
1) & 2)
Input Voltage on true open drain pin VSS-0.3 to 6.5
VIN
Input voltage on any other pin VSS-0.3 to VDD+0.3
|∆VDDx| and |∆VSSx| Variations between different digital power pins 50
mV
|VSSA - VSSx| Variations between digital and analog ground pins 50
VESD(HBM) Electro-static discharge voltage (Human Body Model)
see Section 12.8.3 on page 132
VESD(MM) Electro-static discharge voltage (Machine Model)
12.2.2 Current Characteristics
Symbol Ratings Maximum value Unit
Total current into VDD power lines 32-pin devices 75
IVDD mA
(source) 3) 44-pin devices 150
Total current out of VSS ground lines 32-pin devices 75
IVSS mA
(sink) 3) 44-pin devices 150
Output current sunk by any standard I/O and control pin 25
IIO Output current sunk by any high sink I/O pin 50
Output current source by any I/Os and control pin - 25
Injected current on VPP pin ±5
Injected current on RESET pin ±5 mA
2) & 4)
IINJ(PIN) Injected current on OSC1 and OSC2 pins ±5
Injected current on Flash device pin PB0 +5
Injected current on any other pin 5) & 6) ±5
ΣIINJ(PIN) 2) Total injected current (sum of all I/O and control pins) 5) ± 25
Notes:
1. Directly connecting the RESET and I/O pins to VDD or VSS could damage the device if an unintentional internal reset
is generated or an unexpected change of the I/O configuration occurs (for example, due to a corrupted program counter).
To guarantee safe operation, this connection has to be done through a pull-up or pull-down resistor (typical: 4.7kΩ for
RESET, 10kΩ for I/Os). For the same reason, unused I/O pins must not be directly tied to VDD or VSS.
2. IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum cannot be
respected, the injection current must be limited externally to the IINJ(PIN) value. A positive injection is induced by VIN>VDD
while a negative injection is induced by VIN<VSS. For true open-drain pads, there is no positive injection current, and the
corresponding VIN maximum must always be respected
3. All power (VDD) and ground (VSS) lines must always be connected to the external supply.
4. Negative injection disturbs the analog performance of the device. See note in “ADC Accuracy” on page 145.
For best reliability, it is recommended to avoid negative injection of more than 1.6mA.
5. When several inputs are submitted to a current injection, the maximum ΣIINJ(PIN) is the absolute sum of the positive
and negative injected currents (instantaneous values). These results are based on characterisation with ΣIINJ(PIN) maxi-
mum current injection on four I/O port pins of the device.
6. True open drain I/O port pins do not accept positive injection.
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12.2.3 Thermal Characteristics

Symbol Ratings Value Unit
TSTG Storage temperature range -65 to +150 °C
TJ Maximum junction temperature (see Section 13.2 THERMAL CHARACTERISTICS)
12.3 OPERATING CONDITIONS

12.3.1 Operating Conditions
Symbol Parameter Conditions Min Max Unit
fCPU Internal clock frequency 0 8 MHz
Operating voltage (except Flash Write/
3.8 5.5
VDD Erase) V
Operating Voltage for Flash Write/Erase VPP = 11.4 to 12.6V 4.5 5.5
1 Suffix Version 0 70
5 Suffix Version -10 85
TA Ambient temperature range 6 Suffix Versions -40 85 °C
7 Suffix Versions -40 105
3 Suffix Version -40 125
Figure 60. fCPU Max Versus VDD
fCPU [MHz]
8 FUNCTIONALITY
FUNCTIONALITY GUARANTEED
NOT GUARANTEED IN THIS AREA
6 (UNLESS
IN THIS AREA
OTHERWISE
4 SPECIFIED
IN THE TABLES
2 OF PARAMETRIC
DATA)
1
0
3.5 3.8 4.0 4.5 5.5
SUPPLY VOLTAGE [V]
Note: Some temperature ranges are only available with a specific package and memory size. Refer to Or-
dering Information.
Warning: Do not connect 12V to VPP before VDD is powered on, as this may damage the device.
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OPERATING CONDITIONS (Cont’d)
12.4 LVD/AVD CHARACTERISTICS

12.4.1 Operating Conditions with Low Voltage Detector (LVD)
Subject to general operating conditions for TA
Symbol Parameter Conditions Min Typ Max Unit
VD level = High in option byte 4.0 1) 4.2 4.5
Reset release threshold
VIT+(LVD) VD level = Med. in option byte2) 3.55 1) 3.75 4.01)
(VDD rise) 2) 1)
VD level = Low in option byte 2.95 3.15 3.351)
V
VD level = High in option byte 3.8 4.0 4.25 1)
Reset generation threshold
VIT-(LVD) VD level = Med. in option byte2) 3.351) 3.55 3.751)
(VDD fall)
VD level = Low in option byte2) 2.81) 3.0 3.15 1)
1)
Vhys(LVD) LVD voltage threshold hysteresis VIT+(LVD)-VIT-(LVD) 150 200 250 mV
VtPOR VDD rise time 1) 6µs/V 100ms/V
tg(VDD) Filtered glitch delay on VDD 1) Not detected by the LVD 40 ns
Notes:
1. Data based on characterization results, not tested in production.
2. If the medium or low thresholds are selected, the detection may occur outside the specified operating voltage range.
12.4.2 Auxiliary Voltage Detector (AVD) Thresholds

Subject to general operating conditions for TA
1)
VD level = High in option byte 4.4 4.6 4.9
1⇒0 AVDF flag toggle threshold
VIT+(AVD)
(VDD rise) VD level = Med. in option byte 3.95 1) 4.15 4.41)
VD level = Low in option byte 3.4 1) 3.6 3.81)
V
VD level = High in option byte 4.2 4.4 4.65 1)
0⇒1 AVDF flag toggle threshold
VIT-(AVD)
(VDD fall) VD level = Med. in option byte 3.751) 4.0 4.2 1)
VD level = Low in option byte 3.21) 3.4 3.6 1)
Vhys(AVD) AVD voltage threshold hysteresis VIT+(AVD)-VIT-(AVD) 200 mV
Voltage drop between AVD flag set
∆VIT- VIT-(AVD)-VIT-(LVD) 450 mV
and LVD reset activated
1. Data based on characterization results not tested in production.
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12.5 SUPPLY CURRENT CHARACTERISTICS

The following current consumption specified for the ST7 functional operating modes over temperature
range does not take into account the clock source current consumption. To get the total device consump-
tion, the two current values must be added (except for HALT mode for which the clock is stopped).
12.5.1 CURRENT CONSUMPTION
Flash Devices
Symbol Parameter Conditions Unit
Typ Max 1)
fOSC=2MHz, fCPU=1MHz 1.3 3.0
Supply current in RUN mode 2) mA
fOSC=2MHz, fCPU=62.5kHz 600 2700
fOSC=4MHz, fCPU=125kHz 700 3000
Supply current in SLOW mode 2) µA
IDD 2) fOSC=4MHz, fCPU=2MHz 1.5 4.0
Supply current in WAIT mode mA
fOSC=2MHz, fCPU=62.5kHz 580 1200
Supply current in SLOW WAIT mode 2) µA
-40°C≤TA≤+85°C <1 10
Supply current in HALT mode 3)
-40°C≤TA≤+125°C <1 50
fOSC=2MHz 80 µA
No max.
fOSC=4MHz 160
IDD Supply current in ACTIVE-HALT mode 4) guaran-
fOSC=8MHz 325
teed
fOSC =16MHz 650
Notes:
1. Data based on characterization results, tested in production at VDD max. and fCPU max.
2. Measurements are done in the following conditions:
- Program executed from RAM, CPU running with RAM access. The increase in consumption when executing from Flash
is 50%.
- All I/O pins in input mode with a static value at VDD or VSS (no load)
- All peripherals in reset state.
- LVD disabled.
- Clock input (OSC1) driven by external square wave.
- In SLOW and SLOW WAIT mode, fCPU is based on fOSC divided by 32.
To obtain the total current consumption of the device, add the clock source (Section 12.6.3) and the peripheral power
consumption (Section 12.5.3).
3. All I/O pins in push-pull 0 mode (when applicable) with a static value at VDD or VSS (no load), LVD disabled. Data based
on characterization results, tested in production at VDD max. and fCPU max.
4. Data based on characterisation results, not tested in production. All I/O pins in push-pull 0 mode (when applicable) with
a static value at VDD or VSS (no load); clock input (OSC1) driven by external square wave, LVD disabled. To obtain
the total current consumption of the device, add the clock source consumption (Section 12.6.3).
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SUPPLY CURRENT CHARACTERISTICS (Cont’d)

12.5.1.1 Power Consumption vs fCPU: Flash Devices
Figure 61. Typical IDD in RUN mode Figure 63. Typical IDD in WAIT mode
9 8MHz 6 8MHz
4MHz 4MHz
8
2MHz 2MHz
5
7 1MHz 1MHz
6 4
Idd (mA)
Idd (mA)
5
3
4
3 2
2
1
1
0 0
4 4.4 4.8 5.2 5.5 4 4.4 4.8 5.2 5.5
Vdd (V) Vdd (V)
Figure 62. Typical IDD in SLOW mode Figure 64. Typ. IDD in SLOW-WAIT mode
500kHz 1.20
1.20
250kHz 500kHz
125kHz 1.00 250kHz
1.00
62.5kHz 125kHz
0.80 62.5kHz
0.80
Idd (mA)
Idd (mA)
0.60
0.60
0.40
0.40
0.20
0.20
0.00
0.00
4 4.4 4.8 5.2 5.5
4 4.4 4.8 5.2 5.5
Vdd (V)
Vdd (V)
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12.5.2 Supply and Clock Managers
The previous current consumption specified for the ST7 functional operating modes over temperature
range does not take into account the clock source current consumption. To get the total device consump-
tion, the two current values must be added (except for HALT mode).
Symbol Parameter Conditions Typ Max Unit
IDD(RCINT) Supply current of internal RC oscillator 625
see Section µA
IDD(RES) Supply current of resonator oscillator 1) & 2) 12.6.3 on page
125
µA
IDD(PLL) PLL supply current VDD= 5V 360
IDD(LVD) LVD supply current VDD= 5V 150 300
Notes:
1. Data based on characterization results done with the external components specified in Section 12.6.3, not tested in
production.
2. As the oscillator is based on a current source, the consumption does not depend on the voltage.
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12.5.3 On-Chip Peripherals
TA = 25°C fCPU=4MHz.
Symbol Parameter Conditions Typ Unit
IDD(TIM) 16-bit Timer supply current 1) VDD=5.0V 50
IDD(SPI) SPI supply current 2) VDD=5.0V 400
3) µA
IDD(SCI) SCI supply current VDD=5.0V 400
IDD(ADC) ADC supply current when converting 4) VDD=5.0V 400
Notes:
1. Data based on a differential IDD measurement between reset configuration (timer counter running at fCPU/4) and timer
counter stopped (only TIMD bit set). Data valid for one timer.
2. Data based on a differential IDD measurement between reset configuration (SPI disabled) and a permanent SPI master
communication at maximum speed (data sent equal to 55h). This measurement includes the pad toggling consump-
tion.
3. Data based on a differential IDD measurement between SCI low power state (SCID=1) and a permanent SCI data trans-
mit sequence.
4. Data based on a differential IDD measurement between reset configuration and continuous A/D conversions.
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12.6 CLOCK AND TIMING CHARACTERISTICS

Subject to general operating conditions for VDD, fCPU, and TA.
12.6.1 General Timings
Symbol Parameter Conditions Min Typ 1) Max Unit
2 3 12 tCPU
tc(INST) Instruction cycle time
fCPU=8MHz 250 375 1500 ns
2) 10 22 tCPU
Interrupt reaction time
tv(IT)
tv(IT) = ∆tc(INST) + 10 fCPU=8MHz 1.25 2.75 µs
12.6.2 External Clock Source

VOSC1H OSC1 input pin high level voltage VDD-1 VDD
V
VOSC1L OSC1 input pin low level voltage VSS VSS+1
tw(OSC1H)
OSC1 high or low time 3) see Figure 65 5
tw(OSC1L)
ns
tr(OSC1)
OSC1 rise or fall time 3) 15
tf(OSC1)
IL OSC1 Input leakage current VSS≤VIN≤VDD ±1 µA
Figure 65. Typical Application with an External Clock Source
90%
VOSC1H
10%
VOSC1L
tr(OSC1) tf(OSC1) tw(OSC1H) tw(OSC1L)
OSC2
Not connected internally
fOSC
EXTERNAL
IL
CLOCK SOURCE
OSC1
ST72XXX
Notes:
1. Data based on typical application software.
2. Time measured between interrupt event and interrupt vector fetch. ∆tc(INST) is the number of tCPU cycles needed to finish
the current instruction execution.
3. Data based on design simulation and/or technology characteristics, not tested in production.
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CLOCK AND TIMING CHARACTERISTICS (Cont’d)

12.6.3 Crystal and Ceramic Resonator Oscillators
The ST7 internal clock can be supplied with four close as possible to the oscillator pins in order to
different Crystal/Ceramic resonator oscillators. All minimize output distortion and start-up stabiliza-
the information given in this paragraph are based tion time. Refer to the crystal/ceramic resonator
on characterization results with specified typical manufacturer for more details (frequency, pack-
external components. In the application, the reso- age, accuracy...).
nator and the load capacitors have to be placed as
LP: Low power oscillator 1 2
MP: Medium power oscillator >2 4
fOSC Oscillator Frequency 1) MHz
MS: Medium speed oscillator >4 8
HS: High speed oscillator >8 16
RF Feedback resistor2) 20 40 kΩ
RS=200Ω LP oscillator 22 56
CL1 Recommended load capacitance ver-
RS=200Ω MP oscillator 22 46
sus equivalent serial resistance of the pF
CL2 RS=200Ω MS oscillator 18 33
crystal or ceramic resonator (RS)
RS=100Ω HS oscillator 15 33
Symbol Parameter Conditions Typ Max Unit

VIN=VSS LP oscillator 80 150
MP oscillator 160 250
i2 OSC2 driving current µA
MS oscillator 310 460
HS oscillator 610 910
Figure 66. Typical Application with a Crystal or Ceramic Resonator
WHEN RESONATOR WITH

INTEGRATED CAPACITORS i2
fOSC
CL1 OSC1
RESONATOR RF
CL2
OSC2
ST72XXX
Notes:
1. The oscillator selection can be optimized in terms of supply current using an high quality resonator with small RS value.
Refer to crystal/ceramic resonator manufacturer for more details.
2. Data based on characterisation results, not tested in production.
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CLOCK AND TIMING CHARACTERISTICS (Cont’d)
Typical Ceramic Resonators (information for guidance only) CL1 CL2 tSU(osc)
Oscil.
Reference3) Freq. Characteristic 1) [pF] [pF] [ms] 2)
LP CSA2.00MG 2MHz ∆fOSC=[±0.5%tolerance,±0.3%∆Ta,±0.3%aging,±x.x%correl] 22 22 4
MURATA
Ceramic
MP CSA4.00MG 4MHz ∆fOSC=[±0.5%tolerance,±0.3%∆Ta,±0.3%aging,±x.x%correl] 22 22 2

MS CSA8.00MTZ 8MHz ∆fOSC=[±0.5%tolerance,±0.5%∆Ta,±0.3%aging,±x.x%correl] 33 33 1
HS CSA16.00MXZ0404) 16MHz ∆fOSC=[±0.5%tolerance,±0.3%∆Ta,±0.3%aging,±x.x%correl] 33 33 0.7
Notes:
1. Resonator characteristics given by the ceramic resonator manufacturer.
2. tSU(OSC) is the typical oscillator start-up time measured between VDD=2.8V and the fetch of the first instruction (with a
quick VDD ramp-up from 0 to 5V (<50µs).
3. Resonators all have different characteristics. Contact the manufacturer to obtain the appropriate values of external
components and to verify oscillator performance.
4. 3rd overtone resonators require specific validation by the resonator manufacturer.
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CLOCK CHARACTERISTICS (Cont’d)

12.6.4 RC Oscillators
Internal RC oscillator frequency
fOSC (RCINT) TA=25°C, VDD=5V 2 3.5 5.6 MHz
See Figure 67
Figure 67. Typical fOSC(RCINT) vs TA Note: To reduce disturbance to the RC oscillator,

it is recommended to place decoupling capacitors
between VDD and VSS as shown in Figure 86
4
Vdd = 5V
fOSC(RCINT) (MHz)
3.8
Vdd = 5.5V
3.6
3.4
3.2
3
-45 0 25 70 130
TA(°C)
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CLOCK CHARACTERISTICS (Cont’d)
12.6.5 PLL Characteristics

fOSC PLL input frequency range 2 4 MHz
Flash ST72F324,
1.0 2.5
1) fOSC = 4 MHz.
∆ fCPU/ fCPU Instantaneous PLL jitter %
Flash ST72F324,
2.5 4.0
fOSC = 2 MHz.
Note:
1. Data characterized but not tested.
The user must take the PLL jitter into account in the application (for example in serial communication or
sampling of high frequency signals). The PLL jitter is a periodic effect, which is integrated over several
CPU cycles. Therefore the longer the period of the application signal, the less it will be impacted by the
PLL jitter.
Figure 68 shows the PLL jitter integrated on application signals in the range 125kHz to 2MHz. At frequen-
cies of less than 125KHz, the jitter is negligible.
Figure 68. Integrated PLL Jitter vs signal frequency1
+/-Jitter (%)
1.2
FLASH typ
1 ROM max
0.8 ROM typ
0.6
0.4
0.2
0
4 MHz 2 MHz 1 MHz 500 kHz 250 kHz 125 kHz
Application Frequency
Note 1: Measurement conditions: fCPU = 8MHz.
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12.7 MEMORY CHARACTERISTICS

12.7.1 RAM and Hardware Registers
1)
VRM Data retention mode HALT mode (or RESET) 1.6 V
12.7.2 FLASH Memory

DUAL VOLTAGE HDFLASH MEMORY
Symbol Parameter Conditions Min 2) Typ Max 2) Unit
Read mode 0 8
fCPU Operating frequency MHz
Write / Erase mode 1 8
VPP Programming voltage 3) 4.5V ≤ VDD ≤ 5.5V 11.4 12.6 V
IDD Supply current4) Write / Erase 0 mA
Read (VPP=12V) 200 µA
IPP VPP current4)
Write / Erase 30 mA
tVPP Internal VPP stabilization time 10 µs
tRET Data retention TA=55°C 20 years
NRW Write erase cycles TA=25°C 100 cycles
TPROG Programming or erasing tempera-
-40 25 85 °C
TERASE ture range
Notes:
1. Minimum VDD supply voltage without losing data stored in RAM (in HALT mode or under RESET) or in hardware reg-
isters (only in HALT mode). Not tested in production.
3. VPP must be applied only during the programming or erasing operation and not permanently for reliability reasons.
4. Data based on simulation results, not tested in production.
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12.8 EMC CHARACTERISTICS should be noted that good EMC performance is

highly dependent on the user application and the
Susceptibility tests are performed on a sample ba- software in particular.
sis during product characterization.
Therefore it is recommended that the user applies
12.8.1 Functional EMS (Electro Magnetic EMC software optimization and prequalification
Susceptibility) tests in relation with the EMC level requested for
Based on a simple running application on the his application.
product (toggling 2 LEDs through I/O ports), the Software recommendations:
product is stressed by two electro magnetic events
until a failure occurs (indicated by the LEDs). The software flowchart must include the manage-
ment of runaway conditions such as:
■ ESD: Electro-Static Discharge (positive and
negative) is applied on all pins of the device until – Corrupted program counter
a functional disturbance occurs. This test – Unexpected reset
conforms with the IEC 1000-4-2 standard.
– Critical Data corruption (control registers...)
■ FTB: A Burst of Fast Transient voltage (positive
and negative) is applied to VDD and VSS through Prequalification trials:
a 100pF capacitor, until a functional disturbance Most of the common failures (unexpected reset
occurs. This test conforms with the IEC 1000-4- and program counter corruption) can be repro-
4 standard. duced by manually forcing a low state on the RE-
A device reset allows normal operations to be re- SET pin or the Oscillator pins for 1 second.
sumed. The test results are given in the table be- To complete these trials, ESD stress can be ap-
low based on the EMS levels and classes defined plied directly on the device, over the range of
in application note AN1709. specification values. When unexpected behaviour
12.8.1.1 Designing hardened software to avoid is detected, the software can be hardened to pre-
noise problems vent unrecoverable errors occurring (see applica-
tion note AN1015)
EMC characterization and optimization are per-
formed at component level with a typical applica- .
tion environment and simplified MCU software. It
Level/
Symbol Parameter Conditions
Class
8 or 16K Flash device, VDD=5V,
Voltage limits to be applied on any I/O pin to induce a
VFESD TA=+25°C, fOSC=8MHz conforms to IEC 4B
functional disturbance
1000-4-2
Fast transient voltage burst limits to be applied
V =5V, TA=+25°C, fOSC=8MHz
VFFTB through 100pF on VDD and VDD pins to induce a func- DD 4A
conforms to IEC 1000-4-4
tional disturbance
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EMC CHARACTERISTICS (Cont’d)

12.8.2 Electro Magnetic Interference (EMI)
Based on a simple application running on the
product (toggling 2 LEDs through the I/O ports),
the product is monitored in terms of emission. This
emission test is in line with the norm SAE J 1752/
3 which specifies the board and the loading of
each pin.
Monitored Max vs. [fOSC/fCPU]
Symbol Parameter Conditions Device/ Package Unit
Frequency Band 8/4MHz 16/8MHz
0.1MHz to 30MHz 12 18
8/16K Flash/ 30MHz to 130MHz 19 25 dBµV
TQFP44 130MHz to 1GHz 15 22
SAE EMI Level 3 3.5 -
VDD=5V, 0.1MHz to 30MHz 20 21
TA=+25°C 30MHz to 130MHz 26 31 dBµV
SEMI Peak level 32K Flash/TQFP44
conforming to 130MHz to 1GHz 22 28
SAE J 1752/3 SAE EMI Level 3.5 4.0 -
0.1MHz to 30MHz 25 27
30MHz to 130MHz 30 36 dBµV
Flash/TQFP32
130MHz to 1GHz 18 23
SAE EMI Level 3.0 3.5 -
Notes:
2. Refer to Application Note AN1709 for data on other package types.
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EMC CHARACTERISTICS (Cont’d)

12.8.3 Absolute Maximum Ratings (Electrical 12.8.3.1 Electro-Static Discharge (ESD)
Sensitivity) Electro-Static Discharges (a positive then a nega-
Based on three different tests (ESD, LU and DLU) tive pulse separated by 1 second) are applied to
using specific measurement methods, the product the pins of each sample according to each pin
is stressed in order to determine its performance in combination. The sample size depends on the
terms of electrical sensitivity. For more details, re- number of supply pins in the device (3 parts*(n+1)
fer to the application note AN1181. supply pin). Two models can be simulated: Human
Body Model and Machine Model. This test con-
forms to the JESD22-A114A/A115A standard.
Absolute Maximum Ratings
Symbol Ratings Conditions Maximum value 1) Unit
Electro-static discharge voltage
VESD(HBM) TA=+25°C 2000
(Human Body Model)
VESD(MM) TA=+25°C 200 V
(Machine Model)
VESD(CD) TA=+25°C 250
(Charged Device Model)
Notes:
12.8.3.2 Static and Dynamic Latch-Up ■ DLU: Electro-Static Discharges (one positive
■ LU: 3 complementary static tests are required then one negative test) are applied to each pin
on 10 parts to assess the latch-up performance. of 3 samples when the micro is running to
A supply overvoltage (applied to each power assess the latch-up performance in dynamic
supply pin) and a current injection (applied to mode. Power supplies are set to the typical
each input, output and configurable I/O pin) are values, the oscillator is connected as near as
performed on each sample. This test conforms possible to the pins of the micro and the
to the EIA/JESD 78 IC latch-up standard. For component is put in reset mode. This test
more details, refer to the application note conforms to the IEC1000-4-2 and SAEJ1752/3
AN1181. standards. For more details, refer to the
application note AN1181.
Electrical Sensitivities
Symbol Parameter Conditions Class 1)
TA=+25°C A
LU Static latch-up class TA=+85°C A
TA=+125°C A
DLU Dynamic latch-up class VDD=5.5V, fOSC=4MHz, TA=+25°C A
Notes:
1. Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the JEDEC spec-
ifications, that means when a device belongs to Class A it exceeds the JEDEC standard. B Class strictly covers all the
JEDEC criteria (international standard).
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12.9 I/O PORT PIN CHARACTERISTICS

12.9.1 General Characteristics
Subject to general operating conditions for VDD, fOSC, and TA unless otherwise specified.
Input low level voltage (standard voltage
VIL 0.3xVDD V
devices)1)
VIH Input high level voltage 1) 0.7xVDD
V
Vhys Schmitt trigger voltage hysteresis 2) 0.7
Injected Current on Flash device pin PB0 0 +4
IINJ(PIN)3)
Injected Current on other I/O pins ±4
VDD=5V mA
Total injected current (sum of all I/O and
ΣIINJ(PIN)3) ±25
control pins)
Ilkg Input leakage current VSS ≤ VIN ≤ VDD ±1
Static current consumption induced by each µA
IS Floating input mode4) 200
floating input pin
RPU Weak pull-up equivalent resistor 5) VIN=VSS VDD=5V 50 120 250 kΩ
CIO I/O pin capacitance 5 pF
tf(IO)out 1)
Output high to low level fall time CL=50pF 25
1) Between 10% and ns
tr(IO)out Output low to high level rise time 90% 25
tw(IT)in External interrupt pulse time 6) 1 tCPU
Notes:
2. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested.
3. When the current limitation is not possible, the VIN maximum must be respected, otherwise refer to IINJ(PIN) specifica-
tion. A positive injection is induced by VIN>VDD while a negative injection is induced by VIN<VSS. Refer to Section 12.2.2
on page 117 for more details.
4. Configuration not recommended, all unused pins must be kept at a fixed voltage: using the output mode of the I/O for
example and leaving the I/O unconnected on the board or an external pull-up or pull-down resistor (see Figure 69). Data
based on design simulation and/or technology characteristics, not tested in production.
5. The RPU pull-up equivalent resistor is based on a resistive transistor (corresponding IPU current characteristics de-
scribed in Figure 70).
6. To generate an external interrupt, a minimum pulse width has to be applied on an I/O port pin configured as an external
interrupt source.
Figure 69. Unused I/O Pins configured as input Figure 70. Typical IPU vs. VDD with VIN=VSS
90
VDD ST7XXX T a= 1 40°C
80
T a= 9 5°C
70 T a= 2 5°C
10kΩ UNUSED I/O PORT T a = -4 5 ° C
60
Ip u (u A )
50
40
UNUSED I/O PORT
10kΩ 30
20
ST7XXX
10
0
2 2 .5 3 3 .5 4 4 .5 5 5 .5 6
V d d (V )
Note: I/O can be left unconnected if it is configured as output
(0 or 1) by the software. This has the advantage of
greater EMC robustness and lower cost.
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I/O PORT PIN CHARACTERISTICS (Cont’d)

12.9.2 Output Driving Current
Subject to general operating conditions for VDD, fCPU, and TA unless otherwise specified.
Output low level voltage for a standard I/O pin IIO=+5mA 1.2
when 8 pins are sunk at same time
(see Figure 71) IIO=+2mA 0.5
VOL 1) IIO=+20mA, TA≤85°C 1.3
Output low level voltage for a high sink I/O pin
VDD=5V
when 4 pins are sunk at same time TA>85°C 1.5 V
(see Figure 72 and Figure 74) IIO=+8mA 0.6
Output high level voltage for an I/O pin IIO=-5mA, TA≤85°C VDD-1.4
VOH 2) when 4 pins are sourced at same time TA>85°C VDD-1.6
(see Figure 73 and Figure 76) IIO=-2mA VDD-0.7
Figure 71. Typical VOL at VDD=5V (std. ports) Figure 73. Typical VOH at VDD=5V
5 .5
1 .2
5
1
V o l (V ) a t V d d = 5 V
V d d -V o h (V ) a t V d d = 5 V
4 .5
0 .8
4
0 .6
3 .5
Ta = 1 4 0 ° C "
0 .4 V d d = 5 V 1 4 0 ° C m in
Ta = 9 5 ° C
Ta = 2 5 ° C 3 V d d = 5 v 9 5 °C m in
0 .2
Ta = -4 5 °C
V d d = 5 v 2 5 °C m in
2 .5
0 V d d = 5 v -4 5 °C m i n
0 505
0 .0 010
.0 1 15
0 .0 1 5
2
IIO Ii(mA)
o (A ) -10 -8 -6 -4 -2 0
-0 .0 1 -0 .0 0 8 -0 .0 0 6 -0 .0 0 4 -0 .0 0 2 0
IIO (mA)
Ii o (A )
Figure 72. Typ. VOL at VDD=5V (high-sink ports)

1
0 .9
0 .8
0 .7
V o l (V ) a t V d d = 5 V
0 .6
0 .5
0 .4
Ta = 1 4 0 °C
0 .3
Ta = 9 5 °C
0 .2 Ta = 2 5 °C
0 .1 Ta = -4 5 ° C
0
0 10 0.01 20 0.0 2 30 0 .0 3
IIO (mA)
Iio (A )
Notes:
1. The IIO current sunk must always respect the absolute maximum rating specified in Section 12.2.2 and the sum of IIO
(I/O ports and control pins) must not exceed IVSS.
2. The IIO current sourced must always respect the absolute maximum rating specified in Section 12.2.2 and the sum of
IIO (I/O ports and control pins) must not exceed IVDD. True open drain I/O pins do not have VOH.
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I/O PORT PIN CHARACTERISTICS (Cont’d)

Figure 74. Typical VOL vs. VDD (std. ports)
1 0.45
Ta=-45°C
Ta=-45°C
0.9
Ta=25°C 0.4 Ta=25°C
0.8 Ta=95°C Ta=95°C
Ta=140°C 0.35
Ta=140°C
Vol(V) at Iio=5mA
0.7
Vol(V) at Iio=2mA
0.3
0.6
0.5 0.25
0.4 0.2
0.3 0.15
0.2
0.1
0.1
0.05
0
2 2.5 3 3.5 4 4.5 5 5.5 6 0
2 2.5 3 3.5 4 4.5 5 5.5 6
Vdd(V)
Vdd(V)
Figure 75. Typical VOL vs. VDD (high-sink ports)

0.6 1.6
1.4 Ta= 140°C

0.5
Ta=95°C
1.2 Ta=25°C
0.4 Ta=-45°C
Vol(V) at Iio=20mA
1
Vol(V) at Iio=8mA
0.3 0.8
0.6
0.2
Ta= 140°C
0.4
Ta=95°C
0.1 Ta=25°C
0.2
Ta=-45°C
0 0
2 2.5 3 3.5 4 4.5 5 5.5 6 2 2.5 3 3.5 4 4.5 5 5.5 6
Vdd(V) Vdd(V)
Figure 76. Typical VOH vs. VDD

5.5 6
Ta=-45°C
5
5 Ta=25°C
Vdd-Voh(V) at Iio=-2mA
Ta=95°C
4.5
Vdd-Voh(V) at Iio=-5m
4 Ta=140°C
4
3
3.5
Ta=-45°C
2
3 Ta=25°C
Ta=95°C
2.5 1
Ta=140°C
2
0
2 2.5 3 3.5 4 4.5 5 5.5 6 2 2.5 3 3.5 4 4.5 5 5.5 6
Vdd(V) Vdd(V)
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12.10 CONTROL PIN CHARACTERISTICS

12.10.1 Asynchronous RESET Pin
2)
Vhys Schmitt trigger voltage hysteresis 2.5 V
VIL Input low level voltage 1) 0.16xVDD
V
VIH Input high level voltage 1) 0.85xVDD
VOL Output low level voltage 3) VDD=5V IIO=+2mA 0.2 0.5 V
IIO Driving current on RESET pin 2 mA
RON Weak pull-up equivalent resistor VDD=5V 20 30 120 kΩ
tw(RSTL)out Generated reset pulse duration Internal reset sources 20 30 426) µs
4)
th(RSTL)in External reset pulse hold time 2.5 µs
tg(RSTL)in Filtered glitch duration 5) 200 ns
Notes:
2. Hysteresis voltage between Schmitt trigger switching levels.
3. The IIO current sunk must always respect the absolute maximum rating specified in Section 12.2.2 and the sum of IIO
(I/O ports and control pins) must not exceed IVSS.
4. To guarantee the reset of the device, a minimum pulse has to be applied to the RESET pin. All short pulses applied on
the RESET pin with a duration below th(RSTL)in can be ignored.
5. The reset network (the resistor and two capacitors) protects the device against parasitic resets, especially in noisy en-
vironments.
6. Data guaranteed by design, not tested in production.
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CONTROL PIN CHARACTERISTICS (Cont’d)

Figure 77. RESET pin protection when LVD is enabled.1)2)3)4)5)6)7)
VDD ST72XXX
Recommended Optional RON

(note 6) INTERNAL
EXTERNAL RESET
RESET Filter
0.01µF
1MΩ WATCHDOG
PULSE
GENERATOR
LVD RESET
Figure 78. RESET pin protection when LVD is disabled.1)2)3)4)
Recommended VDD ST72XXX
VDD VDD
RON
USER 0.01µF 4.7kΩ INTERNAL
EXTERNAL RESET
RESET Filter
CIRCUIT
0.01µF
PULSE
WATCHDOG
GENERATOR
Required
1. The reset network protects the device against parasitic resets.

2. The output of the external reset circuit must have an open-drain output to drive the ST7 reset pad. Otherwise the device
can be damaged when the ST7 generates an internal reset (LVD or watchdog).
3. Whatever the reset source is (internal or external), the user must ensure that the level on the RESET pin can go below
the VIL max. level specified in Section 12.10.1. Otherwise the reset will not be taken into account internally.
4. Because the reset circuit is designed to allow the internal RESET to be output in the RESET pin, the user must ensure
that the current sunk on the RESET pin (by an external pull-up for example) is less than the absolute maximum value
specified for IINJ(RESET) in Section 12.2.2 on page 117.
5. When the LVD is enabled, it is mandatory not to connect a pull-up resistor. A 10nF pull-down capacitor is recommended
to filter noise on the reset line.
6. In case a capacitive power supply is used, it is recommended to connect a1MΩ pull-down resistor to the RESET pin
to discharge any residual voltage induced by this capacitive power supply (this will add 5µA to the power consumption of
the MCU).
7. Tips when using the LVD:
– 1. Check that all recommendations related to ICCCLK and reset circuit have been applied (see notes above)
– 2. Check that the power supply is properly decoupled (100nF + 10µF close to the MCU). Refer to AN1709. If this
cannot be done, it is recommended to put a 100nF + 1MΩ pull-down on the RESET pin.
– 3. The capacitors connected on the RESET pin and also the power supply are key to avoiding any start-up margin-
ality. In most cases, steps 1 and 2 above are sufficient for a robust solution. Otherwise: replace 10nF pull-down on
the RESET pin with a 5µF to 20µF capacitor.”
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CONTROL PIN CHARACTERISTICS (Cont’d)

12.10.2 ICCSEL/VPP Pin
VIL Input low level voltage 1) VSS 0.2
V
VIH Input high level voltage 1) VDD-0.1 12.6
IL Input leakage current VIN=VSS ±1 µA
Figure 79. Two typical Applications with ICCSEL/VPP Pin 2)
ICCSEL/VPP VPP
PROGRAMMING
TOOL
10kΩ
ST72XXX ST72XXX
Notes:
1. Data based on design simulation and/or technology characteristics, not tested in production.
2. When ICC mode is not required by the application ICCSEL/VPP pin must be tied to VSS.
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12.11 TIMER PERIPHERAL CHARACTERISTICS

Subject to general operating conditions for VDD, fOSC, and TA unless otherwise specified.
Refer to I/O port characteristics for more details on the input/output alternate function characteristics (out-
put compare, input capture, external clock, PWM output...).
Data based on design simulation and/or characterisation results, not tested in production.
12.11.1 16-Bit Timer
tw(ICAP)in Input capture pulse time 1 tCPU
2 tCPU
tres(PWM) PWM resolution time
fCPU=8MHz 250 ns
fEXT Timer external clock frequency 0 fCPU/4 MHz
fPWM PWM repetition rate 0 fCPU/4 MHz
ResPWM PWM resolution 16 bit
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12.12 COMMUNICATION INTERFACE CHARACTERISTICS

12.12.1 SPI - Serial Peripheral Interface
Subject to general operating conditions for VDD, fCPU, and TA unless otherwise specified. Data based on
design simulation and/or characterisation results, not tested in production.
When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave
mode) has its alternate function capability released. In this case, the pin status depends on the I/O port
configuration. Refer to I/O port characteristics for more details on the input/output alternate function char-
acteristics (SS, SCK, MOSI, MISO).
Master fCPU/128 fCPU/4
fSCK fCPU=8MHz 0.0625 2
SPI clock frequency MHz
1/tc(SCK) Slave fCPU/2
0
fCPU=8MHz 4
tr(SCK)
SPI clock rise and fall time see I/O port pin description
tf(SCK)
tsu(SS) SS setup time Slave 120
th(SS) SS hold time Slave 120
tw(SCKH) Master 100
SCK high and low time
tw(SCKL) Slave 90
tsu(MI) Master 100
Data input setup time
tsu(SI) Slave 100
ns
th(MI) Master 100
Data input hold time
th(SI) Slave 100
ta(SO) Data output access time Slave 0 120
tdis(SO) Data output disable time Slave 240
tv(SO) Data output valid time 90
Slave (after enable edge)
th(SO) Data output hold time 0
tv(MO) Data output valid time 0.25
Master (before capture edge) tCPU
th(MO) Data output hold time 0.25
Figure 80. SPI Slave Timing Diagram with CPHA=0 1)
SS INPUT
tsu(SS) tc(SCK) th(SS)
CPHA=0
SCK INPUT
CPOL=0
CPHA=0
CPOL=1
tw(SCKH)
ta(SO) tw(SCKL) tv(SO) th(SO) tr(SCK) tdis(SO)
tf(SCK)
MISO OUTPUT see
see note 2 MSB OUT BIT6 OUT LSB OUT note 2
tsu(SI) th(SI)
MOSI INPUT MSB IN BIT1 IN LSB IN
Notes:
1. Measurement points are done at CMOS levels: 0.3xVDD and 0.7xVDD.
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COMMUNICATION INTERFACE CHARACTERISTICS (Cont’d)
Figure 81. SPI Slave Timing Diagram with CPHA=11)
SS INPUT
tsu(SS) tc(SCK) th(SS)
CPHA=1
SCK INPUT
CPOL=0
CPHA=1
CPOL=1
ta(SO) tw(SCKH) tdis(SO)

tw(SCKL) tv(SO) th(SO)
tr(SCK)
tf(SCK)
MISO OUTPUT see see
note 2 HZ MSB OUT BIT6 OUT LSB OUT note 2
tsu(SI) th(SI)
MOSI INPUT MSB IN BIT1 IN LSB IN
Figure 82. SPI Master Timing Diagram 1)
SS INPUT
tc(SCK)
CPHA=0
CPOL=0
CPHA=0
SCK INPUT
CPOL=1
CPHA=1
CPOL=0
CPHA=1
CPOL=1
tw(SCKH) tr(SCK)
tw(SCKL) tf(SCK)
tsu(MI) th(MI)
MISO INPUT MSB IN BIT6 IN LSB IN
tv(MO) th(MO)
MOSI OUTPUT see note 2 MSB OUT BIT6 OUT LSB OUT see note 2
Notes:
1. Measurement points are done at CMOS levels: 0.3xVDD and 0.7xVDD.
2. When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave mode) has
its alternate function capability released. In this case, the pin status depends of the I/O port configuration.
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12.13 10-BIT ADC CHARACTERISTICS

fADC ADC clock frequency 0.4 2 MHz
VAREF Analog reference voltage 0.7*VDD ≤VAREF ≤VDD 3.8 VDD
1)
V
VAIN Conversion voltage range VSSA VAREF
Positive input leakage current for analog -40°C≤TA≤+85°C ±250 nA
Ilkg
input2) +85°C≤TA≤+125°C ±1 µA
RAIN External input impedance see kΩ
CAIN External capacitor on analog input Figure 83 pF
and
fAIN Variation freq. of analog input signal Figure Hz
842)3)4)
CADC Internal sample and hold capacitor 12 pF
Conversion time (Sample+Hold)
tADC 7.5 µs
fCPU=8MHz, SPEED=0 fADC=2MHz
- No of sample capacitor loading cycles 4
tADC 1/fADC
- No. of Hold conversion cycles 11
Notes:
1. Any added external serial resistor will downgrade the ADC accuracy (especially for resistance greater than 10kΩ). Data
based on characterization results, not tested in production.
2.For Flash devices: injecting negative current on any of the analog input pins significantly reduces the accuracy of any
conversion being performed on any analog input. Analog pins of ST72F324 devices can be protected against negative
injection by adding a Schottky diode (pin to ground). Injecting negative current on digital input pins degrades ADC accu-
racy especially if performed on a pin close to the analog input pins. Any positive injection current within the limits specified
for IINJ(PIN) and ΣIINJ(PIN) in Section 12.9 does not affect the ADC accuracy.
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ADC CHARACTERISTICS (Cont’d)
Figure 83. RAIN max. vs fADC with CAIN=0pF1) Figure 84. Recommended CAIN & RAIN values.2)
45 1000
40 Cain 10 nF
35 2 MHz Cain 22 nF
100
Max. R AIN (Kohm)
Max. R AIN (Kohm)

30 Cain 47 nF
1 MHz
25
10
20
15
10 1
0 0.1
0 10 30 70 0.01 0.1 1 10
CPARASITIC (pF) fAIN(KHz)
Figure 85. Typical A/D Converter Application

VDD
ST72XXX
VT
RAIN 0.6V
AINx 2kΩ(max) 10-Bit A/D
VAIN Conversion
CAIN VT
0.6V IL CADC
±1µA 12pF
Notes:
1. CPARASITIC represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad ca-
pacitance (3pF). A high CPARASITIC value will downgrade conversion accuracy. To remedy this, fADC should be reduced.
2. This graph shows that depending on the input signal variation (fAIN), CAIN can be increased for stabilization time and
decreased to allow the use of a larger serial resistor (RAIN).
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ST72324Jx ST72324Kx
ADC CHARACTERISTICS (Cont’d)
12.13.1 Analog Power Supply and Reference digital ground plane via a single point on the
Pins PCB.
Depending on the MCU pin count, the package – Filter power to the analog power planes. It is rec-
may feature separate VAREF and VSSA analog ommended to connect capacitors, with good high
power supply pins. These pins supply power to the frequency characteristics, between the power
A/D converter cell and function as the high and low and ground lines, placing 0.1µF and optionally, if
reference voltages for the conversion. In some needed 10pF capacitors as close as possible to
packages, VAREF and VSSA pins are not available the ST7 power supply pins and a 1 to 10µF ca-
(refer to Section 2 on page 8). In this case the an- pacitor close to the power source (see Figure
alog supply and reference pads are internally 86).
bonded to the VDD and VSS pins. – The analog and digital power supplies should be
Separation of the digital and analog power pins al- connected in a star network. Do not use a resis-
low board designers to improve A/D performance. tor, as VAREF is used as a reference voltage by
Conversion accuracy can be impacted by voltage the A/D converter and any resistance would
drops and noise in the event of heavily loaded or cause a voltage drop and a loss of accuracy.
badly decoupled power supply lines (see Section – Properly place components and route the signal
12.13.2 General PCB Design Guidelines). traces on the PCB to shield the analog inputs.
12.13.2 General PCB Design Guidelines Analog signals paths should run over the analog
To obtain best results, some general design and ground plane and be as short as possible. Isolate
layout rules should be followed when designing analog signals from digital signals that may
the application PCB to shield the noise-sensitive, switch while the analog inputs are being sampled
analog physical interface from noise-generating by the A/D converter. Do not toggle digital out-
CMOS logic signals. puts on the same I/O port as the A/D input being
converted.
– Use separate digital and analog planes. The an-
alog ground plane should be connected to the
Figure 86. Power Supply Filtering
ST72XXX
1 to 10µF 0.1µF VSS
ST7
DIGITAL NOISE
FILTERING
VDD
VDD
POWER
SUPPLY
0.1µF VAREF
SOURCE
EXTERNAL
NOISE
FILTERING VSSA
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10-BIT ADC CHARACTERISTICS (Cont’d)
12.13.3 ADC Accuracy

Conditions: VDD=5V 1)
Flash Devices
Symbol Parameter Conditions Unit
Typ Max2)
|ET| Total unadjusted error 1) 4 6
|EO| 1) 3 5
Offset error
1) 0.5 4.5
|EG| Gain Error
LSB
Differential linearity error
|ED| 1) CPU in run mode @ fADC 2 MHz. 1.5 4.5
|EL| Integral linearity error 1) CPU in run mode @ fADC 2 MHz. 1.5 4.5
Notes:
1. ADC Accuracy vs. Negative Injection Current: Injecting negative current may reduce the accuracy of the conversion
being performed on another analog input.
Any positive injection current within the limits specified for IINJ(PIN) and ΣIINJ(PIN) in Section 12.9 does not affect the ADC
accuracy.
2. Data based on characterization results, monitored in production to guarantee 99.73% within ± max value from -40°C
to 125°C (± 3σ distribution limits).
Figure 87. ADC Accuracy Characteristics
Digital Result ADCDR EG

(1) Example of an actual transfer curve
1023
(2) The ideal transfer curve
1022 V –V (3) End point correlation line
AREF SSA
1LSB = --------------------------------------------
1021 IDEAL 1024
(2)
ET=Total Unadjusted Error: maximum deviation
ET between the actual and the ideal transfer curves.
7 (3) EO=Offset Error: deviation between the first actual
(1) transition and the first ideal one.
6
EG=Gain Error: deviation between the last ideal
5 transition and the last actual one.
EO EL ED=Differential Linearity Error: maximum deviation
4 between actual steps and the ideal one.
3 EL=Integral Linearity Error: maximum deviation
ED between any actual transition and the end point
2 correlation line.
1 LSBIDEAL
1
Vin (LSBIDEAL)
0
1 2 3 4 5 6 7 1021 1022 1023 1024
VSSA VAREF
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13 PACKAGE CHARACTERISTICS
13.1 PACKAGE MECHANICAL DATA
Figure 88. 44-Pin Thin Quad Flat Package
mm inches
D A Dim.
Min Typ Max Min Typ Max
D1 A2
A 1.60 0.063
A1 A1 0.05 0.15 0.002 0.006
A2 1.35 1.40 1.45 0.053 0.055 0.057
b b 0.30 0.37 0.45 0.012 0.015 0.018

C 0.09 0.20 0.004 0.000 0.008
D 12.00 0.472
e D1 10.00 0.394
E1 E
E 12.00 0.472
E1 10.00 0.394
e 0.80 0.031
θ 0° 3.5° 7° 0° 3.5° 7°
c L 0.45 0.60 0.75 0.018 0.024 0.030

L1
L1 1.00 0.039
L
h Number of Pins
N 44
Figure 89. 32-Pin Thin Quad Flat Package
mm inches
Dim.
D A A 1.60 0.063
D1 A2 A1 0.05 0.15 0.002 0.006
A2 1.35 1.40 1.45 0.053 0.055 0.057
A1 b 0.30 0.37 0.45 0.012 0.015 0.018
C 0.09 0.20 0.004 0.008
e D 9.00 0.354
D1 7.00 0.276
E1 E
b E 9.00 0.354
E1 7.00 0.276
e 0.80 0.031
c θ 0° 3.5° 7° 0° 3.5° 7°
L1
L 0.45 0.60 0.75 0.018 0.024 0.030
L
h L1 1.00 0.039
Number of Pins
N 32
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PACKAGE MECHANICAL DATA (Cont’d)

Figure
- 90. 42-Pin Plastic Dual In-Line Package, Shrink 600-mil Width
mm inches
Dim.
E Min Typ Max Min Typ Max
A 5.08 0.200
A2 A A1 0.51 0.020
A2 3.05 3.81 4.57 0.120 0.150 0.180
A1 L c E1
b 0.38 0.46 0.56 0.015 0.018 0.022
b2 b e eA
eB
b2 0.89 1.02 1.14 0.035 0.040 0.045
D
E c 0.23 0.25 0.38 0.009 0.010 0.015
D 36.58 36.83 37.08 1.440 1.450 1.460
0.015
E 15.24 16.00 0.600 0.630
GAGE PLANE
E1 12.70 13.72 14.48 0.500 0.540 0.570
e 1.78 0.070
eA 15.24 0.600
eC eB 18.54 0.730
eB
eC 1.52 0.000 0.060
L 2.54 3.30 3.56 0.100 0.130 0.140
Number of Pins
N 42
Figure 91. 32-Pin Plastic Dual In-Line Package, Shrink 400-mil Width
mm inches
Dim.
E eC
A 3.56 3.76 5.08 0.140 0.148 0.200
A1 0.51 0.020
A2 A
A2 3.05 3.56 4.57 0.120 0.140 0.180
A1 b 0.36 0.46 0.58 0.014 0.018 0.023

L
E1 b1 0.76 1.02 1.40 0.030 0.040 0.055
C eA
b2 b e eB
C 0.20 0.25 0.36 0.008 0.010 0.014
D D 27.43 28.45 1.080 1.100 1.120
E 9.91 10.41 11.05 0.390 0.410 0.435
E1 7.62 8.89 9.40 0.300 0.350 0.370
e 1.78 0.070
eA 10.16 0.400
eB 12.70 0.500
eC 1.40 0.055
L 2.54 3.05 3.81 0.100 0.120 0.150
Number of Pins
N 32
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13.2 THERMAL CHARACTERISTICS

Symbol Ratings Value Unit
Package thermal resistance (junction to ambient)
TQFP44 10x10 52
RthJA TQFP32 7x7 70 °C/W
SDIP42 600mil 55
SDIP32 200mil 50
PD Power dissipation 1) 500 mW
2)
TJmax Maximum junction temperature 150 °C
Notes:
1. The power dissipation is obtained from the formula PD=PINT+PPORT where PINT is the chip internal power (IDDxVDD)
and PPORT is the port power dissipation determined by the user.
2. The average chip-junction temperature can be obtained from the formula TJ = TA + PD x RthJA.
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13.3 SOLDERING INFORMATION

In order to meet environmental requirements, ST
offers these devices in ECOPACK® packages.
These packages have a lead-free second level in-
terconnect. The category of second level intercon-
nect is marked on the package and on the inner
box label, in compliance with JEDEC Standard
JESD97. The maximum ratings related to solder-
ing conditions are also marked on the inner box la-
bel.
ECOPACK is an ST trademark. ECOPACK®
specifications are available at www.st.com.
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14 ST72324 DEVICE CONFIGURATION AND ORDERING INFORMATION
14.1 FLASH OPTION BYTES

STATIC OPTION BYTE 0 STATIC OPTION BYTE 1
7 Reserved 0 7 0
Reserved
Reserved
WDG VD OSCTYPE OSCRANGE
PLLOFF
FMP_R
RSTC
PKG1
HALT
SW
1 0 1 0 2 1 0
Default 1 1 1 0 0 1 1 1 1 1 1 0 1 1 1 1
The option bytes allows the hardware configura- Selected Low Voltage Detector VD1 VD0
tion of the microcontroller to be selected. They
have no address in the memory map and can be LVD and AVD Off 1 1
accessed only in programming mode (for example Lowest Voltage Threshold (VDD~3V) 1 0
using a standard ST7 programming tool). The de- Medium Voltage Threshold (VDD~3.5V) 0 1
fault content of the FLASH is fixed to FFh. To pro- Highest Voltage Threshold (VDD~4V) 0 0
gram directly the FLASH devices using ICP,
FLASH devices are shipped to customers with the Caution: If the medium or low thresholds are se-
internal RC clock source. lected, the detection may occur outside the speci-
fied operating voltage range. Below 3.8V, device
OPTION BYTE 0 operation is not guaranteed. For details on the
OPT7= WDG HALT Watchdog reset on HALT AVD and LVD threshold levels refer to Section
This option bit determines if a RESET is generated 12.4.1 on page 119
when entering HALT mode while the Watchdog is
active.
0: No Reset generation when entering Halt mode OPT2:1 = Reserved, must be kept at default value.
1: Reset generation when entering Halt mode
OPT0= FMP_R Flash memory read-out protection
OPT6= WDG SW Hardware or software watchdog Read-out protection, when selected, provides a
This option bit selects the watchdog type. protection against Program Memory content ex-
0: Hardware (watchdog always enabled) traction and against write access to Flash memo-
1: Software (watchdog to be enabled by software) ry.
Erasing the option bytes when the FMP_R option
OPT5 = Reserved, must be kept at default value. is selected causes the whole user memory to be
erased first, and the device can be reprogrammed.
Refer to Section 7.3.1 on page 37 and the ST7
OPT4:3= VD[1:0] Voltage detection Flash Programming Reference Manual for more
These option bits enable the voltage detection details.
block (LVD, and AVD) with a selected threshold for 0: Read-out protection enabled
the LVD and AVD. 1: Read-out protection disabled
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ST72324 DEVICE CONFIGURATION AND ORDERING INFORMATION (Cont’d)

OPTION BYTE 1 these option bits select the resonator oscillator
OPT7= PKG1 Pin package selection bit current source corresponding to the frequency
This option bit selects the package. range of the used resonator. Otherwise, these bits
are used to select the normal operating frequency
Version Selected Package PKG1
range.
J TQFP44 / SDIP42 1
OSCRANGE
K TQFP32 / SDIP32 0 Typ. Freq. Range
2 1 0
Note: On the chip, each I/O port has 8 pads. Pads LP 1~2MHz 0 0 0
that are not bonded to external pins are in input
pull-up configuration after reset. The configuration MP 2~4MHz 0 0 1
of these pads must be kept at reset state to avoid MS 4~8MHz 0 1 0
added current consumption.
HS 8~16MHz 0 1 1
OPT6 = RSTC RESET clock cycle selection

This option bit selects the number of CPU cycles OPT0 = PLL OFF PLL activation
applied during the RESET phase and when exiting This option bit activates the PLL which allows mul-
HALT mode. For resonator oscillators, it is advised tiplication by two of the main input clock frequency.
to select 4096 due to the long crystal stabilization The PLL must not be used with the internal RC os-
time. cillator. The PLL is guaranteed only with an input
0: Reset phase with 4096 CPU cycles frequency between 2 and 4MHz.
1: Reset phase with 256 CPU cycles 0: PLL x2 enabled
1: PLL x2 disabled
OPT5:4 = OSCTYPE[1:0] Oscillator Type CAUTION: the PLL can be enabled only if the
These option bits select the ST7 main clock “OSC RANGE” (OPT3:1) bits are configured to
source type. “MP - 2~4MHz”. Otherwise, the device functionali-
ty is not guaranteed.
OSCTYPE
Clock Source
1 0
Resonator Oscillator 0 0
Reserved 0 1
Internal RC Oscillator 1 0
External Source 1 1
OPT3:1 = OSCRANGE[2:0] Oscillator range

When the resonator oscillator type is selected,
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DEVICE CONFIGURATION AND ORDERING INFORMATION (Cont’d)
14.2 FLASH DEVICE ORDERING INFORMATiON

With the objective of continuous improvement, ST
is developing new ST72F324B devices and is
transferring the production to higher capacity fabs.
Refer to the following tables for guidance on order-
ing.
Standard and Industrial Versions
■ For new designs the ST72F324B devices from
to the separate ST72324B datasheet.
■ For for running production orders select the
devices from Table 26
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DEVICE CONFIGURATION AND ORDERING INFORMATION (Cont’d)

Table 26. Standard and Industrial ST72F324 Flash Order Codes
Part Number Package Flash Memory (KBytes) Temp. Range
ST72F324K2B5 8
ST72F324K4B5 SDIP32 16
-10°C +85°C
ST72F324K6B5 32
ST72F324J6B5 SDIP42 32
ST72F324K6T5 32 -10°C +85°C
ST72F324K2T6 8
ST72F324K4T6 16 -40°C +85°C
ST72F324K6T6 TQFP32 32
ST72F324K2T3 8
ST72F324K4T3 16 -40°C +125°C
ST72F324K6T3 32
ST72F324J6T5 32 -10°C +85°C
ST72F324J2T6 8
ST72F324J4T6 16 -40°C +85°C
ST72F324J6T6 TQFP44 32
ST72F324J2T3 8
ST72F324J4T3 16 -40°C +125°C
ST72F324J6T3 32
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14.3 SILICON IDENTIFICATION

The various ST72F324, ST72F324B and
ST72324B devices are identifiable both by the last
letter of the Trace code marked on the device
package and by the last 3 digits of the Internal
Sales Type printed on the box label.
Table 27. Silicon Identification (Standard and Industrial Versions)

Trace Code Internal Sales Types
Device Status Fab Memory
marked on device on box label
Current production Phoenix “xxxxxxxxx1” 72F324xxxx$x7
8K to 32K
ST72F324xxxx End of production
Rousset Flash “xxxxxxxxxW” 72F324xxxx$x5
Dec. 2005
Current production.
ST72F324Bxxxx Recommended for Rousset 8K/16K Flash “xxxxxxxxxB” 72F324Bxxxx$x4
new designs
32K ROM “xxxxxxxxxA” 72324Bxxxx$x1
ST72324Bxxxx Current production Phoenix
8K/16K ROM “xxxxxxxxxB” 72324Bxxxx$x3
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14.4 DEVELOPMENT TOOLS Two configurations are available from ST:

■ STXF521-IND/USB: Low-cost In-Circuit
STMicroelectronics offers a range of hardware
and software development tools for the ST7 micro- Debugging kit from Softec Microsystems.
controller family. Full details of tools available for Includes STX-InDART/USB board (USB port)
the ST7 from third party manufacturers can be ob- and a specific demo board for ST72521
tain from the STMicroelectronics Internet site: (TQFP64)
➟ http//:mcu.st.com. ■ STxF-INDART
Tools from these manufacturers include C compli- Flash Programming tools

ers, emulators and gang programmers. ■ ST7-STICK ST7 In-circuit Communication Kit, a
Emulators complete software/hardware package for

programming ST7 Flash devices. It connects to
Two types of emulators are available from ST for a host PC parallel port and to the target board or
the ST72324 family: socket board via ST7 ICC connector.
■ ST7 DVP3 entry-level emulator offers a flexible
■ ICC Socket Boards provide an easy to use and
and modular debugging and programming flexible means of programming ST7 Flash
solution. SDIP42 & SDIP32 probes/adapters devices. They can be connected to any tool that
are included, other packages need a specific supports the ST7 ICC interface, such as ST7
connection kit (refer to Table 28) EMU3, ST7-DVP3, inDART, ST7-STICK, or
■ ST7 EMU3 high-end emulator is delivered with many third-party development tools.
everything (probes, TEB, adapters etc.) needed
Evaluation board
to start emulating the ST72324 family. To
configure it to emulate other ST7 subfamily ■ ST7232x-EVAL with ICC connector for
devices, the active probe for the ST7EMU3 can programming capability. Provides direct
be changed and the ST7EMU3 probe is connection to ST7-DVP3 emulator. Supplied
designed for easy interchange of TEBs (Target with daughter boards (core module) for
Emulation Board). See Table 28. ST72F321, ST72F324 & ST72F521 (the
ST72F321 & ST72F324 chips are not included)
In-circuit Debugging Kit
Table 28. STMicroelectronics Development Tools
Emulation Programming
Supported ST7 DVP3 Series ST7 EMU3 series
Products Active Probe & ICC Socket Board
Emulator Connection kit Emulator
T.E.B.
ST72324BJ,
ST7MDT20-T44/
ST72F324J, ST7MDT20-DVP3
DVP
ST72F324BJ ST7MDT20J-
ST7MDT20J-TEB ST7SB20J/xx1
ST72324BK, EMU3
ST7MDT20-T32/
ST72F324K, ST7MDT20-DVP3
DVP
ST72F324BK
Note 1: Add suffix /EU, /UK, /US for the power supply of your region.
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14.4.1 Socket and Emulator Adapter

Information
For information on the type of socket that is sup-
plied with the emulator, refer to the suggested list
of sockets in Table 29.
Note: Before designing the board layout, it is rec-
ommended to check the overall dimensions of the
socket as they may be greater than the dimen-
sions of the device.
For footprint and other mechanical information
about these sockets and adapters, refer to the
manufacturer’s datasheet (www.yamaichi.de for
TQFP44 10 x 10 and www.ironwoodelectron-
ics.com for TQFP32 7 x 7).
Table 29. Suggested List of Socket Types
Socket (supplied with Emulator Adapter (supplied with
Device
ST7MDT20J-EMU3) ST7MDT20J-EMU3)
TQFP32 7 X 7 IRONWOOD SF-QFE32SA-L-01 IRONWOOD SK-UGA06/32A-01
TQFP44 10 X10 YAMAICHI IC149-044-*52-*5 YAMAICHI ICP-044-5
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14.5 ST7 APPLICATION NOTES

Table 30. ST7 Application Notes
IDENTIFICATION DESCRIPTION
APPLICATION EXAMPLES
AN1658 SERIAL NUMBERING IMPLEMENTATION
AN1720 MANAGING THE READ-OUT PROTECTION IN FLASH MICROCONTROLLERS
AN1755 A HIGH RESOLUTION/PRECISION THERMOMETER USING ST7 AND NE555
EXAMPLE DRIVERS
AN 969 SCI COMMUNICATION BETWEEN ST7 AND PC
AN 970 SPI COMMUNICATION BETWEEN ST7 AND EEPROM
AN 972 ST7 SOFTWARE SPI MASTER COMMUNICATION
AN 973 SCI SOFTWARE COMMUNICATION WITH A PC USING ST72251 16-BIT TIMER
AN 974 REAL TIME CLOCK WITH ST7 TIMER OUTPUT COMPARE
AN 976 DRIVING A BUZZER THROUGH ST7 TIMER PWM FUNCTION
AN 979 DRIVING AN ANALOG KEYBOARD WITH THE ST7 ADC
AN 980 ST7 KEYPAD DECODING TECHNIQUES, IMPLEMENTING WAKE-UP ON KEYSTROKE
AN1041 USING ST7 PWM SIGNAL TO GENERATE ANALOG OUTPUT (SINUSOÏD)
AN1044 MULTIPLE INTERRUPT SOURCES MANAGEMENT FOR ST7 MCUS
AN1046 UART EMULATION SOFTWARE
AN1047 MANAGING RECEPTION ERRORS WITH THE ST7 SCI PERIPHERALS
AN1048 ST7 SOFTWARE LCD DRIVER
AN1078 PWM DUTY CYCLE SWITCH IMPLEMENTING TRUE 0% & 100% DUTY CYCLE
AN1445 EMULATED 16 BIT SLAVE SPI
AN1504 STARTING A PWM SIGNAL DIRECTLY AT HIGH LEVEL USING THE ST7 16-BIT TIMER
GENERAL PURPOSE
AN1476 LOW COST POWER SUPPLY FOR HOME APPLIANCES
AN1709 EMC DESIGN FOR ST MICROCONTROLLERS
AN1752 ST72324 QUICK REFERENCE NOTE
PRODUCT EVALUATION
AN 910 PERFORMANCE BENCHMARKING
AN 990 ST7 BENEFITS VERSUS INDUSTRY STANDARD
AN1150 BENCHMARK ST72 VS PC16
AN1151 PERFORMANCE COMPARISON BETWEEN ST72254 & PC16F876
AN1278 LIN (LOCAL INTERCONNECT NETWORK) SOLUTIONS
PRODUCT MIGRATION
AN1131 MIGRATING APPLICATIONS FROM ST72511/311/214/124 TO ST72521/321/324
GUIDELINES FOR MIGRATING ST72F324 & ST72F321 APPLICATIONS TO ST72F324B,
AN2197
ST72F321B OR ST72F325
PRODUCT OPTIMIZATION
AN 982 USING ST7 WITH CERAMIC RESONATOR
AN1014 HOW TO MINIMIZE THE ST7 POWER CONSUMPTION
AN1015 SOFTWARE TECHNIQUES FOR IMPROVING MICROCONTROLLER EMC PERFORMANCE
AN1070 ST7 CHECKSUM SELF-CHECKING CAPABILITY
AN1181 ELECTROSTATIC DISCHARGE SENSITIVE MEASUREMENT
AN1502 EMULATED DATA EEPROM WITH ST7 HDFLASH MEMORY
ACCURATE TIMEBASE FOR LOW-COST ST7 APPLICATIONS WITH INTERNAL RC OSCILLA-
AN1530
TOR
AN1636 UNDERSTANDING AND MINIMIZING ADC CONVERSION ERRORS
PROGRAMMING AND TOOLS
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Table 30. ST7 Application Notes

IDENTIFICATION DESCRIPTION
AN 978 ST7 VISUAL DEVELOP SOFTWARE KEY DEBUGGING FEATURES
AN 983 KEY FEATURES OF THE COSMIC ST7 C-COMPILER PACKAGE
AN 985 EXECUTING CODE IN ST7 RAM
AN 986 USING THE INDIRECT ADDRESSING MODE WITH ST7
AN 987 ST7 SERIAL TEST CONTROLLER PROGRAMMING
AN 988 STARTING WITH ST7 ASSEMBLY TOOL CHAIN
AN 989 GETTING STARTED WITH THE ST7 HIWARE C TOOLCHAIN
AN1039 ST7 MATH UTILITY ROUTINES
AN1064 WRITING OPTIMIZED HIWARE C LANGUAGE FOR ST7
AN1106 TRANSLATING ASSEMBLY CODE FROM HC05 TO ST7
AN1446 USING THE ST72521 EMULATOR TO DEBUG A ST72324 TARGET APPLICATION
AN1478 PORTING AN ST7 PANTA PROJECT TO CODEWARRIOR IDE
AN1575 ON-BOARD PROGRAMMING METHODS FOR XFLASH AND HDFLASH ST7 MCUS
AN1576 IN-APPLICATION PROGRAMMING (IAP) DRIVERS FOR ST7 HDFLASH OR XFLASH MCUS
AN1635 ST7 CUSTOMER ROM CODE RELEASE INFORMATION
AN1754 DATA LOGGING PROGRAM FOR TESTING ST7 APPLICATIONS VIA ICC
AN1796 FIELD UPDATES FOR FLASH BASED ST7 APPLICATIONS USING A PC COMM PORT
SYSTEM OPTIMIZATION
AN1711 SOFTWARE TECHNIQUES FOR COMPENSATING ST7 ADC ERRORS
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15 KNOWN LIMITATIONS
15.1 ALL DEVICES Example:

15.1.1 External RC option SIM
The External RC clock source option described in reset interrupt flag
previous datasheet revisions is no longer support- RIM
ed and has been removed from this specification. Nested interrupt context:
15.1.2 CSS Function The symptom does not occur when the interrupts
The Clock Security System function has been re- are handled normally, i.e.
moved from the datasheet. when:
15.1.3 Safe Connection of OSC1/OSC2 Pins – The interrupt flag is cleared within its own inter-
The OSC1 and/or OSC2 pins must not be left un- rupt routine
connected otherwise the ST7 main oscillator may – The interrupt flag is cleared within any interrupt
start and, in this configuration, could generate an routine with higher or identical priority level
fOSC clock frequency in excess of the allowed
maximum (>16MHz.), putting the ST7 in an un- – The interrupt flag is cleared in any part of the
safe/undefined state. Refer to Section 6.2 on page code while this interrupt is disabled
24. If these conditions are not met, the symptom can
15.1.4 Unexpected Reset Fetch be avoided by implementing the following se-
quence:
If an interrupt request occurs while a “POP CC” in-
struction is executed, the interrupt controller does PUSH CC
not recognise the source of the interrupt and, by SIM
default, passes the RESET vector address to the
CPU. reset interrupt flag
Workaround POP CC
To solve this issue, a “POP CC” instruction must 15.1.6 External Interrupt Missed
always be preceded by a “SIM” instruction. To avoid any risk of generating a parasitic inter-
15.1.5 Clearing active interrupts outside rupt, the edge detector is automatically disabled
interrupt routine for one clock cycle during an access to either DDR
and OR. Any input signal edge during this period
When an active interrupt request occurs at the will not be detected and will not generate an inter-
same time as the related flag is being cleared, an rupt.
unwanted reset may occur.
This case can typically occur if the application re-
Note: clearing the related interrupt mask will not freshes the port configuration registers at intervals
generate an unwanted reset during runtime.
Concurrent interrupt context Workaround
The symptom does not occur when the interrupts The workaround is based on software checking
are handled normally, i.e. the level on the interrupt pin before and after writ-
when: ing to the PxOR or PxDDR registers. If there is a
level change (depending on the sensitivity pro-
– The interrupt flag is cleared within its own inter- grammed for this pin) the interrupt routine is in-
rupt routine voked using the call instruction with three extra
– The interrupt flag is cleared within any interrupt PUSH instructions before executing the interrupt
routine routine (this is to make the call compatible with the
– The interrupt flag is cleared in any part of the IRET instruction at the end of the interrupt service
code while this interrupt is disabled routine).
If these conditions are not met, the symptom can But detection of the level change does ensure that
be avoided by implementing the following se- edge occurs during the critical 1 cycle duration and
quence: the interrupt has been missed. This may lead to
occurrence of same interrupt twice (one hardware
Perform SIM and RIM operation before and after and another with software call).
resetting an active interrupt request.
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KNOWN LIMITATIONS (Cont’d)

To avoid this, a semaphore is set to '1' before jrne OUT
checking the level change. The semaphore is call call_routine; call the interrupt routine
changed to level '0' inside the interrupt routine.
When a level change is detected, the semaphore OUT:LD A,#00
status is checked and if it is '1' this means that the LD sema,A
last interrupt has been missed. In this case, the in-
.call_routine ; entry to call_routine
terrupt routine is invoked with the call instruction.
PUSH A
PUSH X
There is another possible case, that is, if writing to
PxOR or PxDDR is done with global interrupts dis- PUSH CC
abled (interrupt mask bit set). In this case, the .ext1_rt ; entry to interrupt routine
semaphore is changed to '1' when the level
change is detected. Detecting a missed interrupt is LD A,#00
done after the global interrupts are enabled (inter- LD sema,A
rupt mask bit reset) and by checking the status of IRET
the semaphore. If it is '1' this means that the last
interrupt was missed and the interrupt routine is in- Case 2: Writing to PxOR or PxDDR with Global In-
voked with the call instruction. terrupts Disabled:
To implement the workaround, the following soft- SIM ; set the interrupt mask
ware sequence is to be followed for writing into the LD A,PFDR
PxOR/PxDDR registers. The example is for Port AND A,#$02
PF1 with falling edge interrupt sensitivity. The soft-
ware sequence is given for both cases (global in- LD X,A ; store the level before writing to
terrupt disabled/enabled). PxOR/PxDDR
Case 1: Writing to PxOR or PxDDR with Global In- LD A,#$90
terrupts Enabled: LD PFDDR,A ; Write into PFDDR
LD A,#01 LD A,#$ff
LD sema,A ; set the semaphore to '1' LD PFOR,A ; Write to PFOR
LD A,PFDR LD A,PFDR
AND A,#02 AND A,#$02
LD X,A ; store the level before writing to LD Y,A ; store the level after writing to
PxOR/PxDDR PxOR/PxDDR
LD A,#$90 LD A,X ; check for falling edge
LD PFDDR,A ; Write to PFDDR cp A,#$02
LD A,#$ff jrne OUT
LD PFOR,A ; Write to PFOR TNZ Y
LD A,PFDR jrne OUT
AND A,#02 LD A,#$01
LD Y,A ; store the level after writing to LD sema,A ; set the semaphore to '1' if edge is
PxOR/PxDDR detected
LD A,X ; check for falling edge RIM ; reset the interrupt mask
cp A,#02 LD A,sema ; check the semaphore status
jrne OUT CP A,#$01
TNZ Y jrne OUT
jrne OUT call call_routine; call the interrupt routine
LD A,sema ; check the semaphore status if RIM
edge is detected
OUT: RIM
CP A,#01
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JP while_loop Occurrence
.call_routine ; entry to call_routine The occurrence of the problem is random and pro-
PUSH A portional to the baudrate. With a transmit frequen-
cy of 19200 baud (fCPU=8MHz and SCI-
PUSH X BRR=0xC9), the wrong break duration occurrence
PUSH CC is around 1%.
.ext1_rt ; entry to interrupt routine Workaround
LD A,#$00 If this wrong duration is not compliant with the
LD sema,A communication protocol in the application, soft-
ware can request that an Idle line be generated
IRET before the break character. In this case, the break
15.1.7 16-bit Timer PWM Mode duration is always correct assuming the applica-
tion is not doing anything between the idle and the
In PWM mode, the first PWM pulse is missed after break. This can be ensured by temporarily disa-
writing the value FFFCh in the OC1R register bling interrupts.
(OC1HR, OC1LR). It leads to either full or no PWM
during a period, depending on the OLVL1 and The exact sequence is:
OLVL2 settings. - Disable interrupts
15.1.8 SCI Wrong Break duration - Reset and Set TE (IDLE request)
Description - Set and Reset SBK (Break Request)
A single break character is sent by setting and re- - Re-enable interrupts
setting the SBK bit in the SCICR2 register. In
some cases, the break character may have a long-
er duration than expected: 15.2 FLASH DEVICES ONLY
- 20 bits instead of 10 bits if M=0 15.2.1 Internal RC Operation
- 22 bits instead of 11 bits if M=1. In ST72F324J and ST72F324K devices, the inter-
nal RC oscillator is not supported if the LVD is dis-
In the same way, as long as the SBK bit is set,
abled.
break characters are sent to the TDO pin. This
may lead to generate one break more than expect-
ed.
161/164
1
ST72324Jx ST72324Kx
16 IMPORTANT NOTES ON ST72F324B FLASH DEVICES:

With the objective of continuous improvement, ST 16.5 Timer A Registers
has developed new ST72F324B devices. These
devices are fully compatible with all ROM features In ST72F324B Flash devices, all Timer A registers
and provide an improved price/performance ratio are present and their functionality is the same as
compared to the ST72F324 flash devices. described for ROM devices in the ST72324B da-
tasheet.
A summary of the technical improvements is given
below.
Refer to separate ST72324B datasheet for the or-
dering information and full specifications.
16.1 Reset Pin Logic levels

In ST72F324B Flash devices, the VIH/VIL levels for
the reset pin are the same as specified for ROM
devices
16.2 Wake-Up from Active Halt mode using

external interrupts
In ST72F324B Flash devices, any external inter-
rupt that capable of waking-up the MCU from Halt
mode can also wake-up the MCU from Active Halt
mode. Consequently note 1 below Table 8 on
page 36 does not apply to ‘B’ devices.
16.3 PLL Jitter

In ST72F324B Flash devices, PLL clock accuracy
is improved and the jitter is the same as specified
for ROM devices
16.4 Active Halt Power Consumption

In ST72F324B Flash devices, the power con-
sumption in Active Halt mode is specified as
230µA max. See Table 12.5.1 on page 120 for test
conditions.
162/164
1
ST72324Jx ST72324Kx
17 REVISION HISTORY
Table 31. Revision History
Date Revision Description of Changes
Merged ST72F324 Flash with ST72324B ROM datasheet.
Vt POR max modified in Section 12.4 on page 119
Added Figure 78 on page 137
05-May-2004 2.0 Modified VAREF min in “10-BIT ADC CHARACTERISTICS” on page 142
Modified I INJ for PB0 in Section 12.9
Added “Clearing active interrupts outside interrupt routine” on page 159
Modified “32K ROM DEVICES ONLY” on page 164
Removed Clock Security System (CSS) throughout document
Added notes on ST72F324B 8K/16K Flash devices in Table 1 and Table 27
Corrected MCO description in Table 1 and Section 10.2
Modified VtPOR in Section 12.4 on page 119
Static current consumption modified in Section 12.9 on page 133
Updated footnote and Figure 77 and Figure 78 on page 137
Modified Soldering information in Section 13.3
30-Mar-2005 3
Updated Section 14 on page 150
Added Table 27
Modified Figure 7 and note 4 in “FLASH PROGRAM MEMORY” on page 17
Added limitation on ICC entry mode with 39 pulses to “KNOWN LIMITATIONS” on
page 159
Added Section 16 on page 162 for ST72F324B 8K/16K Flash devices
Modified “Internal Sales Types on box label” in Table 29
08-Nov-2005 4 Removed information on ST72F324B and ROM devices (now in separate datasheet)
Changed status to “Not for new design”
04-Apr-2008 5 Added “External interrupt missed” in “KNOWN LIMITATIONS” on page 159
Removed information on automotive versions (now in separate datasheet)
163/164
1
ST72324Jx ST72324Kx
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ST72324Jx ST72324Kx

5V RANGE 8-BIT MCU WITH 8 TO 32K FLASH,

April 2008 Rev. 5 1/164

To obtain the most recent version of this datasheet,

1 INTRODUCTION tion set and are available with FLASH program

8-BIT CORE PROGRAM

BEEP / (HS) PF1

ICAP1_A / (HS) PF6

MCO / AIN8 / PF0

OCMP1_A / AIN10 / PF4

(HS) PB4 1 ei3 42 PB3

PIN DESCRIPTION (Cont’d)

(HS) PB4 1 PB3

Figure 4. 32-Pin TQFP 7x7 Package Pinout

(HS) 20mA high sink capability

PIN DESCRIPTION (Cont’d)

Pin Name Alternate Function

6 1 30 1 PB4 (HS) I/O CT HS X ei3 X X Port B4

Pin n° Level Port

3 REGISTER & MEMORY MAP

Table 2. Hardware Register Map

0000h PADR Port A Data Register 00h1) R/W

0003h PBDR Port B Data Register 00h1) R/W

0006h PCDR Port C Data Register 00h1) R/W

0009h PDADR Port D Data Register 00h1) R/W

000Ch PEDR Port E Data Register 00h1) R/W

000Fh PFDR Port F Data Register 00h1) R/W

0021h SPIDR SPI Data I/O Register xxh R/W

0024h ISPR0 Interrupt Software Priority Register 0 FFh R/W

0028h EICR External Interrupt Control Register 00h R/W

0029h FLASH FCSR Flash Control/Status Register 00h R/W

002Ah WATCHDOG WDGCR Watchdog Control Register 7Fh R/W

002Bh SI SICSR System Integrity Control Status Register xxh R/W

002Ch MCCSR Main Clock Control / Status Register 00h R/W

0031h TACR2 Timer A Control Register 2 00h R/W

0040h Reserved Area (1 Byte)

0041h TBCR2 Timer B Control Register 2 00h R/W

0050h SCISR SCI Status Register C0h Read Only

0070h ADCCSR Control/Status Register 00h R/W

Legend: x=undefined, R/W=read/write

4 FLASH PROGRAM MEMORY

4.1 Introduction Depending on the overall Flash memory size in the

4.2 Main Features 4K Sector 0

FLASH PROGRAM MEMORY (Cont’d)

4.4 ICC Interface – ICCCLK: ICC output serial clock pin

(See Note 3) ICC CONNECTOR

APPLICATION CL2 CL1

FLASH PROGRAM MEMORY (Cont’d)

5 CENTRAL PROCESSING UNIT

5.1 INTRODUCTION 5.3 CPU REGISTERS

CENTRAL PROCESSING UNIT (Cont’d)

CENTRAL PROCESSING UNIT (Cont’d)

Stack Higher Address = 01FFh

6 SUPPLY, RESET AND CLOCK MANAGEMENT

■ Multi-Oscillator Clock Management (MO)

Figure 11. Clock, Reset and Supply Block Diagram

OSC2 MULTI- fOSC fOSC2 MAIN CLOCK fCPU

RESET SEQUENCE AVD Interrupt Request WATCHDOG

6.2 MULTI-OSCILLATOR (MO)