A

PROJECT REPORT
ON
“MUSIC PLAYER IMPLEMENTED ON ZEDBOARD”
SUBMITTED IN THE PARTIAL FULFILLMENT OF THE REQUIREMENT FOR
THE AWARD OF DEGREE OF
MASTER OF TECHNOLOGY
IN
ELECTRONICS & COMMUNICATION ENGINEERING
By
SHEETAL
Roll No: 17001516008
under the Supervision of
Dr. Rajeshwar Das
(Assistant Professor, ECE Department, DCRUST,Murthal)
DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING

DEENBANDHU CHHOTU RAM UNIVERSITY OF SCIENCE AND

TECHNOLOGY
SONIPAT, HARYANA (INDIA)-131039
 DEENBANDHU CHHOTU RAM UNIVERSITY OF SCIENCE
AND TECHNOLOGY, MURTHAL, SONEPAT-131039.

CANDIDATE’S DECLARATION

I SHEETAL, declare that the work presented entitle “Music Player Implemented on
Zedboard” submitted in the Department of Electronics And Communication Engineering(VLSI
Design) of Deenbandhu Chhotu Ram University of Science & Technology, Murthal in the partial
fulfillment of the requirement for the award of degree of Master of Technology in Electronics
And Communication Engineering is an authentic record of my work carried out during the final
year, 2018-2019 at Deenbandhu Chhotu Ram University of Science & Technology, Murthal,
Haryana under the guidance of Dr. Rajeshwar Das, Assistant Professor. The matter embodied in
this work has not been submitted elsewhere by anyone for award of any other degree.

SHEETAL
17001516008
This is to certify that the above statement made by the candidate is correct to the best of
my knowledge.

Date: Dr. RAJESHWAR DAS

(Supervisor)
 ACKNOWLEDGEMENT

I would like to express a deep sense of gratitude and thanks profusely to my report
Supervisor, Dr. Rajeshwar Das, Assistant Professor, Electronics And Communication
Engineering of Deenbandhu Chhotu Ram University of Science & Technology, Murthal.
Without his wise counsel and able guidance, it would have been impossible to complete the
project in this manner. The help rendered by Dr. Pawan Kumar Dahiya, Coordinator of the VLSI
Design , Electronics & communication Engineering ,Deenbandhu Chhotu Ram University of
Science & Technology, Murthal, for experimentation/simulations is greatly acknowledged.
I also express my gratitude to other faculty members of Electronics And Communication
Engineering , Deenbandhu Chhotu Ram University of Science & Technology, Murthal, for their
intellectual support throughout the course of this work. Finally, I am indebted to
all whosoever have contributed in this report work.

Date: SHEETAL
M. Tech in ECE (VLSI DESIGN)
(17001516008)
 ABSTRACT

In recent years, FPGA technology has become increasingly powerful, less expensive, and more
practical for use in real-time vision applications. Human sensing (also called human detection or
human presence detection) encompasses a range of technologies for detecting the presence of a
human body in an area of space, typically without the intentional participation of the detected
person. Common applications include search and rescue, surveillance, and customer analytics. In
India and Japan like countries, the number of accidents resulting in injury or death on railway
track and station platforms is increasing at a higher rate than ever before. In the modern world,
the role of railway network is an essential for the people around the world. The railway system
consists of infrastructure, development and maintenance.

.
 TABLE OF CONTENTS

Contents Page no.

Candidate’s Declaration i

Acknowledgement ii

Abstract iii

Table of contents iv

List of figures v

List of tables vi

1. Introduction 1

2. Objective 2

3. Hardware and Software Used 3

3.1 Design Considerations 6

4. Project Description 8

4.1 Technology Used 8

4.2 System Description 9

5. proposed Methodology 12
 5.1 SPI Interface 13

5.2 I2S Interface 14

5.3 Wave files and Wav files Library 15

6. Verilog Coding 17

6.1 RTL View 25

7.Advantages and Disadvantages 26

8. Conclusion and Future Scope 27

9. Reference 28

LIST OF FIGURES
Fig.no Description Page no.

3.1 Hardware Description 5

4.1 Zed Board Diagram 8

4.2 High Level System Block Diagram 9

5.1 Proposed Methodology 12

5.2 SPI Interface 13

5.3 I2S Interface 14

5.4 Wave File Format 16

6.1 RTL View 25

 LIST OF TABLES

Table no. Description Page no.

4.1 Equipments Table

 CHAPTER 1

INTRODUCTION

On recent developments in railway systems, high-speed trains are being extensively used,
and rail transportation is being increased. Reasons for this increase are high speed, cost
effectiveness, environment friendly, safety, and modern characteristics of railway systems.
In railway tracks, anytime the track is damaged due to weather conditions, floods,
earthquakes, cyclones etc. The existing track surveying systems have some limitations. It
takes more time and it is less accurate. In this paper, the proposed system immediately
notices the cracks in the track and informs the railway authority and hence can reduce the
train accidents. Thus by placing the robot in each station and checking at even intervals will
help to reduce train accidents. The robotic section in the proposed system consists of
ultrasonic sensor which finds the obstacle on the track and IR sensor to detect the track.

For development of railway track management system, The current status of the railway
track and controlling of the barricade at railway crossing more important parameter as
compared to others as it has crucial role in avoiding an accident caused by derailment of
train which saves millions of lives every year .the automatic barricade opening and closing
at the railway crossing help to avoid collision of vehicle at the crossing by train. Study of
crack and the obstacle detection are calculated based on the information available from the
UV sensor and IR sensors respectively. Based on the information provided by robot section
to control station via zigbee module, the control section control the signal light and the
barricade at the railway crossing.
 CHAPTER 2

OBJECTIVES
 Gain in-depth understanding of hardware/software co-design using an FPGA,
 Understand the specifications set for Railway track Management systems and
 Build a FPGA-based system, which implements the HUMAN DETECTION ON
RAILWAY TRACK using Verilog and C language on the Vivado Software
Development Kit (SDK) software platform.
 CHAPTER 3

3. HARDWARE AND SOFTWARE TO BE USED

• Zedboard development kit

• 5V Power Supply

• PIR Sensor

• Xilinx Vivado and SDK 2017.2

VIVADO

Vivado Design Suite is a software suite produced by Xilinx for synthesis and analysis
of HDL designs, superseding XilinX ISE with additional features for SOC development
and high-level synthesis.  Vivado represents a ground-up rewrite and re-thinking of the
entire design flow (compared to ISE), and has been described by reviewers as "well
conceived, tightly integrated, blazing fast, scalable, maintainable, and intuitive".

Vivado enables developers to synthesize their designs, perform timing analysis,

examine RTL diagrams, simulate a design's reaction to different stimuli, and configure
the target device with the programmer. Vivado is a design environment for FPGA
products from Xilinx, and is tightly-coupled to the architecture of such chips, and cannot
be used with FPGA products from other vendors.

Vivado supports newer high capacity devices, and speeds the design of programmable
logic and sI/O. Vivado provides faster integration and implementation for programmable
systems into devices with 3D stacked silicon interconnect technology, ARM processing
systems, analog mixed signal (AMS), and many semiconductor intellectual property (IP)
cores

Vivado is targeted at Xilinx's larger FPGAs, and is slowly replacing Xilinx ISE as their
mainline tool chain

Zed Board

The zedboard Board is a single-board computer based on Xilinx's Zynq device
family.
ZedBoard is a complete development kit for designers interested in exploring designs
using the Xilinx Zynq. The board contains all the necessary interfaces and supporting
functions to enable a wide range of applications. The expandability features of the board
make it ideal for rapid prototyping and proof-of-concept development.

It include
•ZedBoard
•12V Power supply
•Micro USB cable
•USB Adapter: Male Micro-B to Female Standard-A
•4 GB SD Card
•Xilinx ISE WebPACK software with a device locked ChipScope license
•Getting started guide
•Downloadable documentation and reference designs
;
 Hardware Parts

Figure 3.1: Hardware Parts

CHAPTER 4
 PROJECT DESCRIPTION

4.1 TECHNOLOGY USED

 This projects is implemented on ZedBoard which basically a FPGA based

Development board.

 This project detects the human on railway track with the help of PIR sensor and the
signal of PIR sensor is sent to the ZedBoard.

 The ZedBoard FPGA is reconfigure with the help of Verilog coding, in which PIR
sensor signal acts as input.

 The coding will generates the FPGA hardware which can decode the input signal and
produces required signal which can be interpreted by the station master as
notification.

 The reconfigurable and fast response characteristics of FPGA will leads the human
safety on track.

 The whole functionality is encapsulated in IP (Intellectual Property), which can be

further integrated with the other system architecture.
Figure 4.1 Zed Board Diagram
 4.2 System Description

• This project presents an FPGA-based system for detecting people on railway track in both
day and night time efficiently.

• During day or night the human is detected on railway track with the help of Passive Infrared
or Pyroelectric or IR motion sensors (simply PIR sensor).

• PIRs are basically made of a pyroelectric sensor, which can detect levels of infrared
radiation. Everything emits some low level radiation, and the hotter something is, the more
radiation is emitted. The change in IR radiation will be detected by sensor and generate a
3.3 volt signal.

• Such sensor are located on the railway track at various accident prone areas.

• The detected signal is sent to the FPGA board which generates the required action signal
and also inform to the station master. The station master will give this information to the
coming train’s loco pilot.

Figure 4.2 High Level System Block Diagram

 CHAPTER 5

PROPOSED METHODOLOGY

Proposed Methodology

Control Signals OLED Display

Read Wav file SPI Interface Track name,
from SD card
Vol Level etc.

Send digital Control Signals LED 8 Bit Signals

8 LED on Zed
data to I2S Processing System board
interface

Data/Control Signals
Playing the UART Interface
audio file with PC

Figure 5.1:Proposed Methodology

 The system will read an MP3 file from a compact flash memory, decode the MP3 bit
stream into 16-bit pulse code modulated (PCM) outputs using a standard MP3 decoding
algorithm, and play the output through an external speaker.

 C programming language is used to run on a Microblaze 32-bit processor. Hardware

description language such as VHDL is used to drive external peripherals, including the
stereo AC97 codec and LCD controller.
  The AC97 codec converts the digital PCM outputs into an analog sound wave, and the
LCD controller displays the title and author information of the selected song. The
software and hardware designs are integrated on the Xilinx Embedded Development Kit
platform.

 In this project, data compression techniques are used in MP3 encoding and decoding
are explored and tested on hardware.

5.1 SPI Interface

Figure 5.2:SPI INTERFACE

• In SPI protocol, the devices are connected in a Master – Slave relationship in a multi
– point interface. In this type of interface, one device is considered the Master of the
bus (usually a Microcontroller) and all the other devices (peripheral ICs or even
other Microcontrollers) are considered as slaves.
• In SPI protocol, there can be only one master but many slave devices.
• The SPI bus consists of 4 signals or pins. They are
1. Master - Out / Slave – In (MOSI)
2. Master - In/ Slave – Out (MISO)
 3. Serial Clock (SCLK) and
4. Chip Select(CS) or Slave Select(SS)

5.2 I2S (Inter- IC Sound Bus ) Interface

Figure 5.3: I2S (Inter- IC Sound Bus ) Interface

5.2.1 General Description

The Integrated Inter-IC Sound Bus (I2S) is a serial bus interface standard used for
connecting digital audio devices together. The specification is from Philips
Semiconductor (I2S bus specification; February 1986, revised June 5, 1996). The
I2S component operates in master mode only. It also operates in two directions: as a
transmitter (Tx) and a receiver (Rx). The data for Tx and Rx are independent byte
streams. The byte streams are packed with the most significant byte first and the
most significant bit in bit 7 of the first word. The number of bytes used for each
sample (a sample for the left or right channel) is the minimum number of bytes to
hold a sample.

When to use an I2S The component provides a serial bus interface for stereo audio
data. This interface is most commonly used by audio ADC and DAC components.
5.2.2 Features of I2C

• The I2S Audio Interface provides a bidirectional, synchronous, serial interface to off-
chip audio devices.
• The I2S bus carries two channels, left and right, which are typically used to carry
stereo audio data streams. The data alternates between left and right channels, as
controlled by a word select signal driven by the bus master.
• Programmable word select resolution (8-32 clock cycles) in master mode
• Four reference clock sources selectable for bit clock generation with programmable
clock divider
• Interrupt-driven or DMA operation
• Four 8-word FIFOs (left/right; transmit/receive)
• Programmable FIFO threshold levels for interrupt or DMA request generation
• Additional interrupts for transmit FIFO underrun and receive FIFO overrun with
separate enables
• Freeze/suspend operation for system debug support
• Local clock gating for minimal power consumption

5.3 WAVE Files & WAVE File Library

WAVE (Waveform Audio File Format) files are an audio-specialized file format subset of
RIFF (Resource Interchange File Format) files, generic Microsoft multimedia files. WAVE
file format was the chosen format for music due to the simplicity of WAVE file format and
their ease of use – also, no group member had much experience with complex audio formats
or compression issues. Most simply, a wave file begins with a header section, including
fields containing attributes and parameters, and is then followed by samples of sound. Of
especial importance is the ChunkSize field, it contains the entire file size in bytes, minus 8
bytes for the previous ChunkID and ChunkSize fields. Standard WAVE file format is shown
below in Figure 3.4.
 Figure 5.4: Wave File

New WAVE ,files, however, do not exactly follow the standard WAVE file format described
above, they follow an “extended WAVE file format”. This presented a few problems for us in
trying to read the size of the data segment in the WAVE file header. This problem was
remedied by assuming an extra 2 bytes of data existed before the audio data section began.
Additionally creating problems for us was the little-endian convention of most fields. Little-
endian storage convention means that bytes are stored with their least significant bit first
and later have to be ‘reconstructed’ to the correct form before manipulation of processing.
Reconstructing data of 16 and 32-bit integers was accomplished in the audio controller,
detailed in the hardware section of this report.

An independent WAVE file library was implemented, allowing the FPGA-pod to look for
WAVE files with the correct sample rate, read WAVE files, and send audio data to the audio
controller, detailed in the hardware section. Population of a playlist is made possible
through the use of this WAVE file library. Using functions from the library, the SD card is
scanned and then an entry is made in the playlist corresponding to a WAVE file in the
directory to later be used for user interfacing.
 CHAPTER 6

VERILOG CODING

timescale 1ps / 1ps

module design_1_wrapper

(Clock_input,

S1,

S1_Detects,

S2,

S2_Detects,

Wave1,

Wave2,

Wave3);

Input Clock_input;

Input S1;

Output S1_Detects;

Input S2;

Output S2_Detects;

Output Wave1;

Output Wave2;

Output Wave3;;
 Wire Clock_Input;

Wire S1;

Wire S1_Detects;

Wire S2;

Wire S2_Detects;

Wire Wave1;

Wire Wave2;

Wire Wave3;

design_1 design_1_1

(.Clock_input(Clock_input),

.S1(S1),

.S1_Detects(S1_Detects),

.S2(S2),

.S2_Detects(S2_Detects),

.wave1(Wave1),

.wave2(Wave2),

.wave3(Wave3));

endmodule
 CHAPTER 7
CONCLUSION & FUTURE SCOPE
• Safety of passengers due to accident cause by emergency breaks whenever any human
detected on railway track in front of fast moving train.
• Save life on railway track due to accident. The main advantage of this project is that it is able
to detect presence of human even in dark night or day as well, irrespective or various kind
of weather condition like fog, humidity, rain and temperature.
• The future scope of this project includes, sending sensor data to the station controller and
loco pilot directly using wireless communication.
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