Fabrication and Characterization of Vertically Stacked

Gate-AIl-Around Si Nanowire FET Arrays

Davide Sacchetio", M. Haykel Ben-Jamaa l , Giovanni De Micheli l and Yusuf Leblebici 2
1 Integrated System Laboratory (LSI), 2Microelectronic System Laboratory (LSM)
Ecole Polytechnique Federale de Lausanne, Lausanne, Switzerland
e-mail: davide.sacchetto@epfl.ch

Abstract- We describe the fabrication of vertically SiGe selective etching leaves vertically-stacked Si nanowires.
stacked Silicon Nanowire Field Effect Transistors (SiNW Hydrogen annealing is then used to change the SiNW shapes
FETs) in Gate-All Around (GAA) configuration. Stacks
from rectangular to circular, thus yielding channels with less
with the number of channels ranging from 1 to 12 have
been successfully produced by means of a micrometer scale surface roughness and improved controllability.
lithography and conventional fabrication techniques. It is An alternative approach for the fabrication of vertically-
shown that demonstrator Schottky Barrier (SB) devices fab- stacked SiNWs [11] is based on producing a scalloped trench
ricated with Cr /NiCr contacts present good subthreshold in bulk silicon by means of Deep Reactive Ion Etching (DRIE).
4
slope (70mV/dec), IoN/loF F ratio 2:10 and reproducible Sacrificial oxidation steps are performed to reduce the dimen-
ambipolar behavior.
sions of the trench. Thanks to scalloping, the Si trench is
Index Terms-nanowire, FET, multichannel, ambipolar, totally consumed in its thinner parts, leaving a vertical stack of
vertical integration
suspended SiNWs. Although the DRIE process defines trenches
of micrometer dimensions, the iteration of oxidation steps is
I. INTRODUCTION capable for reducing the structures to suspended nanowires

C ont inuing efforts in Complementary-Metal-Oxide-

Semiconductor (CMOS) research have lead to the
exponential increase of device integration density during
with of 20 nm in diameter [11]. This approach has also been
demonstrated to be suitable for producing vertically stacked
SiNW with small dimensions and different section shapes [12],
the last 40 years. More recently increasing fabrication costs yet it has not been used so far for G AA FET fabrication.
and increasing overall variability have become an obstacle
for the scaling trend. In order to overcome such limitations, III. DEVICE FABRICATION
considerable research is dedicated for instance to the use In our work we produce vertical SiNW arrays by means of
of new materials (such as high-x dielectrics with metal optical lithography with 1 Mm resolution limit. Sub-micrometer
gates), dual-gate devices, novel isolation techniques that make features are obtained through sacrificial oxidation steps. Al-
use of Silicon-On-Nothing (SON) or Silicon-On-Insulator though the integration density would have been further in-
(Sal) substrates [1]. In particular, dual-gate technology in creased by means of advanced lithography, the developed pro-
conjunction with the geometry of the device can enhance cess already allows us to produce very high channel densities
the control over the transistor channel. In this sense, further without making use of non standard fabrication steps.
improvements can be achieved with tri-gate, omega-gate or We start by defining a photoresist line on a p-type (N rv 10 15 )
Gate All-Around technologies (GAA) [2]. silicon bulk wafer (see Fig. 1.a). Then a DRIE technique
Recent works explored the vertical stacking of SiNWs as (also called Bosch process) is performed. This technique, that
channels for FET devices [3], [4]. The vertically stacked SiNWs alternates a plasma etching with a passivation step, has been
represent channels of the same SiNW FET, whose electrostactic optimized to produce a scalloped trench in silicon with high
control can be enhanched by using a GAA configuration [5]. reproducibility. Etching time, passivation time and plasma
In addition, SiNW FETs can also be used to build new logic platen power have been optimized in order to enhance the
architectures [6], [7] or as ultimate memory architectures for scalloping effect. The application of the DRIE technique gives
Ultra-Large-Silicon-Integration (ULSI) [8], [9]. a trench like the one depicted in Fig. 1.b. The flexibility of the
In this work we discuss novel and promising fabrication process allows us to change the number of scallops easily. After
method for vertically-stacked SiNW FETs with different num- a wet oxidation step (see Fig. 1.c) vertically stacked SiNWs
ber of channels on bulk Si wafers. The reported method has are formed. Then the cavities produced by the Bosch process
also been applied to fabricate single channel devices that are filled with photoresist. After a combination of chemical
demonstrate excellent reproducible performance. mechanical polishing (CMP) and BHF dip, the wet oxide is re-
moved around the NWs (see Fig. 1.f). The oxide at the bottom
II. RELATED WORK of the cavity is left to isolate the substrate from the successive
Recently, a multichannel structure with GAA configuration processes. The vertical structure obtained is then oxidized to
has been proposed as a candidate for high-performance devices. produce a high quality dry oxide (20 nm thick, see Fig. 1.g)
Its implementation has the advantage of enhanced on-current as gate dielectric. Then between 200 nm and 500 nm of Low
(ION) along with low leakage as well as a small footprint for Pressure Chemical Vapour Deposition (LPCVD) polysilicon is
multi-finger (multi-channel) devices [10], [4]. The fabrication deposited (Fig. 1.h). The polysilicon gate is patterned by means
process described in [10], [4] is based on creating epitaxial layers of a combination of isotropic and anisotropic recipes (see Fig.
to alternate Si and SiGe layers one on top of each other. A 1.i). A final field oxide isolation and Al or Cr/NiCr patterning
vertical trench is etched in the grown structure. A successive make the external electrical connections.

978-1-4244-4353-6/09/$25.00 ©2009 IEEE

A SOl wa fer has been used to fabricate demonstrator de vices be a pplied in order to refine t he dimensions in a cont rolled
with sin gle cha nne l layer . In this case we patterned Cr/ NiC r manner. For instance, it has been demonstrated that the use
throu gh a lift-off t echnique t o form source and drain. An of self-limiting oxidation is capable of producin g channe ls with
advantage for using Ni is that it can eas ily form silicides nanometer d imensions and good cont rolla bility [4], [15]. Surface
with mid -gap work fun ctions at low t emper ature, thus a llowing irregular ities of the sus pe nded NWs can be improved either by
the fabrication of F ETs in few process steps a nd with a low means of a se lf-limiti ng oxid ation or by hydrogen a nnealing step
t her mal budget [13]. However , t he ma in di fferen ce with F ETs [101 . It was found th at t he proposed fabricat ion method cons is-
defined by im pla ntation is t he form ation of Scho ttky Barrier ten tl y produces repeatable a nd very cont ro lla ble d imensions of
(SB) source/ drain thus leading to a dev ice with a mbipolar clearly separate d NW st acks, by op timizing the etc h/ oxidat ion
characte ristic . The ambipolarity refers to the I d s - Vg s elec- cond it ions. A un iform and thin gate oxid e is form ed a round the
trical characte ristic of a tran sistor having both p- and n-typ e suspended NWs by d ry oxidation in a horizontal furnace under
beh aviour [131 . A double step a nnea ling (at 200°C and 400°C, 10 81m 02 flux . By combining isot rop ic and anisot ro pic etc h
respectively) has be en choose n to for m silicided reg ions. This te chniques, polysilicon gat e lengths down to 200 nm (see Fig.
annealing process has been seen as good choice in t erms of 3.a) were pr oduced using 111m lithography. It ca n be seen that
I o N / I OF F ratio improvemen t [14]. Aft er the annealing step s, the the polysili con ga te complete ly surrounds the suspended NW
unreacted Cr / NiC r parts were removed in wet et chant . F inally segment without a ny gaps, and t hat the silicon NW is covered
a 1 J.Lm t hick layer of Al has be en patterned after via opening by a 20nm thick gate oxide (Fig. 3.b) . The proposed GAA
on t he field oxide. device fabrication technique has a lso been succesfu lly applied
for NW stacks with 3 susp ended cha nnels (Fig. 4) . Fig. 4.a
shows a structure with two parallel polysilicon gates, and Fi g.
4.b shows the cross-sec t ion of the st ruct ure wh ere individual
wires and the sur round ing pol ysilicon ga te ar e clearly visible.
Note t hat the cross-section of each susp ended NW (with t he
exception of t he t op wire) has a well-d efined rhombic sh ape
t hat is dict ated by the successive etching/oxid ation steps used
a) b) c) to produce t he wire stacks. The top wire has a t riangula r
profil e that is a lso defined by the process. Schottky-barrier (SB)
SiNW FETs demonstrator devices in GAA configurati on have
a lso been fabricated su ccessfully on SOl , and shown in F ig. 5.
In this particul ar example, the sus pe nded NW segm ent ha s a
t rapezoidal cross-section.

f)

g) i) Fig. 2 . a) Vertically stacked SiNWs in array configuration afte r oxide

••
removal. The nanowires are free and sligt hly bent due to residual
st ress. In thi s sample the number of vertically stacked nanowires
D Silicon SiO2 amounts to 12 . b) Anoth er ar ray with 3 vertically stacked SiNW
channels.
• Photoresist Polysilicon
Fig. 1. Pro cess flow of vertically stacked Si-NW FET . a) A
photoresist line is defined on t he Si wafer. b) A Bosch process is
performed to produce a scalloped tre nch. c) Wet oxidation . d) A
5 J.Lm t hick photoresist is spin-coated in order to fill t he cavities
formed around the t rench. e) T he oxide removal step free th e SiNWs
withouth removing the oxide at th e bottom of the cave. f) SiNWs are
vertically stacked and electrica lly isolated from t he substrate. g) A
high quality dry oxide is formed. h) LPCVD polysilicon deposition.
i) Gate patterning

IV. DI SC USSIO N ON T HE FAB R IC ATED STRUCT URES

T hree dimensional SiNW FET arrays have been fabricated in Fig. 3. a) Single nanowire surr ounded by 500 nm thi ck polysilicon
vertical stacks with the number of channe ls var ying between gate ; Lg ~ 200 nm. b) Gate stack cross-section showing t he Si core
1 and 12 (see Fig. 2). Initially, the formed SiNWs have diam- surrounded by 20 nm gate oxide and polysilicon.
et ers ranging from 70 nm to 200 nm , several t echniques can
 l
~ 10-' ~ \
Iss - 70mV/dec ]

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o
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0/1
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~ 10 -
10
~: o
0: o
o
~ Iss- 250mVldcc , 0
~ 0
, 0
~
Q)
,ks>;
~

10- 1J! -_ _~_ _-:-_ _---: -:--_ _-:

-3 -2 -I 0 2
V [V )
gs

Fig. 6 . Devi ce A : Id s - Vg s cur ve for Vd s = 1 V . T he ob served

a mb ip ola rity is typical for the met allic source and d rain MOSFETs.
Note t he very high su bth res ho ld slopes in bo th modes.

r" ...
0.5 ::~
E::l : ".~

(;f
.-:l~--·~"-~~-S=-O.-5-rY-,
0
:;:
~
- 0.5
- ""
oIl.~...1/
Fig. 4. a ) Long nanowi re channels with two parallel gate const ruc-
t ion . b) Gat e st ac k crossection showing t hree Si NW chan ne ls. - I
l---,li.{b - YgS= I LY I
YgS= 1.5 [VJ

~
A
~ PO IYSi v Vgs= 2 LVJ
-4
,
-2
"
0 2
-4
Vds [VI
-K
1.5 x 10

0.5

Fig. 5. a) Single GAA-NW device with polysilicon gate. b) Gate

stack cross-section a nd highlight on diffe rent stack m aterials .

V. ELECTRI CAL M EAS UREM ENTS

The measured elect rica l performance of two SB SiNW FET , ,' -_ ......'--_-,---"---<J
devic es with single SiNW cha nnel in the stack ar e reported in -4 -2 o 2
V [V]
the following . Each NW channel have 5 urn. gate lengt h an d ds
an effective width of 930 nm. Since the NW cross-section is
Fig. 7. Device A : Id s - Vd s cur ves showing neg a t ive differ ential
t ra pe zoida l, t he effect ive chann el wid th is the perimeter of the resist an ce when the ch annel is a t the inve rsion: a) for Vg s ~ O V
NW . The devic es (see Fig . 6) show an ambipolar behaviour chan ne l in inv ersion mode for positive Vd s and in accumulation mode
with good performance of both p- a nd n- branches . Tab le I for negative Vd s . b) For V gs :::;0 V the chan nel is in inversion mode
reports the device (device A) pa rameters demonstrating device for negative Vd s a nd in accumulation mode wh en Vd s is po sitive.
4
ambipolarity, fO N I f O F F ratio :0:: 10 a nd a subthreshold slope
(SS) lower than 70 mV I dee for the p-type portion of the curves TABLE I
(Vg s > Vt~+ for h +) , and around 250mV I dee for the n-type part D EVICE A : SB SINW F ET PARA METERS .
(Vg s < vtf for e-) . The f d s - Vd s curves have been measured for
positive Vgs (Fig. 7.a) and negative Vg s (Fig. 7.b) . The devic e
ON
IOFF vtt or V;h SS ION
h+
ION
behavior in the "triode" region indicates very distinct gate [V ] [ :re~] [ :~] [ :~ ]
control over the drain current . The plots also show a Negative
Differential Resistance (NDR) region wh en the channe l is in I h -r 2900 - 2 < 70 12.5 -

inversion mode. I e 31000 1 250 - 2

 A par t ially gated device (source and d rai n have b een de- VI. CONCLUSIO NS
signed 111m far away from t he gated channe l) sho ws a mbipolar High channel density SiNW GAA F ETs have been fab ricated
behaviour (see Fig . 8) . T he ext racted paramet ers for t his devic e by me ans of a DRIE t echnique for the first time. T he same
(device B) are reported in Tab le II. T he high Vgs requ ired low cost to p-do wn approac h has been succesfully deployed
for the onset of cond uc ti on is believed to be du e to t he non to fa bricat e vertical SiNW stacks with d ifferent nu mber of
controlled porti on of the channel. This behaviour is con firmed SiNW channe ls; i.e. t he number of channe ls composing the
in [161. Moreover, in [16] the poss ibility of making the device vertical stack could b e eas ily t uned from 1 to 12. Moreover ,
unipolar by using a du a l gates was d iscusse d as well. A de- t he process can be eas ily adopte d for d ifferent su bstrates (b ulk
pend ency of t he IO F F on t he applied Vd s is found (see F ig. 9). or SOl wafers) without any add it ional complexity. F inally, SB
SiNW devices fabricat ed with goo d repeatab ility show exce llen t
10-6 perfo rmance (t he measur ed SS < 70 mV I dec is close t o t he op-
ti ma l value for SiNW devic es for room t em perature op eration)
making the approac h suitable for further invest igat ions .

v
v
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0 2 3 4 5 6 8

F ig. 9. De vice B : IO F F for holes (p -t ype port ion of t he I d s -

Vgs curve) a nd electrons (n -t ype po rtion of t he Ids - Vgs cur ve)
cond uc ti on at d iffer en t Vd s .