Computer Science & Engineering II B.Tech. - II Semester: Department of

Department of
Computer Science & Engineering

II B.Tech. - II Semester
Name of the student

Subject Name Computer Organization
Unit No. 4
Roll No.
Section
Kallam Haranadhareddy Institute of Technology

NH-5, Chowdavaram, Guntur-522 019
Approved by AICTE, New Delhi; Affiliated to JNTUK, Kakinada
Accredited by NBA, NAAC with ‘A’ Grade & An ISO 9001:2015 Certified Institution
Computer Organization -R16 UNIT-4
UNIT–IV
INPUT/OUTPUT ORGANIZATION: Accessing I/O Devices, Interrupts: Interrupt Hardware,
Enabling and Disabling Interrupts, Handling Multiple Devices, Direct Memory Access, and Buses:
Synchronous Bus, Asynchronous Bus, Interface Circuits, Standard I/O Interface: Peripheral Component
Interconnect (PCI) Bus, Universal Serial Bus (USB)
PERIPHERAL DEVICES:
Input or output devices that are connected to computer are called peripheral devices. These devices are
designed to read information into or out of the memory unit upon command from the CPU and are
considered to be the part of computer system. These devices are also called as peripherals.
For example: Keyboards, display units and printers are common peripheral devices.
Types of peripherals:
There are three types of peripherals:
1. Input peripherals: Allows user input, from the outside world to the computer.
Example: Keyboard, Mouse etc.
2. Output peripherals: Allows output information, from the computer to the outside world.
Example: Printer, Monitor etc
3. Input-Output peripherals: Allows both input (from outside world to computer) as well as, output
(from computer to the outside world).
Example: Touch screen etc.
ACCESSING I/O-DEVICES:
 Multiple I/O devices can be connected to the processor and the memory using a single bus
structure. (Figure 7.1).
 Each I/O device is assigned a unique set of address.

 Bus consists of 3 sets of lines to carry address, data & control signals.
 To access an I/O device, processor places an address on address-lines. The particular device
recognizes the address, and responds to the control signals.
 The processor requests either a read or write-operation using control lines.
 The requested-data are transferred over the data-lines.
INPUT-OUTPUT INTERFACE:
 Each peripheral device has associated interface unit with it.
Kallam Haranadhareddy Institute of Technology Page 1

 Interface units are special hardware components which acts as an interface between processor
and peripherals to manage all input and output transfers.
 I/O Interface is used to connect I/O device to the bus.
 I/O Interface circuit consists of Address decoder, control circuit, and data and status registers.
 Address decoder decodes the address placed on the address lines thus enabling the device to
recognize its address.

 Data register holds the data being transferred to or from the processor. It includes 2 buffer
registers
DATAIN Input buffer associated with keyboard.
DATAOUT Output data buffer of a display/printer.
 Status register holds information necessary for the operation of the I/O device. It includes 2
status flags
SIN provides status information associated with keyboard.
SIN=1, when a character is entered at keyboard.
SIN=0, when character is transferred to the processor from DATAIN.
SOUT provides status information of a display/printer.
SOUT=1, when display is ready to receive a character.
SOUT=0, when character is transferred by the processor to DATAOUT.
 Data and status registers are connected to the data lines, and have unique addresses.
 I/O interface circuit coordinates I/O transfers.
I/O INTERFACING TECHNIQUES:

I/O interfacing techniques are mechanisms used for communicating buses with memory and I/O
(interfacing i/o-devices).
There are 2 ways to deal with I/O-devices:
1. Memory-mapped I/O &
2. I/O-mapped I/O.
1. Memory-Mapped I/O:
 This technique uses one common bus for both memory and I/O. (1 data lines, 1 address lines, 1
control lines)
 Memory and I/O-devices share a common address-space.
 Same set of read and write control lines are used for both memory transfer and I/O transfer.
 Any data-transfer instruction (like Move, Load) can be used to exchange information.
For example,
Move DATAIN, R0;
This instruction sends the contents of location DATAIN to register R0.
Here, DATAIN is address of the input-buffer of the keyboard.
2. I/O-Mapped I/O:
 This technique uses one common bus for both memory and I/O but separate control lines for
each. (1 data lines, 1 address lines, 2 control lines)
 Memory and I/O address-spaces are different.
 Separate read and write control lines are used for memory transfer and I/O transfer.
Memory READ and Memory WRITE
I/O READ and I/O WRITE
 Special instructions named IN and OUT are used for data-transfer.
 The IN instruction is used to move data from an I/O port into the accumulator. The OUT
instruction is used to move data from the accumulator to an I/O port.
For example,
IN AL,19H;
Advantage of separate I/O space: I/O-devices deal with fewer address-lines.
MODES OF TRANSFER:
Data Transfer to and from peripherals can be handled in 3modes. They are
1. Program Controlled I/O
2. Interrupt- Initiated I/O
3. Direct Memory Access (DMA)
1. PROGRAM CONTROLLED I/O:

 I/O operations mean data transfer between I/O and memory or I/O and processor.
 If I/O operations are completely controlled by processor, then that mode of transfer is called as
Program Controlled I/O.
 When the processor issues a command to the I/O module, it must wait until the I/O operation is
complete i.e., until the I/O unit indicates that it is ready for data transfer.
 While waiting, processor stays in a program loop and repeatedly checks status of I/O module. This
process is known as polling.
 The processor wastes time in checking status of device before actual data-transfer takes place.
Wasting the processor execution time in this manner can be avoided by using the concept of
interrupts.
Example:
 A program is needed to perform the task of reading the characters produced by the keyboard,
storing these characters in the memory, and sending them to the display.
 The program uses the program-controlled I/O approach described above to read, store, and
display a line of characters typed at the keyboard. As the characters are read in, one by one, they
are stored in the memory and then echoed back to the display. The program finishes when the
carriage return character, CR (ASCII code is 0D hex), is encountered and sends a Line Feed
character (ASCII code is 0A hex) move cursor one line down on display.
 The address of the first byte location of the memory where the line is to be stored is LINE.
Register R0 is used as a pointer to the memory, and it is initially loaded with the address LINE by
the first instruction in the program. R0 is incremented for each character read and displayed.
Move #LINE, R0
WAITK Testbit #0, STATUS // Test SIN
Branch=0 WAITK //wait for character to be entered
Move DATAIN, R1 //read character
WAITD Testbit #1, STATUS // Test SOUT
Branch=0 WAITD //wait for display to receive character
Move R1,(R0)+ //store character and advance pointer
Compare #$0D, R1 //check if character is CR
Branch≠0 WAITK //if character is not CR, still there are characters to read
Move #$0A, DATAOUT //if no more characters to read, send Line Feed
Drawbacks:
 Program-controlled I/O requires continuous involvement of the processor in the I/O activities.
 Almost all of the execution time for the program is spent in the two wait loops, while the processor
waits for a key to be pressed or for the display to become available.
 As a result, the level of the performance is severely degraded.
2. INTERRUPT I/O:
 Wasting the processor execution time in programmed I/O technique can be avoided by using the
concept of interrupts.
 An interrupt I/O is basically an I/O operation requesting to interrupt the CPU to stop its current
execution and switch to the execution of the I/O operation until its completion. Then, the CPU gets
back on the process during which it was interrupted.
 I/O-device sends an interrupt (INTR) signal to processor whenever it is ready for a data-transfer
operation over interrupt request line (IRQ) on bus.
 Processor responds to interrupt signals by sending an interrupt acknowledge signal(INTA)
informing I/O that its request has been recognized and stores the return address from the
program counter (PC) into the memory stack and then the control branches to a interrupt service
routine (ISR).
 Interrupt Service Routine (ISR) is the routine executed in response to an interrupt request.
 After completion of executing interrupt routine CPU returns to previous program and continue
what it was doing before.
 The delay between the time an interrupt is received and start of interrupt service routine is called
as “interrupt latency”. Before starting execution of Interrupt Service Routine (ISR), status and
data registers must be saved. This information is restored to continue original program execution.
Thus, saving registers increases interrupt latency.
 In order to reduce latency, most processors save only minimal amount of information. If there is
any additional information that must be saved, it can be saved explicitly by program instructions
at beginning of ISR.

TRANSFER OF CONTROL BETWEEN PROGRAMS THROUGH INTERRUPTS:
 Consider a program consists of 2 routines COMPUTE and DISPLAY. COMPUTE routine

performs some computations and produces n lines of output. DISPLAY routine prints the output
one line at a time.
 Assume that an interrupt request arrives during execution of instruction i.
 The processor first completes the execution of instruction i.
 When an interrupt occurs, processor informs device that its request has been recognized by
sending INTA signal.
 Then the current content of PC is put in temporary storage location and updates the PC with the
address of the first instruction of the ISR (display routine).
 After the execution of ISR(display routine), the processor has to come back to instruction i+1.
 Therefore, a “return” at the end of ISR reloads the PC from that temporary storage location.
 This causes the execution to resume at instruction i+1.
 The task of saving and restoring the information can be done automatically by the processor.
 The processor saves only the contents of PC & Status register.
 Saving registers also increases the Interrupt Latency.
 Interrupt Latency is a delay between
→ time an interrupt-request is received and
→ start of the execution of the ISR.
 Generally, the long interrupt latency in unacceptable.
INTERRUPT HARDWARE:
 An I/O device requests an interrupt by activating a bus line called “interrupt request line”.
 When several devices requests an interrupt, a single interrupt-request (IR) line may be used to
serve those devices.
 All devices are connected to IR line via switches to ground.
 To request an interrupt, a device closes its associated switch.
 Thus, if all interrupt-request (IR) signals INTR1to INTRn are inactive, i.e if all switches are open,
the voltage on the IR line will be equal to Vdd.
 When a device requests an interrupt by closing its switch, the voltage on the line drops to 0. This
causes the interrupt request signal INTR received by the processor to go to 1.
 The value of INTR is the logical OR of the requests from individual devices.
INTR=INTR1+ INTR2+ +INTRn

 The complement form of INTR is used as name of the interrupt on common bus line because this
signal is active on low voltage state.
 A special gates known as open-collector or open-drain are used to drive the INTR line.
 The Output of the open collector control is equal to a switch to the ground that is
→ open when gates input is in ”0‟ state and
→ closed when the gates input is in “1‟ state.
 Resistor R is called a Pull-up Resistor because it pulls the line voltage up to the high-voltage state
when the switches are open.
ENABLING & DISABLING INTERRUPTS

 A processor has the ability to enable and disable interruptions as desired.
 The problem of infinite loop occurs due to successive interruptions of active interrupt request
(INTR) signals. i.e., when a device requests an interrupt while processor is providing service to
another interrupt, then processor enters into infinite loop.
 There are 3 mechanisms to solve problem of infinite loop:
1. Processor should ignore the interrupts until execution of ISR has been completed.
 In this case, Interrupt disable instruction will be the first instruction and Interrupt
enable instruction, Return from interrupt instruction will be the last two
instructions.
 Thus, no further interruptions will occur until an Interrupt enable instruction is
executed.
 The processor must guarantee that before further interruptions can occur,
execution of Return from interrupt instruction is completed.
2. Processor should automatically disable interrupts before starting the execution of the ISR.
 In this case, One bit in processor status register (PS) called “interrupt enable”
(IEN) indicates whether interrupts are enabled or disabled.
 When interrupt occurs, IEN=1.
 Before starting ISR, processor saves the contents of PC and processor status
register (PS) on the stack.
 After saving processor clears IEN bit in PS (IEN=0), thus disabling interrupts.
 After execution of Return from interrupt instruction is completed, the contents of
PC are restored and processor sets IEN bit in PS (IEN=1), thus enabling
interrupts.
3. Processor has a special interrupt request (INTR) line for which the interrupt-handling
circuit responds only to leading edge of signal. Such line is called edge-triggered.
 In this case, no need to explicitly disable the interrupts, because the processor will
receive only one request over INTR, regardless of how long the line is activated.
 Sequence of events involved in handling an interrupt-request from a single device:
1. The device raises an interrupt-request.
2. The processor interrupts the program currently being executed.
3. Interrupts are disabled by changing the control bits in the processor status register (PS).
4. The device is informed that its request has been recognized.

5. In response, the device deactivates the interrupt-request signal.
6. The action requested by the interrupt is performed by the interrupt-service routine.
7. Interrupts are enabled and execution of the interrupted program is resumed.
HANDLING MULTIPLE DEVICES

 While handling interrupt requests from multiple devices, the issues concerned are:
 How can the processor recognize the device requesting an interrupt?
 How can the processor obtain the starting address of the appropriate ISR?
 Should a device be allowed to interrupt the processor while another interrupt is
being serviced?
 How should 2 or more simultaneous interrupt-requests be handled?
 There are 4 approaches to handle multiple devices
1. Polling
2. Vector interrupts
3. Interrupt nesting
4. Daisy Chaining
1. POLLING
 When multiple devices sends an interrupt request, simplest way to identify interrupting-device is to
have ISR poll all devices connected to bus.
 When a request is received over common INTR line, additional information is needed to recognize
the device requesting an interrupt. This Information is available in IRQ bit of status-register.
 When device raises an interrupt, IRQ bit sets to 1(IRQ=1).
 The first device encountered with its IRQ bit set is serviced.
 After servicing first device, next requests may be serviced.
 Advantage: Simple & easy to implement.
 Disadvantage: More time spent polling IRQ bits of all devices connected to bus.
Example:
 DIRQ - Interrupt-request bit for display.

 KIRQ - Interrupt-request bit for keyboard.
 KEN - Keyboard Enable.
 DEN - Display Enable.
 IRQ=1 → when a device raises an interrupt-requests.
2. VECTORED INTERRUPTS
 To reduce time involved in polling process, a device requesting an interrupt identifies itself
directly to processor over bus.
 A vectored interrupt is where the CPU actually knows the address of the Interrupt Service Routine
in advance.
 In this approach, when INTR occurs, if processor is ready to receive interrupt-vector code, it
activates INTA line.
 Then, I/O-device responds by sending its interrupt-vector code & turning off the INTR signal.
 The interrupting device sends its unique vector (special-code) via a data bus and through its I/O
interface to the CPU. The interrupt vector indicates starting-address of ISR ranges from 4 to 8

bits.
 The interrupt vector also includes a new value for the Processor Status Register.
 The CPU loads interrupt-vector into PC & checks an interrupt table in memory, and then executes
appropriate ISR for that device. So the vectored interrupt allows the CPU to be able to know what
ISR to carry out in software (memory).
3. INTERRUPT NESTING
 When an interrupt occurs from one or more devices simultaneously, the processor has to decide
which request to be serviced first. This can be done using interrupt priorities.
 Nesting interrupt is allowed, only when a high priority device interrupts a low priority device, but
not vice versa.
 In nested interrupt, a higher priority interrupt must be serviced before the current ISR.
 When multiple interrupt request lines are used to interrupt and priorities are assigned to these
lines, the interrupt received in a line of low priority will not be served if an interrupt routine is
running for a device high priority. After completion of the high-priority devices interrupt service
routine, the processor will meet the demand of low priority interrupt devices.
 A multiple-priority scheme is implemented by using separate INTR & INTA lines for each device.
 Each INTR line is assigned a different priority-level.
 Priority-level of processor is the priority of program that is currently being executed.
 Processor accepts interrupts only from devices that have higher-priority than its own.
 At the time of execution of ISR for some device, priority of processor is raised to that of the device.
 Thus, interrupts from devices at the same level of priority or lower are disabled.
 Interrupt requests received over these lines are sent to a priority arbitration circuit in the
processor.
 Privileged Instruction
 Processor's priority is encoded in a few bits of PS word. (PS Processor-Status).
 Encoded-bits can be changed by Privileged Instructions that write into PS.
 Privileged-instructions can be executed only while processor is running in Supervisor
Mode.
 Processor is in supervisor-mode only when executing operating-system routines.
 Privileged Exception
 Before executing application programs, Processor switches from supervisor-mode to user
mode.
 User program cannot
→ accidently or intentionally change the priority of the processor &
→ disrupt the system-operation.
 An attempt to execute a privileged-instruction while in user-mode leads to a Privileged
Exception.

4. SIMULTANEOUS REQUESTS (DAISY CHAINING)
 The processor must have some mechanisms to decide which request to service when simultaneous
requests arrive.
 The priority can be determined using 3 schemes.
1. Polling
2. Vectored interrupts
3. Daisy chaining
 Polling the status registers of devices is simplest mechanism and priority is determined by the
order in which devices are polled.
 When vectored interrupts are used, only one device is selected to send its interrupt vector code.
 In interrupt nesting, only high priority device interrupting a low priority device is allowed.
 Most commonly used scheme is Daisy Chaining priority interrupt.
 It consists of a serial connection of all the devices that requests an interrupt. The device with
highest priority is placed in first position is followed by next lower priority devices upto the device
with lowest priority placed last in the chain.
 INTR line is common to all devices.
 INTA line is connected in a daisy-chain fashion. INTA signal propagates serially through devices.
 When several devices raise an interrupt-request, INTR line is activated and Processor responds by
setting INTA line to 1. This signal is received by device 1.
 Device-1 passes signal on to device 2 only if it does not require any service.
 If device-1 requires service, then the device-1
→ blocks INTA signal &
→ proceeds to put its identifying-code on data-lines.
 Advantage: It requires fewer wires than the individual connections.
 Arrangement of Priority Groups
→When I/O devices were organized into a priority structure, each device had its own interrupt-
request and interrupt-acknowledge line.
→When I/O devices were organized in a daisy chain fashion, the devices shared a common
interrupt-request line, and the interrupt-acknowledge propagated through the devices.
→Here, the devices are organized in groups by combining priority structure and daisy chaining
→each group is connected at a different priority level. Within a group, devices are connected in a
daisy chain

3. DIRECT MEMORY ACCESS (DMA):
 DMA transfers a block of data directly between an I/O device and main memory without
continuous involvement by the processor.
 DMA is a technique used for high speed I/O-device.
DMA CONTROLLER:
 It is a control circuit used to perform data transfers and allows peripheral device to directly
access memory.
 When accessing main memory, it performs the functions that would normally be carried out by
processor.
 While a DMA transfer is taking place, the processor can be used to execute another program.
 Block diagram of DMA Controller:
 CPU communicates with DMA Controller using data bus and control lines.
 DMA interface has three registers :
1. Address register - used for storing starting-address.
2. Word count register - used for storing word-count.
3. Control register - contains status- & control-flags.
 Address bus buffer stores the address of next word to be transferred. After each word is
transferred, address register is automatically incremented or decremented.
 The R/𝑊̅ bit determines direction of transfer.
̅ =1, controller performs a read-operation (i.e. it transfers data from memory to I/O),
 If R/𝑊
Otherwise, controller performs a write-operation (i.e. it transfers data from I/O to
memory).
 If Done=1, the controller
→ has completed transferring a block of data and
→ is ready to receive another command. (IE Interrupt Enable).
 If IE=1, controller raises an interrupt after it has completed transferring a block of data.
 If IRQ=1, controller requests an interrupt.
 Requests by DMA devices for using the bus are always given higher priority than
processor requests.

 BASIC operation of DMA Controller is as follows:
 When I/O device sends a DMA request, DMA controller request the CPU to release the
control of buses by enabling BR( Bus Request) control signal.
 In response to BR signal, CPU grant control of buses by enabling BG (Bus Grant) control
signal sending the following information.
 Starting address where data is available or data to be stored.
 No. of words in the block to read or write
 Direction of transfer (memory to I/O (read) or I/O to memory (write))
 Then DMA controller takes control of buses and enables R/𝑊 ̅ signal and sends DMA
Acknowledgement signal to I/O device.
 When I/O device receives DMA Acknowledgement signal, I/O device puts data on bus
(write) or receives data from bus (read).
 After data transfer is completed, DMA controller disables BR signal and sends interrupt
signal to CPU.
 then CPU disables BG signal and takes control of buses and return to its normal
operation.
TWO CHANNEL DMA CONTROLLER:

 A DMA controller may have more than one channel. In this case, each channel has a request and
acknowledges pair of control signals which are connected to separate peripheral devices. Each
channel also has its own address register and word count register within the DMA controller. A
priority among the channels may be established so that channels with high priority are serviced
before channels with lower priority.
 DMA controller connects a high-speed network to the computer bus.

 Disk controller, which controls two disks also has DMA capability. It provides two DMA
channels.
 It can perform two independent DMA operations, as if each disk has its own DMA controller. The
registers to store the memory address, word count and status and control information are
duplicated.
MODES OF DMA TRANSFER:

 There are 2 ways in which the DMA operation can be carried out
1. Cycle stealing (or) Single transfer mode.
2. Block transfer mode (or) burst transfer mode
1. Cycle stealing mode:
 In this mode of transfer, DMA controller transfers only one byte or word at a time.
 After each transfer, DMA controller must give control of buses to the CPU.
 i.e., Processor delays its operation for one memory-access cycle to allow DMA transfer..
 Thus, DMA controller is said to "steal" memory cycles from processor.
 Hence, this technique is usually called Cycle Stealing.
2. Burst Transfer mode:
 DMA controller is given exclusive access to main-memory to transfer a block of data without any
interruption. This is known as Block Mode (or burst mode).

BUS ARBITRATION:
 A conflict may arise if both the processor and a DMA controller (or) two DMA controllers try to
use the bus at the same time to access the main memory. To resolve these conflicts, an arbitration
procedure is used.
 The device that is allowed to initiate data transfers on the bus at any given time is called the bus
master. In a computer system there may be more than one bus master such as processor, DMA
controller etc. They share the system bus.
 When current master relinquishes control of the bus, another bus master can acquire the control
of the bus.
 “Bus Arbitration” is the process by which the next device to become the bus master is selected
and bus mastership is transferred to it. The selection of bus master is usually done on the priority
basis.
 There are two approaches to bus arbitration:
1. Centralized Arbitration
2. Distributed Arbitration.
1. CENTRALIZED ARBITRATION
 In centralized bus arbitration, a single bus arbiter performs the required arbitration. The bus
arbiter may be the processor or a separate controller connected to the bus.
 Bus arbiter may be the processor or a separate unit connected to the bus.
 Normally, the processor is the bus master, unless it grants bus membership to one of the DMA
controllers.
 DMA controller requests the control of the bus by asserting the Bus Request (BR) line.
 In response, the processor activates the Bus-Grant1 (BG1) line, indicating that the controller may
use the bus when it is free.
 BG1 signal is connected to all DMA controllers in a daisy chain fashion.
 If DMA Controller1 is requesting bus, it blocks the propagation of the bus grant, otherwise it
passes bus grant downstream by enabling BG2.
 The current bus master blocks the propagation of the bus grant signal, by activating the bus busy
line BBSY and gains control of the bus. Therefore any other requesting controller will not receive
the grant signal and hence cannot get the bus access.
 BBSY signal is 0, it indicates that the bus is busy. When BBSY becomes 1, the DMA controller
which asserted BR can acquire control of the bus.
Example:
Here DMA Controller2 requests and acquires bus mastership.

2. DISTRIBUTED ARBITRATION
 In distributed arbitration, all devices waiting to use the bus participate in the selection of the next
bus master.
 In this scheme each device on the bus is assigned a 4-bit identification number.
 When one or more devices request for the control of bus, they assert the start-arbitration signal
and place their 4-bit ID numbers on arbitration lines, ARB0 through ARB3.
 These four arbitration lines are all open-collector. Therefore, more than one device can place
their 4-bit ID number to indicate that they need to control of bus.
 The pattern that appears on the arbitration lines is the logical-OR of all the 4-bit device IDs
placed on the arbitration lines. i.e., If one device puts 1 on the bus line and another device puts 0
on the same bus line, the bus line status will be 0.
 Each device compares the pattern that appears on the arbitration lines to its own ID, starting with
MSB.
 If it detects a difference, it transmits 0s on the arbitration lines for that and all lower bit positions.
 If pattern matches, then that particular device can use the bus.
 The decentralized arbitration offers high reliability because operation of the bus is not dependent
on any single device.
Example:
 Consider that two devices A and B, having ID number 5 and 6, respectively are requesting the use
of the bus.
 Device A puts the bit pattern 0101, and device B puts the bit pattern 0110 on arbitration lines.
 Pattern that appears on the arbitration lines is the logical OR of the patterns: With this
combination Pattern 0111 appears on the arbitration lines.
 Each device compares the code formed on the arbitration line to its own ID, starting from the
most significant bit. If it finds the difference at any bit position, it disables its drives at that bit
position and for all lower-order bits by placing a 0.
 Device A compares its ID 5 with a pattern 0101 to pattern 0111.
 It detects a difference at bit position 0 on line ARB2 and hence it disables its drives on line ARB2,
ARB1 and ARB0, as a result, it transmits a pattern 0100 on the arbitration lines.
 Now, the pattern that appears on the arbitration lines is the logical-OR of 0100 and 0110, which
is 0110.
 This pattern is the same as the device ID of B, and hence B has won the arbitration.
BUS:
 A bus protocol is the set of rules that govern the behavior of various devices connected to the bus,
as to when to place information on the bus, when to assert control signals, etc.
 Bus consists of data lines, address lines and control lines.
 Control signals specify:
 Whether it is a read or a write operation.
 Timing information to indicate when the processor and I/O devices may place data or
receive data from the bus.
 Timing of data transfers over a bus can be specified in 2ways.
 Synchronous,
 Asynchronous.
1. SYNCHRONOUS BUS:
 The device that initiates the data transfer on the bus by issuing read or write control signals is
called as a master. The device that is being addressed by the master is called a slave or a target.
 In this approach , a common clock line is used to derive timing information.
 Equally spaced clock pulses (equal time intervals) constitutes a “bus cycle”.
Sequence of events during READ operation using single clock cycle on a synchronous bus:
 In case of a READ operation, the master places the address and commands on the bus at time t0.
 Once the master places the device address and command on the bus, it takes time for this
information to propagate to the devices: This time depends on the physical and electrical
characteristics of the bus.
 Also, all the devices have to be given enough time to decode the address and control signals, so
that the addressed slave can place data on the bus.
 Width of the pulse t1 - t0 depends on:
 Maximum propagation delay between two devices connected to the bus.
 Time taken by all the devices to decode the address and control signals,
 The addressed slave responds by placing data on data lines at time t1.
 At the end of the clock cycle, at time t2, the master strobes the data on the data lines into its input
buffer if it’s a Read operation.
Sequence of events during READ operation with a detailed timing diagram on a synchronous bus:

 It shows 2 views. One as seen by the master and the other as seen by the slave.
 the master places the address and commands on the bus at time t0.
 Signals do not appear on the bus as soon as they are placed on the bus, due to the propagation
delay tAM in the interface circuits.
 Signals reach the devices after a propagation delay tAS which depends on the characteristics of the
bus.
 The slave decodes the address and at time t1sends the data.
 Data do not appear on the bus until tDS and arrives master at tDM.
 At t2 master loads the data into its input buffer. The ti e t2- tDM is setup time for master input
buffer.
 Data must remain on the bus for some time after t2 equal to the hold time of the buffer.
Sequence of events during WRITE operation using single clock cycle on a synchronous bus:
 In case of a Write operation, the master places the data on the bus along with the address and
commands at time t0.
 The slave strobes the data into its input buffer at time t2.
 “Strobe” means to capture the values of the data and store them into a buffer.
 When data are to be loaded into a storage buffer register, the data should be available for a
period longer than the setup time of the device.
 Width of the pulse t2 - t1 should be longer than:
 Maximum propagation time of the bus plus
 Set up time of the input buffer register of the master.
Limitations of single cycle data transfer on a synchronous bus:

 Data transfer has to be completed within one clock cycle.
 Clock period t2 - t0 must be such that the longest propagation delay on the bus and the slowest
device interface must be accommodated.
 Forces all the devices to operate at the speed of the slowest device.
 Processor don’t know whether the device has actually responded or not. It just assumes that the
data are available at t2 in case of a Read operation, and data is read by the device in case of a
Write operation.
 If device does not respond due to some malfunction, the error will not be detected.
Multi cycle data transfer on a synchronous bus:

 To overcome limitations of single cycle data transfer, most buses have control signals to represent
a response from the slave.
 Control signals serve two purposes:
 Inform the master that the slave has recognized the address, and is ready to participate in a
data transfer operation.
 Enable to adjust the duration of the data transfer operation based on the speed of the
participating slaves.
 High-frequency bus clock is used such that data transfer spans several clock cycles instead of just
one clock cycle as in the earlier case.
 Sequence of events during READ operation using multiple clock cycles on a synchronous bus:
 During clock cycle 1,the master places the address and commands on the bus at time t0.
 The addressed slave decodes the address and control signals, and decides to place data on the
bus.
 After some delay, at clock cycle3 slave places data on data lines and asserts a control signal
slave-ready.
 Slave-ready signal is an acknowledgement from the slave to the master to confirm that the valid
data has been sent. Depending on when the slave-ready signal is asserted, the duration of the data
transfer can change.
 The master, on seeing this signal strobes data into its input buffer at the end of clock cycle 3.
 The master waits for slave-ready signal for a predefined maximum number of clock cycles and if
slave does not respond in this time, master aborts the operation resulting in incorrect address or
device malfunction.
2. ASYNCHRONOUS BUS:
 Data transfers on the bus is controlled by a handshake between the master and the slave.
 Common clock in the synchronous bus case is replaced by two timing control lines:
 Master-ready,
 Slave-ready.
 Master-ready signal is asserted by the master to indicate to the slave that it is ready to participate
in a data transfer.

 Slave-ready signal is asserted by the slave in response to the master-ready from the master, and it
indicates to the master that the slave is ready to participate in a data transfer.
Data transfer during input (READ) operation using the handshake protocol:
 Master places the address and command information on the bus.
 Asserts the Master-ready signal to indicate to the slaves that the address and command
information has been placed on the bus.
 All devices on the bus decode the address.
 Address slave performs the required operation, and informs the processor it has done so by
asserting the Slave-ready signal.
 Master removes all the signals from the bus, once Slave-ready is asserted.
 If the operation is a Read operation, Master also strobes the data into its input buffer.
 t0 - Master places the address and command information on the bus.

 t1 - Master asserts the Master-ready signal. Master-ready signal is asserted at t1 instead of t0
 t2 - Addressed slave places the data on the bus and asserts the Slave-ready signal.
 t3 - Slave-ready signal arrives at the master.
 t4 - Master removes the address and command information.
 t5 - Slave receives the transition of the Master-ready signal from 1 to 0. It removes the data and
the Slave-ready signal from the bus.
Data transfer during output (WRITE) operation using the handshake protocol:
 Master places the address and command information along with data on the bus.
 Asserts the Master-ready signal to indicate to the slaves that the address and command
information has been placed on the bus.
 All devices on the bus decode the address.
 Addressed slave strobes the data into its output buffer, and informs the processor it has done so by
asserting the Slave-ready signal.
 Master removes all the signals from the bus, once Slave-ready is asserted.
 Advantages of asynchronous bus:

 Eliminates the need for synchronization between the sender and the receiver.

 Can accommodate varying delays automatically, using the Slave-ready signal.
 Disadvantages of asynchronous bus:
 Data transfer rate with full handshake is limited by two-round trip delays.
 Data transfers using a synchronous bus involves only one round trip delay, and hence a
synchronous bus can achieve faster rates.
INTERFACE CIRCUITS:
 I/O interface consists of the circuitry required to connect an I/O device to a computer bus.
 On one side of the interface which connects to the computer has bus signals for Address, Data
and Control lines.
 Other side of the interface which connects to the I/O device has datapath with its associated
controls to transfer data between the interface and the I/O device.This side is called as a “port”.
 Ports can be classified into two types:
 Parallel port,
 Serial port.
 Parallel port transfers data in the form of a number of bits, normally 8 or 16 to or from the device.
 Serial port transfers and receives data one bit at a time.
 Processor communicates with the bus in the same way, whether it is a parallel port or a serial
port.
 Conversion from the parallel to serial and vice versa takes place inside the interface circuit.
Functionalities of I/O interface:

 Provides a storage buffer for atleast one word of data
 Contains status flags that can be accessed by the processor to determine whether buffer is full(for
input) or empty (output)
 Contains address decoder to recognize the address given by processor.
 Generates appropriate timing signals received by bus control scheme.
 Performs parallel – serial conversion in case of serial port to transfer data between bus and I/O
device.
1. PARALLEL PORT:
Keyboard to Processor Connection:
 Keyboard is connected to a processor using a parallel port.

 Assume interface circuit is connected to a 32-bit Processor that uses memory-mapped I/O and the
asynchronous bus protocol.
 Data transfers are controlled using handshake signals Master-ready signal and Slave-ready
signal.
 On the processor side of the interface we have:
 Data lines.
 Address lines
 Control or R/W line.
 Master-ready signal and
 Slave-ready signal.

 On the keyboard side of the interface:
 Encoder circuit which generates a ASCII code for the key pressed.
 Debouncing circuit which eliminates the effect of a key bounce (a single key stroke may
appear as multiple events to a processor).
 Data lines contain the code for the key.
 Valid line changes from 0 to 1 when the key is pressed. This causes the code to be loaded
into DATAIN and SIN to be set to 1.
 SIN is cleared to 0 when processor reads the contents of DATAIN register.
Input Interface Circuit:
 Output lines of DATAIN are connected to the data lines of the bus by means of 3 state drivers
 Drivers are turned on when the processor issues a read signal and the address selects this
register.
 SIN signal is generated using a status flag circuit.
 It is connected to line D0 of the processor bus using a three-state driver.
 Address decoder selects the input interface based on bits A1 through A31.
 Bit A0 determines whether the status or data register is to be read, when Master-ready is active.
 In response, the processor activates the Slave-ready signal, when either the Read-status or Read-
data is equal to 1, which depends on line A0.
Printer to Processor Connection:

 Printer is connected to a processor using a parallel port.

 Assume interface circuit is connected to a 32-bit Processor that uses memory-mapped I/O and the
asynchronous bus protocol.
 Printer operates under control of handshake signals Valid signal and Idle signal.
 On the processor side of the interface we have:
 Data lines.
 Address lines
 Control or R/W line.
 Master-ready signal and
 Slave-ready signal.
 On the printer side:
 Idle signal line which, the printer asserts when it is ready to accept a character. This causes
the SOUT flag to be set to 1.
 Processor places a new character into a DATAOUT register.
 Valid signal is asserted by the interface circuit when it places a new character on the data
lines.
 In response printer starts printing and negates idle signal, which causes the interface to
deactivate valid signal.
Ouput Interface Circuit:
 Data lines of the processor bus are connected to the DATAOUT register of the interface.
 The status flag SOUT is connected to the data line D1 using a three-state driver.

 The three-state driver is turned on, when the control Read-status line is 1.
 Address decoder selects the output interface using address lines A1 through A31.
 Address line A0 determines whether the data is to be loaded into the DATAOUT register or status
flag is to be read.
 If the Load-data line is 1, then the Valid line is set to 1.
 If the Idle line is 1, then the statusflag SOUT is set to 1.
Combined Input-Ouput Interface Circuit:
 Address bits A2 through A31, that is 30 bits are used to select the overall interface.
 Address bits A1 through A0, that is, 2 bits select one of the three registers, namely, DATAIN,
DATAOUT, and the status register.
 Status register contains the flags SIN and SOUT in bits 0 and 1.
 RS0 and RS1 determines the register being selected.
 Data lines PA0 through PA7 connect the input device to the DATAIN register.
 DATAOUT register connects the data lines on the processor bus to lines PB0 through PB7 which
connect to the output device.
 Separate input and output data lines for connection to an I/O device.
8-bit Parallel Interface Circuit:

 Data lines to I/O device are bidirectional.

 Data lines P7 through P0 can be used for both input, and output.
 In fact, some lines can be used for input & some for output depending on the pattern in the Data
Direction Register (DDR).
 Processor places an 8-bit pattern into a DDR.
 If a given bit position in the DDR is 1, the corresponding data line acts as an output line,
otherwise it acts as an input line.
 C1 and C2 control the interaction between the interface circuit and the I/O devices.
 Ready and Accept lines are the handshake control lines on the processor bus side, and are
connected to Master-ready & Slave-ready.
 Input signal My-address is connected to the output of an address decoder.
 Three register select lines that allow upto 8registers to be selected.
2. SERIAL PORT:
 Serial port is used to connect the processor to I/O devices that require transmission of data one bit
at a time.
 Serial port communicates in a bit-serial fashion on the device side and bit parallel fashion on the
bus side.
 Transformation between the parallel and serial formats is achieved with shift registers that have
parallel access capability.
 Input shift register accepts input one bit at a time from the I/O device.
 Once all the 8 bits are received, the contents of the input shift register are loaded in parallel into
DATAIN register.
 Output data in the DATAOUT register are loaded into the output shift register.
 Bits are shifted out of the output shift register and sent out to the I/O device one bit at a time.
 As soon as data from the input shift reg. are loaded into DATAIN, it can start accepting another 8
bits of data.
 Input shift register and DATAIN registers are both used at input so that the input shift register can
start receiving another set of 8 bits from the input device after loading the contents to DATAIN,
before the processor reads the contents of DATAIN. This is called as double-buffering.

 Serial interfaces require fewer wires, and hence serial transmission is convenient for connecting
devices that are physically distant from the computer.
 Speed of transmission of the data over a serial interface is known as the “bit rate”.
 Bit rate depends on the nature of the devices connected.
 In order to accommodate devices with a range of speeds, a serial interface must be able to use a
range of clock speeds.
 Several standard serial interfaces have been developed such as Universal Asynchronous
Receiver Transmitter (UART) for low-speed serial devices and RS-232-C for connection to
communication links.
STANDARD I/O INTERFACES:

 I/O device is connected to a computer using an interface circuit.
 A practical approach to design a different interface for every combination of an I/O device and a
computer is to develop standard interfaces and protocols.
 A personal computer has:
 A motherboard which houses the processor chip, main memory and some I/O interfaces.
 A few connectors into which additional interfaces can be plugged.
 Processor bus is defined by the signals on the processor chip.
 Devices which require high-speed connection to the processor are connected directly to this
bus.
 Because of electrical reasons only a few devices can be connected directly to the processor bus.
 Motherboard usually provides another bus that can support more devices.
 Processor bus and the other bus (called as expansion bus) are interconnected by a
circuit called “bridge”.
 Devices connected to the expansion bus experience a small delay in data transfers.
 Design of a processor bus is closely tied to the architecture of the processor. No uniform
standard can be defined. Expansion bus however can have uniform standard defined.
 A number of standards have been developed for the expansion bus.

 Three widely used bus standards are
 PCI (Peripheral Component Interconnect)
 SCSI (Small Computer System Interface)
 USB (Universal Serial Bus)
1. PCI BUS:
 Peripheral Component Interconnect
Features of PCI bus:
 Low-cost bus
 Processor independent
 Plug-and-play capability for connecting I/O devices.
Use of PCI bus/ Data transfer on PCI bus:
 Devices connected to PCI bus appear to the processor as if they were connected directly to the
processor bus.
 They are assigned addresses in the memory address space of the processor.
 PCI bridge provides a separate physical connection for the main memory.
 In today’s computers, most memory transfers involve a burst of data rather than just one word. The
PCI is designed primarily to support this mode of operation.
 The bus supports three independent address spaces: memory, I/O, and configuration.
 The configuration space is intended to give the PCI its plug and play capability.
 4- bit command given with the address identifies which of the three spaces is being used in a given
data transfer operation.
 Assume that the master maintains the address information on the bus until data transfer is
completed. But, the address is needed only long enough for the slave to be selected. Thus, the
address is needed on the bus for one clock cycle only, freeing the address lines to be used for
sending data in subsequent clock cycles. The result is a significant cost reduction.
 A master is called an initiator in PCI terminology. The addressed device that responds to read and
write commands is called a target.

READ OPERATION on PCI BUS:
 When an I/O device is connected to a computer, several actions are needed to configure both the
device and the software that communicates with it.
 In Clock cycle1, the processor asserts FRAME # to indicate the beginning of a transaction; it
sends the address on AD lines and command on C/BE # Lines.
 Clock cycle2 is used to turn the AD Bus lines around ; the processor ; The processor removes
the address and disconnects its drives from AD lines.
 The selected target enable its drivers on AD lines and fetches the requested data to be placed on
the bus.
 It asserts DEVSEL # and maintains it in asserted state until the end of the transaction.
 C/BE # is used to send a bus command in clock cycle and it is used for different purpose during
the rest of the transaction.
 During clock cycle 3, the initiator asserts IRDY #, to indicate that it is ready to receive data.
 If the target has data ready to send then it asserts TRDY #. In our eg, the target sends 3 more
words of data in clock cycle 4 to 6.
 The indicator uses FRAME # to indicate the duration of the burst, since it read 4 words, the
initiator negates FRAME # during clock cycle 5.
 After sending the 4th word, the target disconnects its drivers and negates DEVSEL # during
clock cycle 7.

Device Configuration:
 When an I/O device is connected to a computer, several actions are needed to configure both the
device and the software that communicates with it.
 PCI incorporates in each I/O device interface a small configuration ROM memory that stores
information about that device.
 The configuration ROMs of all devices are accessible in the configuration address space. The
PCI initialization software reads these ROMs and determines whether the device is a printer, a
keyboard, an Ethernet interface, or a disk controller. It can further learn about various device
options and characteristics.
 Devices are assigned addresses during the initialization process.
 This means that during the bus configuration operation, devices cannot be accessed based on
their address, as they have not yet been assigned one.
 Hence, the configuration address space uses a different mechanism. Each device has an input
signal called Initialization Device Select, IDSEL#
 Electrical characteristics:
 PCI bus has been defined for operation with either a 5 or 3.3 V power supply
2. SCSI BUS:
 SCSI is an acronym for Small Computer Systems Interface. It is an ANSI standard that has
become one of the leading I/O buses in the computer industry.
 The SCSI bus is a parallel bus, which comes in a number of variants. The oldest and most used is
an 8 bit wide bus, with single-ended signals, carried on 50 wires.
 Devices connected to the SCSI bus are not part of the address space of the processor
 The SCSI bus is connected to the processor bus through a SCSI controller. This controller uses
DMA to transfer data packets from the main memory to the device, or vice versa.
 A controller connected to a SCSI bus is one of two types – an initiator or a target.
 An initiator has the ability to select a particular target and to send commands specifying the
operations to be performed. The disk controller operates as a target. It carries out the
commands it receives from the initiator.
 Assume that processor needs to read block of data from a disk drive and that data are stored in
disk sectors that are not contiguous.
 The processor sends a command to the SCSI controller, which causes the following sequence of
events to take place:
 The SCSI controller, acting as an initiator, contends for control of the bus.
 When the initiator wins the arbitration process, it selects the target controller and hands
over control of the bus to it.
 The target starts an output operation (from initiator to target); in response to this, the
initiator sends a command specifying the required read operation.
 The target, realizing that it first needs to perform a disk seek operation, sends a message
to the initiator indicating that it will temporarily suspend the connection between them.
Then it releases the bus.
 The target controller sends a command to the disk drive to move the read head to the first
sector involved in the requested read operation. Then, it reads the data stored in that
sector and stores them in a data buffer. When it is ready to begin transferring data to the
initiator, the target requests control of the bus. After it wins arbitration, it reselects the
initiator controller, thus restoring the suspended connection.
 The target transfers the contents of the data buffer to the initiator and then suspends the
connection again
 The target controller sends a command to the disk drive to perform another seek
operation. Then, it transfers the contents of the second disk sector to the initiator as
before. At the end of this transfers, the logical connection between the two controllers is
terminated.
 As the initiator controller receives the data, it stores them into the main memory using
the DMA approach.
 The SCSI controller sends as interrupt to the processor to inform it that the requested
operation has been completed
SCSI BUS SIGNALS:
The main phases involved in the operation of the SCSI bus are:
 Arbitration
 Selection
 Information Transfer
 Reselection

Arbitration:
 The bus is free when the -BSY signal is in the inactive (high voltage) state. Any controller can
request the use of the bus while it is in this state. Since two or more controllers may generate
such a request at the same time, an arbitration scheme must be implemented. A controller
requests the bus by asserting the -BSY signal and by asserting its associated data line to identify
itself. Each controller in the bus is assigned a fixed priority, with controller 7 having highest
priority. When -BSY becomes active, all controllers that are requesting the bus examine the data
lines and determine whether a higher priority device is requesting the bus at the same time. The
controller using the highest numbered line realizes that it has won the arbitration.
Selection:
 Having won arbitration, controller 6 continues to assert -BSY and -DB6 (its address). It
indicates that it wishes to select controller 5 by asserting the -SEL and then the -DB5 line. The
selected target controller responds by asserting -BSY. This informs the initiator that the
connection it is requesting has been established, so that it may remove the address information
from data lines. The selection process is now complete, and the target controller is asserting -
BSY.
Information Transfer:
 The information transferred between two controllers may consist of commands from the
initiator to the target, status responses from the target to the initiator, or data being transferred
to or from the I/O device. Handshake signaling is used to control information transfers. The
target asserts -I/O during an input operation (target to initiator) and it asserts -C/D to indicate
that information is a command or status response. At the end of the transfer, the target
controller releases -BSY signal, thus freeing the bus for use by other devices.
Reselection
 When a logical connection is suspended and the target is ready to restore it, the target must first
gain control of the bus. It starts an arbitration cycle, and after winning arbitration, it selects the
initiator. The initiator is now asserting -BSY. The initiator waits for short period after being
selected to make sure that target has asserted -BSY, and then releases the -BSY line. The
connection between the two controllers has now been reestablished, with the target in control of
the bus as required for data transfer to proceed.
3. USB:
 Universal Serial Bus (USB) is a standard interface for connecting peripheral devices to a host
computer. The USB system was originally devised by a group of companies, including Compaq,
Hewlett-Packard, Intel, Lucent, Microsoft, Nortel Networks, and Philips.
 USB was designed to replace the multitude of cables and connectors required to connect
peripheral devices to a host computer. The main goal of USB was to make the addition of
peripheral devices quick and easy. All USB devices share some key characteristics to make this
possible. All USB devices are self-identifying on the bus. All devices are hot-pluggable to allow
for true Plug’n’Play capability. Additionally, some devices can draw power from the USB which
eliminates the need for extra power adapters.

PREVIOUS QUESTIONS
1. Draw the input-output interface for an input device and explain accessing of input-output device.
2. Define interrupt and interrupt service routine.
3. Write about the transfer of control between programs through interrupts.
4. Define interrupt-acknowledge signal and interrupt latency.
5. Write a note on enabling and disabling interrupts.
6. Discuss about interrupt vector.
7. What do you mean by vectored interrupts?
8. Discuss the implementation of nested interrupts to handle multiple devices.
9. Explain the usage of daisy chains and priority in simultaneous interrupt handling.
10. Write a note on DMA.
11. Define DMA and draw the two-channel DMA controller and explain it.
12. What is bus arbitration?
13. Write about two different approaches for bus arbitration.
14. Discuss about Synchronous bus and draw the timing diagram of input transfer of synchronous bus.
15. Explain the importance of handshake control for data transfer in asynchronous bus.
16. Draw and explain input/output interface circuit connecting a keyboard to an asynchronous bus.
17. Discuss about Interface Circuits.
18. List the functionalities of I/O interface. Draw and explain a combined input/output interface circuit.
19. Discuss briefly about peripheral component interconnect (PCI).
20. What is the use of PCI bus in a computer system?
21. Explain typical read operation with various data transfer signals on the PCI bus.
22. What are the main phases involved in the operation of SCSI bus.
23. Discuss briefly about universal serial bus (USB).
24. How to meet device characteristics and addressing objectives by USB? Explain.

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Kallam Haranadhareddy Institute of Technology

 Each I/O device is assigned a unique set of address.

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recognize its address.

I/O INTERFACING TECHNIQUES:

1. PROGRAM CONTROLLED I/O:

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 Consider a program consists of 2 routines COMPUTE and DISPLAY. COMPUTE routine

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ENABLING & DISABLING INTERRUPTS

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HANDLING MULTIPLE DEVICES

 DIRQ - Interrupt-request bit for display.

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TWO CHANNEL DMA CONTROLLER:

 DMA controller connects a high-speed network to the computer bus.

MODES OF DMA TRANSFER:

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Here DMA Controller2 requests and acquires bus mastership.

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Limitations of single cycle data transfer on a synchronous bus:

Multi cycle data transfer on a synchronous bus:

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 t0 - Master places the address and command information on the bus.

 Advantages of asynchronous bus:

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Functionalities of I/O interface:

Keyboard to Processor Connection:

 Keyboard is connected to a processor using a parallel port.

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Input Interface Circuit:

Printer to Processor Connection:

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 Printer is connected to a processor using a parallel port.

Ouput Interface Circuit:

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Combined Input-Ouput Interface Circuit:

8-bit Parallel Interface Circuit:

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 Data lines to I/O device are bidirectional.

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STANDARD I/O INTERFACES:

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READ OPERATION on PCI BUS:

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