74HC4002; 74HCT4002

Dual 4-input NOR gate

Rev. 4 — 17 September 2012 Product data sheet

1. General description
The 74HC4002; 74HCT4002 is a dual 4-input NOR gate. Inputs also include clamp diodes
that enable the use of current limiting resistors to interface inputs to voltages in excess of
VCC.

2. Features and benefits

 Complies with JEDEC standard JESD7A
 Low-power dissipation
 Input levels:
 For 74HC4002: CMOS level
 For 74HCT4002: TTL level
 ESD protection:
 HBM JESD22-A114F exceeds 2000 V
 MM JESD22-A115-A exceeds 200 V
 Multiple package options
 Specified from 40 C to +80 C and from 40 C to +125 C.

3. Ordering information
Table 1. Ordering information
Type number Package
Temperature range Name Description Version
74HC4002N 40 C to +125 C DIP14 plastic dual in-line package; 14 leads (300 mil) SOT27-1
74HCT4002N
74HC4002D 40 C to +125 C SO14 plastic small outline package; 14 leads; body width SOT108-1
74HCT4002D 3.9 mm

74HC4002DB 40 C to +125 C SSOP14 plastic shrink small outline package; 14 leads; body SOT337-1
74HCT4002DB width 5.3 mm

74HC4002PW 40 C to +125 C TSSOP14 plastic thin shrink small outline package; 14 leads; SOT402-1
body width 4.4 mm
NXP Semiconductors 74HC4002; 74HCT4002
Dual 4-input NOR gate

4. Functional diagram

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Fig 1. Functional diagram Fig 2. Logic symbol

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Fig 3. IEC Logic symbol Fig 4. Logic diagram

5. Pinning information

5.1 Pinning

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+&7

<   9&&
+&
$   <
+&7

%   ' <   9&&

$   <
&   &
%   '
'   % &   &
'   %
QF   $
QF   $
*1'   QF *1'   QF

DDD DDD

Fig 5. Pin configuration SOT27-1 and SOT108-1 Fig 6. Pin configuration SOT337-1 and SOT402-1

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Product data sheet Rev. 4 — 17 September 2012 2 of 16

NXP Semiconductors 74HC4002; 74HCT4002
Dual 4-input NOR gate

5.2 Pin description

Table 2. Pin description
Symbol Pin Description
1Y 1 data output
1A, 1B, 1C, 1D 2, 3, 4, 5 data input
n.c. 6, 8 not connected
GND 7 ground (0 V)
2Y 13 data output
2A, 2B, 2C, 2D 9, 10, 11, 12 data input
VCC 14 supply voltage

6. Functional description
Table 3. Function table[1]
Input Output
nA nB nC nD nY
L L L L H
H X X X L
X H X X L
X X H X L
X X X H L

[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care.

7. Limiting values
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
VCC supply voltage 0.5 +7 V
IIK input clamping current VI < 0.5 V or VI > VCC + 0.5 V [1] - 20 mA
IOK output clamping current VO < 0.5 V or VO > VCC + 0.5 V [1] - 20 mA
IO output current 0.5 V < VO < VCC + 0.5 V - 25 mA
ICC supply current - 50 mA
IGND ground current 50 - mA
Tstg storage temperature 65 +150 C
Ptot total power dissipation [2]

DIP14 package - 750 mW

SO14, and (T)SSOP14 - 500 mW
packages

[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For DIP14 package: Ptot derates linearly with 12 mW/K above 70 C.
For SO14 package: Ptot derates linearly with 8 mW/K above 70 C.
For (T)SSOP14 packages: Ptot derates linearly with 5.5 mW/K above 60 C.

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Product data sheet Rev. 4 — 17 September 2012 3 of 16

NXP Semiconductors 74HC4002; 74HCT4002
Dual 4-input NOR gate

8. Recommended operating conditions

Table 5. Recommended operating conditions
Voltages are referenced to GND (ground = 0 V)
Symbol Parameter Conditions 74HC4002 74HCT4002 Unit
Min Typ Max Min Typ Max
VCC supply voltage 2.0 5.0 6.0 4.5 5.0 5.5 V
VI input voltage 0 - VCC 0 - VCC V
VO output voltage 0 - VCC 0 - VCC V
Tamb ambient temperature 40 +25 +125 40 +25 +125 C
t/V input transition rise and fall rate VCC = 2.0 V - - 625 - - - ns/V
VCC = 4.5 V - 1.67 139 - 1.67 139 ns/V
VCC = 6.0 V - - 83 - - - ns/V

9. Static characteristics
Table 6. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +125 C Unit
Min Typ Max Min Max Min Max
74HC4002
VIH HIGH-level VCC = 2.0 V 1.5 1.2 - 1.5 - 1.5 - V
input voltage VCC = 4.5 V 3.15 2.4 - 3.15 - 3.15 - V
VCC = 6.0 V 4.2 3.2 - 4.2 - 4.2 - V
VIL LOW-level VCC = 2.0 V - 0.8 0.5 - 0.5 - 0.5 V
input voltage VCC = 4.5 V - 2.1 1.35 - 1.35 - 1.35 V
VCC = 6.0 V - 2.8 1.8 - 1.8 - 1.8 V
VOH HIGH-level VI = VIH or VIL
output voltage IO = 20 A; VCC = 2.0 V 1.9 2.0 - 1.9 - 1.9 - V
IO = 20 A; VCC = 4.5 V 4.4 4.5 - 4.4 - 4.4 - V
IO = 20 A; VCC = 6.0 V 5.9 6.0 - 5.9 - 5.9 - V
IO = 4.0 mA; VCC = 4.5 V 3.98 4.32 - 3.84 - 3.7 - V
IO = 5.2 mA; VCC = 6.0 V 5.48 5.81 - 5.34 - 5.2 - V
VOL LOW-level VI = VIH or VIL
output voltage IO = 20 A; VCC = 2.0 V - 0 0.1 - 0.1 - 0.1 V
IO = 20 A; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V
IO = 20 A; VCC = 6.0 V - 0 0.1 - 0.1 - 0.1 V
IO = 4.0 mA; VCC = 4.5 V - 0.15 0.26 - 0.33 - 0.4 V
IO = 5.2 mA; VCC = 6.0 V - 0.16 0.26 - 0.33 - 0.4 V
II input leakage VI = VCC or GND; - - 0.1 - 1 - 1 A
current VCC = 6.0 V
ICC supply current VI = VCC or GND; IO = 0 A; - - 2 - 20 - 40 A
VCC = 6.0 V

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Product data sheet Rev. 4 — 17 September 2012 4 of 16

NXP Semiconductors 74HC4002; 74HCT4002
Dual 4-input NOR gate

Table 6. Static characteristics …continued

At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +125 C Unit
Min Typ Max Min Max Min Max
CI input - 3.5 - - - - - pF
capacitance
74HCT4002
VIH HIGH-level VCC = 4.5 V to 5.5 V 2.0 1.6 - 2.0 - 2.0 - V
input voltage
VIL LOW-level VCC = 4.5 V to 5.5 V - 1.2 0.8 - 0.8 - 0.8 V
input voltage
VOH HIGH-level VI = VIH or VIL; VCC = 4.5 V
output voltage IO = 20 A 4.4 4.5 - 4.4 - 4.4 - V
IO = 4.0 mA 3.84 4.32 - 3.84 - 3.7 - V
VOL LOW-level VI = VIH or VIL; VCC = 4.5 V
output voltage IO = 20 A - 0 0.1 - 0.1 - 0.1 V
IO = 5.2 mA - 0.15 0.26 - 0.33 - 0.4 V
II input leakage VI = VCC or GND; - - 0.1 - 1 - 1 A
current VCC = 5.5 V
ICC supply current VI = VCC or GND; IO = 0 A; - - 2 - 20 - 40 A
VCC = 5.5 V
ICC additional per input pin; - 45 162 - 203 - 221 A
supply current VI = VCC  2.1 V; IO = 0 A;
other inputs at VCC or GND;
VCC = 4.5 V to 5.5 V
CI input - 3.5 - - - - - pF
capacitance

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Product data sheet Rev. 4 — 17 September 2012 5 of 16

NXP Semiconductors 74HC4002; 74HCT4002
Dual 4-input NOR gate

10. Dynamic characteristics

Table 7. Dynamic characteristics
GND = 0 V; CL = 50 pF; for load circuit see Figure 8.
Symbol Parameter Conditions 25 C 40 C to +125 C Unit
Min Typ Max Max Max
(85 C) (125 C)
74HC4002
tpd propagation delay nA, nB, nC or nD to nY; [1]

see Figure 7
VCC = 2.0 V - 30 100 125 150 ns
VCC = 4.5 V - 11 20 25 30 ns
VCC = 6.0 V - 9 17 21 26 ns
VCC = 5.0 V; CL = 15 pF - 9 - - - ns
tt transition time see Figure 7 [2]

VCC = 2.0 V - 19 75 95 110 ns

VCC = 4.5 V - 7 15 19 22 ns
VCC = 6.0 V - 6 13 16 19 ns
CPD power dissipation per package; VI = GND to VCC [3] - 16 - - - pF
capacitance
74HCT4002
tpd propagation delay nA, nB, nC or nD to nY; [1]

see Figure 7
VCC = 4.5 V - 13 22 28 33 ns
VCC = 5.0 V; CL = 15 pF - 11 - - - ns
tt transition time VCC = 4.5 V; see Figure 7 [2] - 7 15 19 22 ns
CPD power dissipation per package; [3] - 22 - - - pF
capacitance VI = GND to VCC  1.5 V

[1] tpd is the same as tPHL and tPLH.

[2] tt is the same as tTHL and tTLH.
[3] CPD is used to determine the dynamic power dissipation (PD in W):
PD = CPD  VCC2  fi  N +  (CL  VCC2  fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
 (CL  VCC2  fo) = sum of outputs.

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NXP Semiconductors 74HC4002; 74HCT4002
Dual 4-input NOR gate

11. Waveforms

9,
Q$Q%Q& 90
Q'LQSXW
*1'

W3+/ W3/+
92+
9<
Q<RXWSXW 90
9;
92/
W7+/ W7/+
DDD

Measurement points are given in Table 8.

VOL and VOH are typical voltage output levels that occur with the output load.
Fig 7. Waveforms showing the input (nA, nB, nC, nD) to output (nY) propagation delays and the output
transition times

Table 8. Measurement points

Type Input Output
VM VM VX VY
74HC4002 0.5VCC 0.5VCC 0.1VCC 0.9VCC
74HCT4002 1.3 V 1.3 V 0.1VCC 0.9VCC

tW
VI
90 %
negative
VM VM
pulse
10 %
GND
tf tr
tr tf
VI
90 %
positive
VM VM
pulse
10 %
GND tW

VCC

VI VO
G DUT

RT CL

001aah768

Test data is given in Table 9.

Definitions test circuit:
RT = termination resistance should be equal to output impedance Zo of the pulse generator.
CL = load capacitance including jig and probe capacitance.
Fig 8. Test circuit for measuring switching times

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Product data sheet Rev. 4 — 17 September 2012 7 of 16

NXP Semiconductors 74HC4002; 74HCT4002
Dual 4-input NOR gate

Table 9. Test data

Type Input Load Test
VI tr, tf CL
74HC4002 VCC 6.0 ns 15 pF, 50 pF tPLH, tPHL
74HCT4002 3.0 V 6.0 ns 15 pF, 50 pF tPLH, tPHL

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NXP Semiconductors 74HC4002; 74HCT4002
Dual 4-input NOR gate

12. Package outline

DIP14: plastic dual in-line package; 14 leads (300 mil) SOT27-1

D ME
seating plane

A2 A

L A1

c
Z e w M
b1
(e 1)
b
14 8 MH

pin 1 index
E

1 7

0 5 10 mm
scale

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

UNIT
A A1 A2
b b1 c D (1) E (1) e e1 L ME MH w Z (1)
max. min. max. max.
1.73 0.53 0.36 19.50 6.48 3.60 8.25 10.0
mm 4.2 0.51 3.2 2.54 7.62 0.254 2.2
1.13 0.38 0.23 18.55 6.20 3.05 7.80 8.3
0.068 0.021 0.014 0.77 0.26 0.14 0.32 0.39
inches 0.17 0.02 0.13 0.1 0.3 0.01 0.087
0.044 0.015 0.009 0.73 0.24 0.12 0.31 0.33

Note
1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.

OUTLINE REFERENCES EUROPEAN

ISSUE DATE
VERSION IEC JEDEC JEITA PROJECTION

99-12-27
SOT27-1 050G04 MO-001 SC-501-14
03-02-13

Fig 9. Package outline SOT27-1 (DIP14)

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Product data sheet Rev. 4 — 17 September 2012 9 of 16

NXP Semiconductors 74HC4002; 74HCT4002
Dual 4-input NOR gate

SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1

D E A
X

y HE v M A

14 8

Q
A2
(A 3) A
A1
pin 1 index
θ
Lp

1 7 L

e w M detail X
bp

0 2.5 5 mm
scale

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

A
UNIT A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) θ
max.
0.25 1.45 0.49 0.25 8.75 4.0 6.2 1.0 0.7 0.7
mm 1.75 0.25 1.27 1.05 0.25 0.25 0.1
0.10 1.25 0.36 0.19 8.55 3.8 5.8 0.4 0.6 0.3 8o
o
0.010 0.057 0.019 0.0100 0.35 0.16 0.244 0.039 0.028 0.028 0
inches 0.069 0.01 0.05 0.041 0.01 0.01 0.004
0.004 0.049 0.014 0.0075 0.34 0.15 0.228 0.016 0.024 0.012

Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

OUTLINE REFERENCES EUROPEAN

ISSUE DATE
VERSION IEC JEDEC JEITA PROJECTION

99-12-27
SOT108-1 076E06 MS-012
03-02-19

Fig 10. Package outline SOT108-1 (SO14)

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Product data sheet Rev. 4 — 17 September 2012 10 of 16

NXP Semiconductors 74HC4002; 74HCT4002
Dual 4-input NOR gate

SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm SOT337-1

D E A
X

c
y HE v M A

14 8

Q
A2 A
A1 (A 3)

pin 1 index
θ
Lp
L

1 7 detail X

w M
e bp

0 2.5 5 mm
scale

DIMENSIONS (mm are the original dimensions)

A
UNIT A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) θ
max.

mm 2
0.21 1.80 0.38 0.20 6.4 5.4 7.9 1.03 0.9 1.4 8o
0.25 0.65 1.25 0.2 0.13 0.1 o
0.05 1.65 0.25 0.09 6.0 5.2 7.6 0.63 0.7 0.9 0

Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

OUTLINE REFERENCES EUROPEAN

ISSUE DATE
VERSION IEC JEDEC JEITA PROJECTION

99-12-27
SOT337-1 MO-150
03-02-19

Fig 11. Package outline SOT337-1 (SSOP14)

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Product data sheet Rev. 4 — 17 September 2012 11 of 16

NXP Semiconductors 74HC4002; 74HCT4002
Dual 4-input NOR gate

TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1

D E A
X

y HE v M A

14 8

Q
A2 (A 3)
A
A1
pin 1 index

θ
Lp
L
1 7
detail X
w M
e bp

0 2.5 5 mm
scale

DIMENSIONS (mm are the original dimensions)

A
UNIT A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ
max.

mm 1.1
0.15 0.95 0.30 0.2 5.1 4.5 6.6 0.75 0.4 0.72 8o
0.25 0.65 1 0.2 0.13 0.1 o
0.05 0.80 0.19 0.1 4.9 4.3 6.2 0.50 0.3 0.38 0

Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

OUTLINE REFERENCES EUROPEAN

ISSUE DATE
VERSION IEC JEDEC JEITA PROJECTION

99-12-27
SOT402-1 MO-153
03-02-18

Fig 12. Package outline SOT402-1 (TSSOP14)

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Product data sheet Rev. 4 — 17 September 2012 12 of 16

NXP Semiconductors 74HC4002; 74HCT4002
Dual 4-input NOR gate

13. Abbreviations
Table 10. Abbreviations
Acronym Description
CMOS Complementary Metal Oxide Semiconductor
DUT Device Under Test
ESD ElectroStatic Discharge
HBM Human Body Model
MM Machine Model
TTL Transistor-Transistor Logic

14. Revision history

Table 11. Revision history
Document ID Release date Data sheet status Change notice Supersedes
74HC_HCT4002 v.4 20120917 Product data sheet - 74HC_HCT4002 v.3
Modifications: • Table 1: Type number 74HC20DB changed into 74HC4002DB.
74HC_HCT4002 v.3 20120904 Product data sheet - 74HC_HCT4002_CNV v.2
Modifications: • The format of this data sheet has been redesigned to comply with the new identity
guidelines of NXP Semiconductors.
• Legal texts have been adapted to the new company name where appropriate.
74HC_HCT4002_CNV v.2 19970829 Product specification - -

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Product data sheet Rev. 4 — 17 September 2012 13 of 16

NXP Semiconductors 74HC4002; 74HCT4002
Dual 4-input NOR gate

15. Legal information

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Objective [short] data sheet Development This document contains data from the objective specification for product development.
Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.
Product [short] data sheet Production This document contains the product specification.

[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
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information is available on the Internet at URL http://www.nxp.com.

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Product data sheet Rev. 4 — 17 September 2012 14 of 16

NXP Semiconductors 74HC4002; 74HCT4002
Dual 4-input NOR gate

Export control — This document as well as the item(s) described herein NXP Semiconductors’ specifications such use shall be solely at customer’s
may be subject to export control regulations. Export might require a prior own risk, and (c) customer fully indemnifies NXP Semiconductors for any
authorization from competent authorities. liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
Non-automotive qualified products — Unless this data sheet expressly
standard warranty and NXP Semiconductors’ product specifications.
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested Translations — A non-English (translated) version of a document is for
in accordance with automotive testing or application requirements. NXP reference only. The English version shall prevail in case of any discrepancy
Semiconductors accepts no liability for inclusion and/or use of between the translated and English versions.
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer 15.4 Trademarks
(a) shall use the product without NXP Semiconductors’ warranty of the
Notice: All referenced brands, product names, service names and trademarks
product for such automotive applications, use and specifications, and (b)
are the property of their respective owners.
whenever customer uses the product for automotive applications beyond

16. Contact information

For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com

74HC_HCT4002 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.

Product data sheet Rev. 4 — 17 September 2012 15 of 16

NXP Semiconductors 74HC4002; 74HCT4002
Dual 4-input NOR gate

17. Contents
1 General description . . . . . . . . . . . . . . . . . . . . . . 1
2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1
3 Ordering information . . . . . . . . . . . . . . . . . . . . . 1
4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 2
5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
6 Functional description . . . . . . . . . . . . . . . . . . . 3
7 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3
8 Recommended operating conditions. . . . . . . . 4
9 Static characteristics. . . . . . . . . . . . . . . . . . . . . 4
10 Dynamic characteristics . . . . . . . . . . . . . . . . . . 6
11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9
13 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 13
14 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 13
15 Legal information. . . . . . . . . . . . . . . . . . . . . . . 14
15.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 14
15.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
15.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
15.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 15
16 Contact information. . . . . . . . . . . . . . . . . . . . . 15
17 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.

© NXP B.V. 2012. All rights reserved.

For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 17 September 2012
Document identifier: 74HC_HCT4002
This datasheet has been downloaded from:

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