MCQs
MCQs
MCQs
No
UNIT-I
PIC16FXXX Mid-Range MCU Family Architecture,
Instruction Flow and pipelining,
general instruction format,
Arithmetic Logical Unit (ALU),
Program and data Memory organization,
Basic instruction set summary.
1.BASICS
1 1 The assembler list file generated by an assembler R1_P3_5
mainly includes ________
a. binary codes
b. assembly language statements
c. offset for each instruction
d. All of the above
a. Only A
b. Only B
c. Only A & B
d. A & D
A (a) Only A
39 2 How many bits are utilized by the instruction of direct R1_p4_33
addressing mode in order to address the register files
in PIC?
a. 2
b. 5
c. 7
d. 8
A c.7
INSTRUCTION SET
40 1 Which instruction is applicable to set any bit while R1_P5_24
performing bitwise operation settings?
a. bcf
b. bsf
c. Both a & b
d. None of the above
A (b) bsf
34
A
35
A
36
A
IO PORT & PROGRAMMING
41 1 What is the possible range of current limiting resistor R1_P3_20
essential for lightening the LED in certain applications
after pressing the push-button?
a. 25-55 Ω
b. 55-110 Ω
c. 110-220 Ω
d. 220-330 Ω
A (d) 220-330 Ω
42 2 What does the availability of LCD in 16 x 2 typical R1_P3_22
value indicate?
a. 16 lines per character with 2 such lines
b. 16 characters per line with 2 such lines
c. 16 pixels per line with 2 such sets
d. 16 lines per pixel with two such sets
A (c) 15 ms
47 7 On which factors do the delay between two characters R1_P3_29
depend for display purposes in LCD?
a. Clock frequency
b. Display module
c. Both a & b
d. None of the above
A (c) Both a & b
48 8 How many data lines are essential in addition to RS, R1_P3_30
EN and RW control lines for interfacing LCD with
microcontroller?
a. 4
b. 5
c. 8
d. 10
A (c) 8
49 9 How is the latch interfacing with the microcontroller R1_P3_42
related to the number of digital output functions?
a. It increases the number of digital output functions in
a time multiplexed manner
b. It decreases the number of digital output functions
in a time multiplexed manner
c. It increases the number of digital output functions in
a frequency multiplexed manner
d. It decreases the number of digital output functions
in a frequency multiplexed manner
A (a) It increases the number of digital output functions
in a time multiplexed manner
50 10 In an electromechanical relay, the necessity of R1_P3_44
connecting an external base resistance arises only
_________
a. in the presence of an internal pull-up resistor
b. in the absence of an internal pull-up resistor
c. in the absence of an internal push-up resistor
d. in the presence of an internal push-up resistor
A (b) in the absence of an internal pull-up resistor
51 11 Which diodes are employed in the electromechanical R1_P3_45
relays since the inductor current cannot be reduced to
zero?
a. Tunnel Diode
b. Shockley Diode
c. Freewheeling Diode
d. Zener Diode
Q
A
Q
A
UNIT-II
ADVANCED PERIPHERALS - Timers, CCP
(Capture/Compare/PWM) module, A/D converter,
Master Synchronous Serial Port (MSSP) module –
SPI mode and I2C mode. Watchdog timer and sleep
mode, Device configuration Bits.
Timers, WDT
1 1 Which timer/s possess an ability to prevent an endless R1_P5_7
loop hanging condition of PIC along with its own on-
chip RC oscillator by contributing to its reliable
operation?
a. Power-Up Timer (PWRT)
b. Oscillator Start-Up Timer (OST)
c. Watchdog Timer (WDT)
d. All of the above
A (c) Watchdog Timer (WDT)
2 2 Where are the prescalar assignments applied with a R1_P4_39
usage of PSA bit?
a. Only RTCC
b. Only Watchdog timer
c. Either RTCC or Watchdog timer
d. Neither RTCC nor Watchdog timer
A (c) Either RTCC or Watchdog timer
Which bits play a crucial role in specifying the R2_T0_WDT_2
a.PD & TO
b. C & Z
c. DC & RPO
d. All of the above
a. ADIF
b. ADON
c. Go/!Done
d. ADSC1
A (c) Go/!Done
20 10 What would be the value of ADC clock source, if both R1_P4_58
the ADC clock bits are selected to be ‘1’?
a. FOSC/2
b. FOSC/8
c. FOSC/32
d. FRC
A (d) FRC
21 11 The functionalities associated with the pins RA0- RA3 R1_P4_59
in ADCON1 are manipulated by __________
a. PCFG1 & PCG0
b. VREF
c. ADON
d. All of the above
A (a) PCFG1 & PCG0
22 5 Where do the conversion interrupt flag (ADIF) end R1_p4_52
after an accomplishment of analog-to-digital (ADC)
conversion process?
a. INTCON
b. ADCON0
c. OPTION
d. None of the above
A (b) ADCON0
23 6 How much time is required for conversion per channel R1_p4_53
if PIC 16C71 possesses four analog channels, each
comprising of 8-bits?
a. 10 μs
b. 15 μs
c. 20 μs
d. 30 μs
A (c) 20 μs
24 3 Where is the exact specified location of an interrupt R1_P4_40
flag associated with analog-to-digital converter?
a. INTCON
b. ADCON0
c. ADRES
d. PCLATH
A (b) ADCON0
Master Synchronous Serial Port (MSSP) module –
SPI mode
25 41 Which among the below stated salient feature/s of SPI R1_P3-1
contribute to the wide range of its applicability?
a. Simple hardware interfacing
b. Full duplex communication
c. Low power requirement
d. All of the above
A (d) SSPEN
28 Q What should be the value of SSPM3:SSPM0 bits so 2 R1_P5_8
that SPI can enter the slave mode by enabling SS pin
control?
a. 0000
b. 0100
c. 0010
d. 0001
A (b) 0100
29 Q How many upper bits of SSPSR are comparable to R1_P5_12
the address located in SSPADD especially after the
shifting of 8 bits into SSPSR under the execution of
START condition?
a. 7
b. 8
c. 16
d. 32
A (a) 7
a. SSPADD
b. SSPBUF
c. Both a & b
d. None of the above
A a. SSPADD
31 38 Which command/s should be essentially written for I2C
input threshold selection and slew rate control
operations?
a. SSPSTAT
b. SSPIF
c. ACKSTAT
d. All of the above
A a. SSPSTAT
32 39 Where does the baud rate generation occur and
begins to count the bits required to get transmitted,
after an execution (set) of BF flag?
a. SCL line
b. SDA line
c. Both a & b
d. None of the above
A b. SDA line
33 40 How many upper bits of SSPSR are comparable to
the address located in SSPADD especially after the
shifting of 8 bits into SSPSR under the execution of
START condition?
a. 7
b. 8
c.16
d.32
A a. 7
34 Q Which bits assist in determining the I2C bit rate during
the initialization process of MSSP module in I2C
mode?
a. SSPADD
b. SSPBUF
c. Both a & b
d. None of the above
A (a) SSPADD
35 Q Where does the baud rate generation occur and R1_P5_11
begins to count the bits required to get transmitted,
after an execution (set) of BF flag?
a. SCL line
b. SDA line
c. Both a & b
d. None of the above
A (b) SDA line
36 37 Which bits assist in determining the I2C bit rate during
the initialization process of MSSP module in I2C
mode?
a. SSPADD
b. SSPBUF
c. Both a & b
d. None of the above
A a. SSPADD
37 38 Which command/s should be essentially written for I2C
input threshold selection and slew rate control
operations?
a. SSPSTAT
b. SSPIF
c. ACKSTAT
d. All of the above
A a. SSPSTAT
38 39 Where does the baud rate generation occur and
begins to count the bits required to get transmitted,
after an execution (set) of BF flag?
a. SCL line
b. SDA line
c. Both a & b
d. None of the above
A b. SDA line
39 40 How many upper bits of SSPSR are comparable to
the address located in SSPADD especially after the
shifting of 8 bits into SSPSR under the execution of
START condition?
a. 7
b. 8
c.16
d.32
USART
34 Where should the value of TX9 bit be loaded during
the 9 bit transmission in an asynchronous mode?
a. TXSTA
b. RCSTA
c. SPBRG
d. All of the above
A a. TXSTA
35 Why is the flag bit TXIF tested or examined in the
PIR1 register after shifting all the data bits during the
initialization process of USART in asynchronous
mode?
a. FOSC / 8 (X +1 )
b. FOSC / 16 (X +1 )
c. FOSC / 32 (X +1 )
d. FOSC / 64 (X +1 )
A b. FOSC / 16 (X +1 )