THE MINISTRY OF EDUCATION AND SCIENCE OF UKRAINE

KHARKIV NATIONAL UNIVERSITY

OF RADIO ELECTRONICS

CENTER FOR STUDENTS TRAINING

IN FOREIGN LANGUAGES

GUIDELINES
FOR LABORATORY WORK

for full-time students of specialty 6.050102 “Computer engineering”

by discipline “COMPUTER LOGIC”

Composed by
Dariia E. Kucherenko

KHARKOV 2013
Guidelines for laboratory work of the discipline “Computer logic” for students of
specialty 6.050102 “Computer engineering” / Redactor: Syrevitch Yev.Yef.,
Kucherenko D.Yef. –Kharkov:KNURE, 2013. − p.

Redactor: Yev.Yef. Syrevitch

D.Yef. Kucherenko
 CONTEXT

Introduction ………………………………………………………………….. 4

1. Introduction to XILINX ISE 14.6………………………………………... 7

2. Simple combinational circuit design ………………………………...…... 24
3. Multiplexer/demultiplexer design………………………………………... 28
4. Encoder/decoder design……………………………………………...…... 33
5. Structural type of VHDL description…………………………………….. 39
6. Simulation of latches/flip-flops……………………………………...…… 45
7. Counters and shifter based on trigger……………………………………. 57
8. Finite state machine………………………………………………………. 62
9. Code converters design…………………………………………………... 71
Reference……………………………………………………………………... 75
 INTRODUCTION

Computer logic is an aspect of computer design concerning the fundamental

operations and structures upon which all computer systems are built. Theoretical part
of this discipline contains such topics as number system and codes, logic gates and
digital circuit, combinational logic design, sequential logic, memory and etc.
During the labs students will:
− perform the conversion of the numbers to and from a common numeral
systems, calculate addition, subtraction, multiplication and division results of two
binary numbers with a different sign;
− minimize Boolean functions using Karnaugh maps, synthesize of the
combinational circuits;
− form a transition table, transition graphs, a transition matrix and
characteristic functions of transitions for different types of synchronous and
asynchronous flip-flops;
− build a table of transitions, transition graphs for Moore automata; perform
synthesis machines based on a graph-scheme of an algorithm;
− form a description of combinational circuits, flip-flops and machines using
VHDL;
− develop algorithms of arithmetic and logic devices;
− perform functional verification of VHDL-models of devices by simulation;
− use CAD-systems for simulation and implementation of device models.
For practical development of design methods based on programmable logic
device of FPGA family we will use tool set SPARTAN-3E STARTER KIT (fig. i.1).

Figure i.1 – Spartan 3E Starter Board

The Spartan 3E Starter Board provides a powerful and highly advanced self-
contained development platform for designs targeting the Spartan 3E FPGA from
Xilinx. It features a 500K gate Spartan 3E FPGA with a 32 bit RISC processor and
DDR interfaces.

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 The board also features a Xilinx Platform Flash, USB and JTAG parallel
programming interfaces with numerous FPGA configuration options via the onboard
Intel StrataFlash and ST Microelectronics Serial Flash. The board is fully compatible
with all versions of the Xilinx ISE tools including the free WebPack. The board ships
with a power supply and USB cable for programming so designs can be implemented
immediately with no hidden costs.
The key features of the Spartan-3E Starter Kit board are:
 Xilinx XC3S500E Spartan-3E FPGA
 Up to 232 user-I/O pins
 320-pin FBGA package
 Over 10,000 logic cells
 Xilinx 4 Mbit Platform Flash configuration PROM
 Xilinx 64-macrocell XC2C64A CoolRunner CPLD
 64 MByte (512 Mbit) of DDR SDRAM, x16 data interface, 100+ MHz
 16 MByte (128 Mbit) of parallel NOR Flash (Intel StrataFlash)
 FPGA configuration storage
 MicroBlaze code storage/shadowing
 16 Mbits of SPI serial Flash (STMicro)
 FPGA configuration storage
 MicroBlaze code shadowing
 2-line, 16-character LCD screen
 PS/2 mouse or keyboard port
 VGA display port
 10/100 Ethernet PHY (requires Ethernet MAC in FPGA)
 Two 9-pin RS-232 ports (DTE- and DCE-style)
 On-board USB-based FPGA/CPLD download/debug interface
 50 MHz clock oscillator
 SHA-1 1-wire serial EEPROM for bitstream copy protection
 Hirose FX2 expansion connector
 Three Digilent 6-pin expansion connectors
 Four-output, SPI-based Digital-to-Analog Converter (DAC)
 Two-input, SPI-based Analog-to-Digital Converter (ADC) with
programmable-gain pre-amplifier
 ChipScope™ SoftTouch debugging port
 Rotary-encoder with push-button shaft
 Eight discrete LEDs
 Four slide switches
 Four push-button switches
 SMA clock input
 8-pin DIP socket for auxiliary clock oscillator.

The kit includes a standard USB Type A/Type B cable, similar to the one
shown in figure i.2.

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 Figure i.2 – Standard USB Type A/Type B Cable

The wider and narrower Type A connector fits the USB connector at the back
of the computer. After installing the Xilinx software, connect the square Type B
connector to the Spartan-3E Starter Kit board, as shown in figure i.3.

Figure i.3 – Standard the USB Type B Connector to the Starter Kit Board Connector

The USB connector is on the left side of the board, immediately next to the
Ethernet connector. When the board is powered on, the Windows operating system
should recognize and install the associated driver software. When the USB cable
driver is successfully installed and the board is correctly connected to the PC, a green
LED lights up, indicating a good connection.
This course introduces the VHDL language and then provides a series of
tutorials that demonstrate the use of VHDL running on a Xilinx CPLD. It starts with
some very basic and easy examples that will get the beginner in VHDL started
comfortably. VHDL is an industry-standard language for modeling and synthesizing
digital hardware, particularly for programmerable logic or Application Specific
Integrated Circuits. The VHDL simulation serves as a basis for testing complex
designs and validating the design prior to fabrication. As a result, the redesign is
reduced, the design cycle is shortened, and the product is brought to market sooner. A
VHDL program can be considered as a description of a digital system; the associated
simulator will use this description to produce behavior that will mimic that of the
physical system.
The software used to write the VHDL code and program the CPLD is the free
Xilinx ISE software (called WebPACK). Xilinx Integrated Software Environment
(ISE) – is design software suite which allows you to take your design from design
entry through Xilinx device programming. The ISE Project Navigator manages and
processes your design through several steps in the ISE design flow. These steps are
Design Entry, Synthesis, Implementation, Simulation/Verification, and Device
Configuration.

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 1 INTRODUCTION TO THE ENVIRONMENT PROJECT NAVIGATOR
CAD-PACKAGE XILINX ISE 14.6

1.1 Purpose of the work

This lab is an introduction to logic design using VHDL with the Xilinx ISE x.y
tools. No new logic design concepts are presented in this lab. The goal of this lab is
for you to become familiar with the tools you will be using for the rest of the
semester: The Xilinx ISE Project Navigator and The Xilinx Spartan-3E Starter Kit.
Please read carefully, pay attention, and take your time.
In order to receive credit for this lab, you must demonstrate to the instructor
that your final design works correctly in hardware. The details of the required
demonstration are at the end of the lab handout.

1.2 Instructions for the independent work organization

Before the work it is necessary to study theoretical material and lecture notes.

1.3 The required software

Laboratory work is done individually. On every workplace must be installed

Xilinx ISE 14.1. SE® WebPACK™ design software is the industry´s only FREE,
fully featured front-to-back FPGA design solution for Linux, Windows XP, and
Windows 7. ISE WebPACK is the ideal downloadable solution for FPGA and CPLD
design offering HDL synthesis and simulation, implementation, device fitting, and
JTAG programming. ISE WebPACK delivers a complete, front-to-back design flow
providing instant access to the ISE features and functionality at no cost. Xilinx has
created a solution that allows convenient productivity by providing a design solution
that is always up to date with error-free downloading and single file installation
(URL:http://www.xilinx.com/support/download/index.html/content/xilinx/en/downlo
adNav/design-tools.html ).

1.4 The order of work and guidelines for its implementation

1.4.1 Design entry

The design will be described in VHDL. Select Start→Programs→Xilinx

Design Tools →ISE Design Suite14.6 → ISE Design Tools→ ProjectNavigator.
From Project Navigator, select File→New Project. The first of the New
Project dialog boxes will appear, as shown in figure 1.1.

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 Figure 1.1 − New Project Dialog 1 of 3

You are prompted to enter a project name, a project location, and a top level
source type, as shown in figure 1.1. You may change the project location to another
folder if you wish.
Do not use file or folder names that contain spaces. I advise all students to
purchase a USB Flash Drive and store their labs on removable media. Even though
you are doing most of your work from home, you must have some means to transport
your project to the lab if you need help debugging it. Never store your projects on the
lab machines!!!
When you are satisfied with the project name and location, click “Next”.
The next dialog allows you to set additional project options.

Figure 1.2 − New Project Dialog 2 of 3

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 The first group of settings shown in figure 1.2 represents the FPGA that is
available to you on the Spartan-3E Starter Kit board. The second group of settings
represents the design entry language, synthesis tool, and simulator preferences. Set
the options as shown in figure 1.2 and click “Next”.
The final dialog box in the new project process, shown in figure 1.3, provides a
summary of the project that Project Navigator will create based on your settings.
Review the summary to make sure it matches what is shown in figure 1.3. If it does
not, go “Back” and correct any errors. Otherwise, click “Finish” to complete this
process.

Figure 1.3 − New Project Dialog 3 of 3

At this point, the project has been created but it does not contain any source
files. Create a new source file for the new design. Either select Project→New
Source from the main menu or use the equivalent process in the Processes window.
The first of the New Source dialog boxes will appear, shown in figure 1.4.

Figure 1.4 − New Source Dialog 1 of 3

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 Select VHDL Module to indicate you are creating a VHDL design module.
Then, provide a filename as shown in figure 1.4. You should not need to change the
specified location, which should be inside the project directory you created earlier.
Click “Next”.
The next dialog optionally allows you to specify the ports of the module. This
may also bedone in the text editor, when creating the module, so skip it at this stage.
Simply confirm that the settings match those shown in figure 1.5 and click “Next”.

Figure 1.5 − New Source Dialog 2 of 3

The final dialog box in figure 1.6 provides a summary of the source that Project
Navigator will create based on your settings. Review the summary to make sure it
matches what is shown in figure 1.6. If it does not, go “Back” and correct any errors.
Otherwise, click “Finish” to complete this process.

Figure 1.6 − New Source Dialog 3 of 3

Now, in figure 1.7 you can see the result.

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 Figure 1.7 − The window of your future project

Project Navigator is divided into four sub-areas (fig. 1.7). On the top left is the
Sources window which hierarchically displays the elements included in the project
for the currently selected stage of the design flow. Beneath the Sources window is the
Processes window which displays available processes for the currently selected
source. The third area at the bottom is the Console window which displays status
messages, errors, and warnings. The fourth area, on the top right, is for viewing and
editing project files. Each window may be resized or moved within Project
Navigator. The default layout can always be restored by selecting View → Restore
Default Layout.
In the text editor, some of the basic file structure is already in place although
we are going to replace everything that was automatically generated. Keywords are
displayed in blue, data types in red, comments in green, and values in black. This
color-coding enhances readability and recognition of typographical errors.
Now, you can enter the VHDL-code of the combinational circuit design. But,
before that you have to learn methods of combinational circuits’ synthesis and way of
its representation.

1.4.2 Pre-lab Work

Let’s create the design of the combinational circuit to display number in the
binary system (figure 1.8).

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 Figure 1.8 − LED’s for binary number representation

The input decimal number X have to be represent in the binary system. For
example,
X in decimal system X in binary system
5 101
It means that X is vector which consists of 3 bits. You can see the following
VHDL code for our design:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL; The connection of the libraries.
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity lab is
The description of the input and
port (x:inout std_logic_vector (2 downto 0);
output.
y:out std_logic_vector (2 downto 0));
end lab;
The dimension of these vectors has to
be the same.
architecture Behavioral of lab is
begin
The description of the architecture
x<="101";
body (the function of the circuit).
y<=x;
end Behavioral;

This template of the VHDL-code you have to change according to your variant
and paste to the Test editor of the Project Navigator. At this point, you should end up
with a window that looks somewhat like that shown in figure 1.9. Once you are
satisfied, save the file and close the window. It is a good idea to get in the habit of
saving your project. There are options on the main menu to save individual files or
the complete project (Ctrl+S).

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 Figure 1.9 − Completed Design

1.4.3 Design synthesize

With a functionally correct design description in VHDL, the next step is to use
a synthesis tool to transform your description into a netlist. A netlist is a machine-
readable schematic.
To locate the synthesis process, set the Sources window to display sources for
Synthesis/Implementation. If you select the lab.vhd source file, you should then see
Synthesize-XST as an available process in the Processes window.
Double click on Synthesize-XST to run the synthesizer. When it has finished,
you should see a green checkmark next to this process as shown in figure 1.10.

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 Figure 1.10 − Design synthesize complete

You should not see any errors in the Console window. However, you should
always review the log file, which is available for viewing if you expand the
Synthesize-XST process item by clicking on the + next to it. Select View Synthesis
Report. If you don’t understand a particular message, you should not simply ignore
it. Instead, search the Xilinx support web site or ask the instructor.

1.4.4 Design implementation

Design implementation is the sequence of events that translates your

synthesized design netlist to a programming file for the FPGA device.
The design used in this tutorial is a combinational circuit. For this we will use
Spartan-3E Starter Kit board (figure 1.11).

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 Figure 1.11 – Spartan 3E Starter Board

Your design description, which you have now synthesized, has a number of
ports at the top level. The implementation tools need to know how to assign the ports
in your top level to physical pins on the FPGA, which are connected to various
resources on the Spartan-3E Starter Kit board. If you do not make explicit
assignments, the tools will randomly assign pins for you. However, this is generally a
bad idea because random assignments will be wrong.
You now have enough information to create what is called a user constraint
file, or UCF. This file contains design constraints that you did not specify in the
VHDL description, such as pin location and design performance constraints. It is
convenient to provide them in a UCF rather than in the VHDL description. For
instance, if you make a mistake in the pin assignments, you do not need to go back
and re-synthesize your design.
Specify the pin locations for the ports of the design so that they are connected
correctly on the Spartan-3 Startup Kit demo board.
To constrain the design ports to package pins, do the following:
1. Verify that lab.vhd is selected in the Sources window.
2. Select Project→New Source from the main menu or use the equivalent pro-
cess in the Processes window. The first of the New Source dialog boxes will appear,
as shown in figure 1.12.

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 Figure 1.12 − New Source Dialog 1 of 2

3. Select Implementation Constraints File to indicate you are creating a con-

straints file. Then, provide file name as shown in Figure 1.12. You should not need to
change the specified location, which should be inside the project directory you cre-
ated earlier. Click “Next”.
4. The final dialog box of Figure 1.13 provides a summary of the source that
Project Navigator will create based on your settings. Review the summary to make
sure it matches what is shown in Figure 1.13. If it does not, go “Back” and correct
any errors. Otherwise, click “Finish ” to complete this process.

Figure 1.13 − New Source Dialog 2 of 2

This time, however, you will notice that the new source file is not automatically

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opened in any editor.
5. Verify that lab.ucf is selected in the Sources window as shown in figure
1.14.

Figure 1.14 − UCF file edit

6. Click to + next to User Constraints and select text editor by choosing Edit
Constraints (Text). Paste following strings to field of editor and change according to
your variant.
NET "y(2)" LOC = "E11";
NET "y(1)" LOC = "E12";
NET "y(0)" LOC = "F12";

During this lab we will use only LEDs to observe the result. The names of the
physical pins on the board for LEDs represent below.

Now that you have a constraint file in your project, you can implement the
design. Select lab.vhd in the Sources window. Then, double click on the Implement
Design process in the Processes window (fig. 1.15).

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 Figure 1.15 − Design Implementation

You should not see any errors in the Console window. However, you should
always review the three log files, which are available for viewing if you expand the
Implement Design process item by clicking on the + next to it. There are log files
located under Translate, Map, and Place and Route. If you don’t understand a
particular message, you should not simply ignore it. Instead, search the Xilinx
support web site or ask the instructor. At this point, you should have a green
checkmark next to the Implement Design process (fig. 1.15).

1.4.5 FPGA programming

Programming the FPGA directly is a convenient way to try out a design. The
first order of business is to create a programming file for the FPGA. Select lab.vhd in
the Sources window. Then, double click on the Generate Programming File
process in the Processes window (fig.1.16). Project Navigator will generate a
programming file and print information to the Console window.

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 Figure 1.16 − Programming file generation

Before you continue, you must have the Spartan-3E Starter Kit board,
power supply, and USB cable available. Connect the USB cable to an available
USB port on the computer you are using. Plug the power supply into the wall. Then,
insert the power plug into the Power Jack and turn on the power. Be aware that if a
programming file was previously stored on the board, it will automatically load, and
may result in board activity like flashing LEDs, etc… This can be safely ignored.
Finally, connect the USB cable to its connector. As a side note – if this is the first
time you have used your board, the Windows New Hardware Wizard will run several
times while the drivers for the board are installed.
To download your bitstream to the FPGA device, click on the + next to
Configure Target Device, and then double click on the Manage Configuration
Project (iMPACT) process (fig. 1.17).

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 Figure 1.17 − iMPACT program launch loading

This will launch the iMPACT program in another window. The rest of the
tutorial is performed in iMPACT. When iMPACT launches, you will be presented
with a main window (fig. 1.18).

Figure 1.18 − iMPACT program launch

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 The board has an integrated JTAG programming function, which is also called
Boundary Scan. Now, double click on the Boundary Scan process in the iMPACT
Flows window (fig.1.18). iMPACT program launch will open Boundary Scan
window. Here right click to initialize JTAG chain (fig.1.19).

Figure 1.19 − JTAG chain initializing

After that, you will see the next message (fig. 1.20).

Figure 1.20 − Assign configuration files

Next, you should get a sequence of three file requestors. In the first file
requestor, shown in figure 1.21, select the lab.bit file you created with the
implementation process. This is the FPGA programming file.

Figure 1.21 − Selecting the FPGA programming file

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 Next, you will see the next window (fig. 1.22). Click “No”.

Figure 1.22 − Attach SPI or BPI PROM

Now, you will see the next files requestors. The purpose of the next two file
requestors is to identify programming files for other Xilinx devices on the board. We
are not programming either of these yet, so select BYPASS FOR BOTH (fig. 1.23).

Figure 1.23 − New configuration file for other Xilinx devices on the board

Now, you will see the next window with programming properties (fig. 1.24).
Do not change anything at this time; simply click “Ok” to proceed.

Figure 1.24 − Device programming properties

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 Finally, you will reach the display shown in figure 1.25. iMPACT is ready to
program the FPGA. Select the FPGA icon in the window and then use the right
mouse button to activate the menu as shown and select the Program option (fig. 1.25).
Note here, that the Assign New Configuration File option may be used to change
your configuration file assignments if you should ever need to do so.

Figure 1.25 − Device programming window

Now, right click on the first cheap and choose program. A progress indicator
will appear(figure 1.26).

Figure 1.26 − Progress indicator

Once the programming is complete, the program will be sure to let you know if
it was successful or if it failed.
If the programming has failed, re-check your cable connections, the power
connections, and the jumpers – and then try again. If it still fails, ask the instructor for
assistance.
Now, you can test your design in hardware. For our example, we have to
observe number 5dec (101bin): the led 2 and led 0 should be lit (fig. 1.13).

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 1.4.6 In-lab assignment

 Create a VHDL-model of a combinational circuit subject to your variant

(table 1.1). The number of your variant equals to the serial number in your register.

Table 1.1 − Variants

№ variant Description of input X in decimal system
1 72
2 101
3 35
4 60
5 188
6 157
7 56
8 245
9 85
10 132

 Run a synthesis of VHDL-model.

 Create the ucf-file and run an implementation.
 Program your project.
 Prepare your report.

1.5 Contents of the report

The report has to contain the individual task and VHDL-code.

1.6 Control questions and tasks

1. What does the term “VHDL” mean?

2. What are the stages of the of digital devices design in the environment Xilinx
Project Navigator?
3. What do the terms “synthesize”, “implementation”, and “programming”
mean?
4. What is the structure of the VHDL program?
5. Conversions between different number systems.

2 SIMPLE COMBINATIONAL CIRCUIT DESIGN

2.1 Purpose of the work

During this lab you will develop the combinational circuit design using VHDL

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language. For this purpose you will use minimization by Carnaugh map. To control
the correctness of your design you will program the Spartan-3E Starter Kit board.

2.2 Instructions for the independent work organization

Before the work it is necessary to study theoretical material and lecture notes.

2.3 The order of work and guidelines for its implementation

2.3.1 Design entry

The design will be described in VHDL. Select Start→Programs→Xilinx

Design Tools →ISE Design Suite14.6 → ISE Design Tools→ ProjectNavigator.
All instructions you can find in the lab № 1.

2.3.2 The example of the pre-lab work

During combinational circuit synthesis from specified logical function it’s
necessary to write its disjunctive normal form (DNF) from truth table in form of
disjunctions of “1” constituents. Then a minimization by Carnaugh map. Example:
Y=1 on sets (0, 1, 2, 4, 6, 8, 9, 12) using and-or-not elements. Let’s construct the
truth table (table 1.2).

Table 2.1 − Truth table

X X X X
№ of sets Y
1 2 3 4
0 0 0 0 0 1
1 0 0 0 1 1
2 0 0 1 0 1
3 0 0 1 1 0
4 0 1 0 0 1
5 0 1 0 1 0
6 0 1 1 0 1
7 0 1 1 1 0
8 1 0 0 0 1
9 1 0 0 1 1
10 1 0 1 0 0
11 1 0 1 1 0
12 1 1 0 0 1
13 1 1 0 1 0
14 1 1 1 0 0
15 1 1 1 1 0

Based on the truth table let’s create a Carnaugh map (fig. 2.1).

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 Figure 2.1 − Carnaugh map

After minimization we will get the minimal DNF:

Y =x3⋅x4∨x1⋅x4∨x2⋅x3 .
Now we can draw the combinational circuit (fig. 2.2).

Figure 2.2 − Combinational circuit

You can see the following VHDL template for our design:
library IEEE;
use IEEE.std_logic_1164.all;
entity comb_circt is
port ( x1: in STD_LOGIC;
x2: in STD_LOGIC;
x3: in STD_LOGIC;
x4: in STD_LOGIC;
y: out STD_LOGIC );
end comb_circt;
architecture arch of comb_circt is
begin
y <= ((not x4) and (not x3)) or ((not x1) and (not x4)) or ((not x3) and (not x2));
end arch;
Below you can see the UCF code for our design. You can use it without any
changing.
NET "x1" LOC = "L13";
NET "x2" LOC = "L14";
NET "x3" LOC = "H18";
NET "x4" LOC = "N17";
NET "y" LOC = "F12";

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 2.3.3 In-lab assignment

 Create a VHDL-model of a combinational circuit subject to your variant

(table 2.2). The number of your variant equals to the serial number in your register.

Table 2.2 − Variants

№ of variant Sets where Y=1
1 0, 1, 3, 5, 6, 7, 15
2 1, 2, 4, 6, 7, 14
3 3, 5, 7, 8, 13, 14
4 4, 6, 8, 9, 12, 13
5 5, 7, 9, 10, 11, 12
6 6, 8, 10,11, 12, 13
7 7, 9, 11, 12, 13, 14
8 8, 10, 12, 13, 14, 15
9 0, 9, 11, 13, 14, 15
10 0, 1, 10, 12, 14, 15
11 0, 2, 3, 11, 13, 15
12 0, 1, 3, 12, 14, 15
13 1, 2, 4, 6, 13, 15
14 0, 2, 4, 6, 9, 14
15 1, 6, 7, 8, 9, 15
 Draw the circuitry of your model.
 Run a synthesis of VHDL-model
 Create the ucf-file and run an implementation.
 Program your project.
 Prepare your report.

2.4 Contents of the report

The report has to contain the individual task, the truth table, the Carnaugh map,
the interface with inputs and output and the VHDL model with comments.

2.5 Control questions and tasks

1. What does the term “ucf - file” mean?

2. Minimization using Carnaugh map.
3. What does the term “combinational circuit” mean?
4. Graphical representation of the combinational circuits.
5. Truth table of all primitive elements?

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 3 MULTIPLEXER/DEMULTIPLEXER DESIGN

3.1 Purpose of the work

The goal of this lab is to become familiar with describing a digital circuit of
multiplexer or demultiplexer using truth tables, different types of the VHDL
descriptions.

3.2 Instructions for the independent work organization

Before the work it is necessary to study theoretical material and lecture notes.

3.3 The order of work and guidelines for its implementation

3.3.1 General theory

In telecommunications and computer networks, multiplexing (known as

muxing) is a term used to refer to a process where multiple analog message signals or
digital data streams are combined into one signal over a shared medium. The aim is
to share an expensive resource. For example, in telecommunications, several phone
calls may be transferred using one wire. The multiplexed signal is transmitted over a
communication channel, which may be a physical transmission medium. The
multiplexing divides the capacity of the low-level communication channel into
several higher-level logical channels, one for each message signal or data stream to
be transferred. A reverse process, known as demultiplexing, can extract the original
channels on the receiver side. A device that performs the multiplexing is called a
multiplexer (MUX), and a device that performs the reverse process is called a
demultiplexer (DEMUX). In digital circuit design, the selector wires are a digital
value. In the case of a 2-to-1 multiplexer, a logic value of 0 would connect I0 to the
output while a logic value of 1 would connect I1 to the output. In larger multiplexers,
the number of selector pins is equal to log 2  n  where n is the number of inputs. For
example, 9 to 16 inputs would require no less than 4 selector pins and 17 to 32 inputs
would require no less than 5 selector pins. The binary value expressed on these
selector pins determines the selected input pin.

3.3.2 Design entry

The design will be described in VHDL. Select Start→Programs→Xilinx

Design Tools →ISE Design Suite14.6 → ISE Design Tools→ ProjectNavigator.
All instructions you can find in the lab № 1.

3.3.3 The example of the multiplexer

28
 A 2-to-1 multiplexer (MUX) has a boolean equation where A and B are the two
inputs, S is the selector input, and Z is the output (fig. 3.1).

Figure 3.1 − MUX 2-to-1

This truth table should make it quite clear that when S = 0 then Z = A but when
S = 1 then Z = B. A straightforward realization of this 2-to-1 multiplexer would need
2 AND gates, an OR gate, and a NOT gate. Symbol z means the state of high
impedance or high resistance on output (break connection).
Larger multiplexers are also common and, as stated above, requires log 2  n 
selector pins for n inputs. Other common sizes are 4-to-1, 8-to-1, and 16-to-1 (fig.
3.2). Since digital logic uses binary values, powers of 2 are used (4, 8, 16) to
maximally control a number of inputs for the given number of selector inputs.

Figure 3.2 − MUX 4-to-1 (a), MUX 8-to-1 (b), MUX 16-to-1 (c)

The boolean equation for a 4-to-1 multiplexer is:

F = A⋅S 0⋅S 1 ∨ B⋅S 0⋅S 1 ∨ C⋅S 0⋅S 1 ∨ D⋅S 0⋅S 1 .
You can easily describe it like a regular switching circuit.
But in this lab we are trying to describe circuits like they are in real hardware.

So, there are several possibilities to describe the same multiplexer. We will
consider couple of them.
− Using conditional concurrent signal assignment.
output_signal <= input_signal_1 when control_signal = “___” else
input_signal_2 when control_signal = “___” else
input_signal_3 when control_signal = “___” else
input_signal_4 when control_signal = “___” else
‘X’;
− Using selected concurrent signal assignment.
with control_signal select
output_signal <= input_signal1 when “___”,
input_signal2 when “___”,
input_signal3 when “___”,
input_signal4 when “___”,
‘X’ when others;

29
 − Using Process Statement and IF Statement to choose the corresponding
output.
process (control_signal) is
begin
if control_signal = “___” then output_signal <= input_signal_1;
elsif control_signal = “___” then output_signal <= input_signal_2;
elsif control_signal = “___” then output_signal <= input_signal_3;
elsif control_signal = “___” then output_signal <= input_signal_4;
else output_signal <=‘X’;
end if;
end process;
− Using Process Statement and CASE Statement to choose the corresponding
output.
process (control_signal) is
begin
case control_signal is
when “___” => output_signal <= input_signal_1;
when “___” => output_signal <= input_signal_2;
when “___” => output_signal <= input_signal_3;
when “___” => output_signal <= input_signal_4;
when others => output_signal <=‘X’;
end case;
end process;

3.3.4 The example of the demultiplexer

A 1-to-2 demultiplexer (DEMUX) has a boolean equation where D is the input,
S is the selector input, and F0 and F1 are outputs (fig. 3.3).

Figure 3.3 − DEMUX 1-to-2

This truth table should make it quite clear that when S = 0 then F0 = D but
when S = 1 then F1 = B. A straightforward realization of this 2-to-1 multiplexer
would need 2 AND gates and a NOT gate. You can easily describe it like a regular
switching circuit.
But in this lab we are trying to describe circuits like they are in real hardware.
So, there are several possibilities to describe the same demultiplexer. We will
consider couple of them.
− Using simple concurrent signal assignment.
output_signal_1 <= input_signal and control_signal and … ;
output_signal_N <= input_signal and control_signal and … ;

30
 − Using Process Statement and IF Statement to choose the corresponding
output.
process (control_signal, input_signal) is
begin
if control_signal = “____” then output_signal_1 <= input_signal;
elsif control_signal = “____” then output_signal_2 <= input_signal;
elsif control_signal = “____” then output_signal_3 <= input_signal;
elsif control_signal = “____” then output_signal_4 <= input_signal;
else output_signal_1 <=’X’;
output_signal_2 <=’X’;
output_signal_3 <=’X’;
output_signal_4 <=’X’;
end if;
end process;
− Using Process Statement and CASE Statement to choose the corresponding
output.
process (control_signal) is
begin
case control_signal is
when “____” => output_signal_1 <= input_signal;
when “____” => output_signal_2 <= input_signal;
when “____” => output_signal_3<= input_signal;
when “____” => output_signal_4 <= input_signal;
when others => NULL;
end case;
end process;

3.3.5 In-lab assignment

 The number of your variant pick up according to the serial number in your
register (table 3.1). The task will contain: type of the circuit – multiplexer
(demultiplexer) and variants of the VHDL description.

Table 3.1 − Variants

№ of
Type of the circuit Variants of description
variant
1 MUX «3 to 1» Using conditional concurrent signal assignment
2 DEMUX «1 to 3» Using simple concurrent signal assignment
3 MUX «4 to 1» Using selected concurrent signal assignment
4 DEMUX «1 to 4» Using Process Statement and CASE Statement
5 MUX «5 to 1» Using Process Statement and IF Statement
6 DEMUX «1 to 5» Using Process Statement and IF Statement
7 MUX «6 to 1» Using Process Statement and CASE Statement
8 DEMUX «1 to 6» Using Process Statement and CASE Statement
9 MUX «7 to 1» Using conditional concurrent signal assignment
10 DEMUX «1 to 7» Using simple concurrent signal assignment

31
Continuation of the table 3.1
11 MUX «8 to 1» Using selected concurrent signal assignment
12 DEMUX «1 to 8» Using Process Statement and IF Statement
13 MUX «3 to 1» Using Process Statement and IF Statement
14 DEMUX «1 to 3» Using Process Statement and CASE Statement
15 MUX «4 to 1» Using Process Statement and CASE Statement

 Create project of the device according to your variant using required types
of the VHDL description. Be sure that you have obtained the truth table for the
circuit according to your variant. Do not forget to draw a block schematic.
 Don’t forget that before implementation you have to create
Implementation constraints file (*. ucf) to identify which FPGA pins are used for
your inputs and outputs variable.
You can use following names of FPGA pins (figl 3.4).

Figure 3.4 − Board pins

If it is necessary, you can declare control signal S like vector:

S: in std_logic_vector (N downto 0), where N − the dimension of this vector.
For example, if numbers of bits for control signal equal 2, then

S: in std_logic_vector (1 downto 0);

Thus, the code for UCF file will adopt the following view:
NET "S(0)" LOC = "L13";
NET "S(1)" LOC = "L14";
 Verify the VHDL models by programming them in Xilinx WebPack.
Check that your devices work as expected and compare them with the truth tables.
Verify each entry. If the VHDL models do not work properly, check and correct
them.
 Record the results in your report.

3.4 Contents of the report

The report has to contain the individual task, the truth table, the Carnaugh map,
the interface with inputs and outputs (block circuit), the VHDL model with comments
and the results of synthesis in WebPack software (RTL circuit).

3.5 Control questions and tasks

1. What is the difference between multiplexer and demultiplexer?

32
 2. VHDL selected and conditional signal assignment?
3. What does the term “std_logic” mean?
4. How to assign pins with constraints for I/Os if the input signal is vector?
5. Write a behavioral code for the given block circuit using different types of
VHDL description.

4 ENCODER/DECODER DESIGN

4.1 Purpose of the work

To understand the usage of different operations for describing the same

functionality. To construct VHDL models of different multiplexing structures.

4.2 Instructions for the independent work organization

Before the work it is necessary to study theoretical material and lecture notes.

4.3 The order of work and guidelines for its implementation

4.3.1 General theory

There are several simple combinational devices, which can be used in real life.
They are multiplexers, demultiplexers (lab № 3), encoders, decoders. The encoder
and decoder are different kind of combinational circuits which are used to convert
binary information to decimal, octal and hexa decimal and vice-versa.
An encoder is a device used to change incoming information into a code. The
code may serve any of a number of purposes such as compressing information for
transmission or storage, encrypting or adding redundancies to the input code, or
translating from one code to another. This is usually done by means of a programmed
algorithm, especially if any part is digital, while most analog encoding is done with
analog circuitry. A decoder, in general, is a device which does the reverse of an
encoder, undoing the encoding so that the original information can be retrieved. The
same method used to encode is usually just reversed in order to decode.

4.3.2 Design entry

The design will be described in VHDL. Select Start→Programs→Xilinx

Design Tools →ISE Design Suite14.6 → ISE Design Tools→ ProjectNavigator.
All instructions you can find in the lab № 1.

4.3.3 The example of the encoder

An encoder is a combinational circuit which is used to convert 2 n inputs to n
outputs. So that it is reverse operation of a decoder (fig. 4.1 )

33
 Figure 4.1 − Block circuit of encoder
For example, the truth table of the encoder with 8 inputs and 3 outputs is shown
in figure 4.2.

Figure 4.2 − Encoder 8-to-3

There are many variant of encoder description. One of them is represented

below:
library ieee;
use ieee.std_logic_1164.all;
entity encdr is
port (D: in std_logic_vector (7 downto 0);
F: out std_logic_vector (2 downto 0));
end encdr;
architecture arch of encdr is begin
process (D) begin
case D is
when ”10000000” => F <="000";
when ”01000000” =>F<="001" ;
when ”00100000” =>F<="010" ;
when ”00010000” =>F<="011";
when ”00001000” =>F<="100";
when ”00000100” =>F<="101";
when ”00000010” =>F<="110";
when ”00000001” =>F<="111";

34
 when others => F<=”000”;
end case;
end process;
end arch;

4.3.4 The example of the decoder

A decoder is a combinational circuit that converts coded inputs to another

coded outputs. A binary decoder has n inputs and a maximum of 2 n outputs. As we
know, an n-bit binary number provides 2n minterms or maxterms. This type of
decoder produces one of the 2n minterms or maxterms at the outputs based on the
input combinations. Let’s take the 2-to-4 decoder as an example, the logic diagram
and the truth table of this decoder is shown in figure 4.3.

Figure 4.3 − 2-to-4 decoder

There are many variant of describing decoders. Two of them are:

1. We use Simple Concurrent 2. We use Process Statement and Conditional
Statement Assignment for each output Statement to choose the corresponding output.
on a base of truth table.
library ieee; library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_1164.all;

entity dec is entity dec2 is

port (A1, A2: in std_logic; port (A: in std_logic_vector (1 downto 0);
D0, D1,D2,D3: out std_logic); D: out std_logic_vector (3 downto 0));
end dec; end dec2;

architecture arch of dec is architecture arch of dec2 is

begin begin
D0<=not (A1) and not (A2); process (A)
D1<=not (A1) and A2; begin
D2<=A1 and not (A2); case A is
D3<=A1 and A2; when “00” => D <=”0001”;
end arch; when “01” =>D<=”0010” ;

35
 when “10” =>D<=”0100”;
when “11” =>D<=”1000”;
when others => D<=”0000”;
end case;
end process;
end arch;

The famous examples of decoders like we already consider are binary n-to-2 n
decoders and seven-segment decoders. Let’s create the VHDL description of the last
one.

3.4.5 An example

You have to design the elevator controller in a building with X floors. For that
purpose you will use a binary code to represent each certain floor (N bits). The
number of 7-segment displays you have to choose according to N.
For example, if a building has X=5 floors, it means that numbers of bits,
required for representation of 5 floors, N=3 bits. Thus, we need only one 7-segment
display to represent numbers of floors from 1 to 5. But if we want to represent
numbers in the way “05”, then we need 2 displays (fig. 4.4).

Figure 4.4 − Code converter

Thus, in the capacity of a code converter you have to use a coder with N inputs
(according to your variant in binary system) and 14 outputs (if you need to use two 7-
segment displays) or 7 outputs (if you need to use only one 7-segment display).
The truth table for code converter when N=5 is shown in the table 4.1.

36
 Table 4.1 − Truth table
Inputs Outputs of 7-segment display №2
A2 A1 A0 DD6 DD5 DD4 DD3 DD2 DD1 DD0
0 0 0 0 1 1 1 1 1 1
0 0 1 0 0 0 0 1 1 0
0 1 0 1 0 1 1 0 1 1
0 1 1 1 0 0 1 1 1 1
1 0 0 1 1 0 0 1 1 0
1 0 1 1 1 0 1 1 0 1

Using Karnaugh map for minimization of each output expression, we will get 7
expressions:
DD 6= A2 A1∨ A2 A1 ; DD 5= A1 A0∨A2 A1 ;
DD 4= A2 A0 ; DD 3= A2 A0∨ A2 A1∨A2 A1 A0 ;
DD 2= A1∨ A1∨A2 A0 ; DD 1=A2∨A2 A0 ;
DD 0=A2 A0∨A2 A1∨ A2 A1 A0 ;

3.4.6 In-lab assignment

 The task will contain: a number of floors (X) and 2 variants of description
(using one of CSAs or one of behavioural operators). PICK UP VARIANTS OF
FLOOR’S NUMBERS and TYPE of DESCRIPTION FROM YOUR
SUPERVISOR!!!
 Create projects of the device according to your variant using VHDL. Be
sure that you have obtained the truth table for the circuit according to you variant and
you have a minimal form of the final output expression. Do not forget to draw a
schematic.
 Verify the VHDL models by programming them in Xilinx WebPack.
Check that your devices work as expected and compare them with the truth tables.
Verify each entry. If the VHDL models do not work properly, check and correct
them.
 Don’t forget that before implementation you have to create implementation
constraints file (*.ucf) to identify which FPGA pins are used for your inputs and
outputs.
 Record the results in your report.

3.5 Contents of the report

The report has to contain the individual task, the truth table, the Carnaugh map,
the interface with inputs and outputs (block circuit), the VHDL model with comments
and the results of synthesis in WebPack software (RTL circuit).

4.5 Control questions and tasks

37
 1. What is the difference between encoder and decoder?
2. What is the difference between minterms or maxterms?
3. What does the term “BCD” mean?
4. What does the term “7-segment display” mean?
5. Write a behavioral code for the given block circuit using different types of
VHDL description.

5 STRUCTURAL TYPE OF VHDL DESCRIPTION

5.1 Purpose of the work

The goal of this lab is to understand the usage of different operations for
describing the same functionality and to construct a structural VHDL model.

5.2 Instructions for the independent work organization

Before the work it is necessary to study theoretical material and lecture notes.

5.3 The order of work and guidelines for its implementation

5.3.1 General theory

There are 3 styles of structurally functional model creation:

− Data Flow description (functional descriptions of components are specified
with usage of concurrent signal assignment statements) - is used for simple
combinational circuits description;
− Procedural description (behavioral models of each component are described
by single or several processes using sequential signal assignment statements) - is
applied for components with complex internal structure, when a usage of Data Flow
style is impossible;
− Structural description (system is represented in terms of the interconnection
of its components instead of focusing on components functionality; behavioral
models of each component are already assumed to exist in the local working
directory).
Several motivations make structural models usage more preferable. They
enable the definition of a precise interface for the sharing of model components
between developers within an organization. Structural models also facilitate the use
of hierarchy and abstraction in modeling complex digital systems. Structural models
are easily integrated with models that use processes and concurrent signal assignment
statements providing a powerful modeling approach for complex digital systems.

5.3.2 Design entry

38
 The design will be described in VHDL. Select Start→Programs→Xilinx
Design Tools →ISE Design Suite14.6 → ISE Design Tools→ ProjectNavigator.
All instructions you can find in the lab № 1.

5.3.4 The example of the combinational circuit design using structural type
of the description.

During combinational circuit synthesis from specified logical function it’s

necessary to write its disjunctive normal form (DNF) or Sum of Products (SOP) from
truth table in form of disjunctions of “1” constituents. Then a minimization by
Carnaugh map and a representation in form of bracket multiplication by methods of
Boolean functions decomposition are accomplished.
The truth table and Carnaugh map for the combinational circuit where Y=1 on
sets (0, 1, 2, 4, 6, 8, 9, 12) is represented in figure 5.1.

Figure 5.1 − Truth table and Carnaugh map for minimization

DNF (SOP) in form of bracket multiplication (Boolean equation form):

F =C D∪ A D∪B C = C D∪ A D∪ C D∪B C  = D C∪ A∪C  D∪B 
Now we can execute combinational circuit synthesis (fig. 5.2).

Figure 5.2 − Logic scheme

Here, we will work with synthesized combinational circuit (look at the scheme)

39
where each gate will be presented as a component with predefined behavior.
Thus, we have to redraw the combinational circuit using structural approach
(fig. 5.3).

Figure 5.3 − The structural model of combinational circuit

Now we have to create a single VHDL-code for description each component.

For this example we will create the VHDL-description of three components (NOT,
AND, OR):
“AND” - component “OR” - component
library IEEE; library IEEE;
use IEEE.std_logic_1164.all; use IEEE.std_logic_1164.all;
entity and_el is entity or_el is
port (x1,x2: in std_logic; port (x1,x2: in std_logic;
y: out std_logic); y: out std_logic);
end and_el; end or_el;
architecture arch of and_el is architecture arch of or_el is
begin begin
y<=x1 and x2; y<=x1 or x2;
end; end;
“NOT” - component
library IEEE;
use IEEE.std_logic_1164.all;
entity not_el is
port (x: in std_logic; y: out std_logic);
end not_el;
architecture arch of not_el is begin
y<=not(x);
end;

Now we can create main program. It’s necessary to declare a component in that
VHDL-model where it will be used. Component declaration is placed in declarative
part of appropriate architecture.
In the following code you can see the component declaration of “NOT”-
element:

40
 component not_el
port (x: in STD_LOGIC;
y: out STD_LOGIC);
end component;

The statement port map defines interconnections of component’s ports with

model’s signals or ports of other components. Format of this statement is following:
LABEL1: COMPONENT_NAME
port map (PORT_NAME of this component =>SIGNAL_NAME of other
component or model,...
PORT_NAME => SIGNAL_NAME ...);
Structural model of our combinational circuit from figure 5.3 is represented
below:
library IEEE;
use IEEE.std_logic_1164.all;
entity comb_circt is The description of entity for
port ( A: in std_logic; combinational circuit.
B: in std_logic;
C: in std_logic;
D: in std_logic;
F: out std_logic );
end comb_circt;
architecture arch of comb_circt is
component not_el is The description of entity for “not”
port ( x: in std_logic; element.
y: out std_logic);
end component;
component or_el is The description of entity for “or”
port ( x1: in std_logic; element.
x2: in std_logic;
y: out std_logic);
end component;
component and_el is The description of entity for “and”
port ( x1: in std_logic; element.
x2: in std_logic;
y: out std_logic);
end component;
signal s1, s2, s3, s4, s5, s6, s7, s8 : std_logic; Creation of temporary signals for
internal lines. In the fig. 5.3 such
lines were marked in red.

41
begin el_1 … el_9 – labels for each
el_1: not_el port map (x=>A, y=>s1); component;
el_2: not_el port map (x=>B, y=>s2); not_el, or_el, and_el – names of
el_3: not_el port map (x=>C, y=>s3); component which coincide with
el_4: not_el port map (x=>D, y=>s4); names of theirs entity.
el_5: or_el port map (x1=>s1, x2=>s3, y=>s5);
In the all port maps for each input-
el_6: or_el port map (x1=>s2, x2=>s4, y=>s6);
output port you have to describe
el_7: and_el port map (x1=>s5, x2=>s4,
y=>s7); explicitly theirs connection with
el_8: and_el port map (x1=>s6, x2=>s3, internal signals.
y=>s8);
el_9: or_el port map (x1=>s7, x2=>s8, y=>F);
end arch;
For example, for first element: el_1: not_el port map (x=>A, y=>s1);
el_1 – label;
not_el – name of the entity of “not” component;
x=>A – according to the fig. 3 we connected input x of “not” element with global
input A of combinational circuit;
y=>s1 – according to the fig. 5.3 we connect output x of “not” element with internal
signal s1 of combinational circuit;

5.3.5 In-lab assignment

 The number of your variant pick up according to the serial number in your
register (table 5.1). For given variant of function write its DNF, minimize it by
Carnaugh map and write its bracket multiplication form. The result of these actions is
minimized Boolean equation.

Table 5.1 − Variants

№ of variant Sets where Y=1
1 0,1,3,5,6,7,15
2 1,2,4,6,7,14
3 3,5,7,8,13,14
4 4,6,8,9,12,13
5 5,7,9,10,11,12
6 6,8,10,11,12,13
7 7,9,11,12,13,14
8 8,10,12,13,14,15
9 0,9,11,13,14,15
10 0,1,10,12,14,15
11 0,2,3,11,13,15
12 0,1,3,12,14,15
13 1,2,4,6,13,15
14 0,2,4,6,9,14,
15 1,6,7,8,9,15

42
  Execute combinational circuit synthesis from minimized Boolean equation.
 Create a model of synthesized combinational circuit in a form of Structural
description.

Figure 5.4 − Main window

 Program the board.

 At the start of next lab you have to hand in a lab report.

5.4 Contents of the report

The report has to contain the individual task, the truth table, the Carnaugh map,
the interface with inputs and outputs (logic circuit), the VHDL model with comments
and the results of synthesis in WebPack software (RTL circuit).

5.5 Control questions and tasks

1. What is the difference between SOP and POS?

2. Three styles of the functional VHDL description?
3. What does the term “component” mean?
4. What does the term “port map” mean?
5. Write a structural code for the given circuit or function.

43
 6 SIMULATION OF LATCHES/FLIP-FLOPS

6.1 Purpose of the work

The goal of this lab is to understand the operation of a sequential circuit, to

construct VHDL model of a sequential circuit and experimentally check the VHDL
model.

6.2 Instructions for the independent work organization

Before the work it is necessary to study theoretical material and lecture notes.

6.3 The order of work and guidelines for its implementation

6.3.1 General theory

So far, we have been looking at the design of combinational circuits. Recall

that the outputs of sequential circuits are dependent on not only their current inputs
(as in combinational circuits), but also on all their past inputs. Because of this
necessity to remember the history of inputs, sequential circuits must contain memory
elements.
In order to remember this history of inputs, sequential circuits must have
memory elements. Memory elements, however, are just like combinational circuits in
the sense that they are made up of the same basic logic gates. What makes them
different is in the way these logic gates are connected together. In order for a circuit
to “remember” its current value, we have to connect the output of a logic gate directly
or indirectly back to the input of that same gate. We call this a feedback loop circuit,
and it forms the basis for all memory elements. Combinational circuits do not have
any feedback loops. Latches and flip-flops are the basic memory elements for storing
information. Hence, they are the fundamental building blocks for all sequential
circuits. A single latch or flip-flop can store only one bit of information. This bit of
information that is stored in a latch or flip-flop is referred to as the state of the latch
or flip-flop. Hence, a single latch or flip-flop can be in either one of two states: 0 or 1.
We say that a latch or a flip-flop changes state when its content changes from a 0 to a
1 or vice versa. This state value is always available at the output. Consequently, the
content of a latch or a flip-flop is the state value, and is always equal to its output
value. The main difference between a latch and a flip-flop is that for a latch, its state
or output is constantly affected by its input as long as its enable signal is asserted. In
other words, when a latch is enabled, its state changes immediately when its input
changes. When a latch is disabled, its state remains constant, thereby, remembering
its previous value. On the other hand, a flip-flop changes state only at the active edge
of its enable signal, i.e., at precisely the moment when either its enable signal rises
from a 0 to a 1 (referred to as the rising edge of the signal), or from a 1 to a 0 (the

44
falling edge). However, after the rising or falling edge of the enable signal, and
during the time when the enable signal is at a constant 1 or 0, the flip-flop’s state
remains constant even if the input changes. In a microprocessor system, we usually
want changes to occur at precisely the same moment. Hence, flip-flops are used more
often than latches, since they can all be synchronized to change only at the active
edge of the enable signal. This enable signal for the flip-flops is usually the global
controlling clock signal. Historically, there are basically four main types of flip-flops:
SR, D, JK, and T. The major differences between them are the number of inputs they
have and how their contents change. Any given sequential circuit can be built using
any of these types of flip-flops (or combinations of them). However, selecting one
type of flip-flop over another type to use in a particular sequential circuit can affect
the overall size of the circuit.
Today, sequential circuits are designed mainly with D flip-flops because of
their ease of use. This is simply a tradeoff issue between ease of circuit design versus
circuit size. Thus, we will focus mainly on the D flip-flop.

6.3.2 Design entry

The design will be described in VHDL. Select Start→Programs→Xilinx

Design Tools →ISE Design Suite14.6 → ISE Design Tools→ ProjectNavigator.
All instructions you can find in the lab № 1.

6.3.3 The example of letches

Latches are known as level-sensitive because their outputs are affected by their
inputs as long as they are enabled. Their memory state can change during this entire
time when the enable signal is asserted.

D latch. Qnext always gets the same value as the input D, and is independent of
the current value of Q. Hence, we obtain the truth table for the D latch, as shown in
figure 6.1(b).

Figure 6.1 – D latch

D latch with enable. The circuit for the D latch with enable (also known as a
gated D latch) is shown in Figure 6.2 (a). The external input becomes the new D
input, the output of the multiplexer is connected to the original D input, and the select
line of the multiplexer is the enable signal E.

45
 When the enable signal E is asserted (E = 1), the external D input passes
through the multiplexer, and so Q next (i.e., the output Q) follows the D input. On the
other hand, when E is de-asserted (E = 0), the current value of Q loops back as the
input to the circuit, and so Q next retains its last value independent of the D input.
When the latch is enabled, the latch is said to be open, and the path from the input D
to the output Q is transparent. In other words, Q follows D. Because of this
characteristic, the D latch with enable circuit is often referred to as a transparent
latch. When the latch is disabled, it is closed, and the latch remembers its current
state.
The truth table and the logic symbol for the D latch with enable are shown in
Figure 6.2 (b) and (c). A sample trace for the operation of the D latch with enable is
shown in Figure 6.2 (d). Between t0 and t1, the latch is enabled with E = 1, so the
output Q follows the input D. Between t1 and t2, the latch is disabled, so Q remains
stable even when D changes.

Figure 6.2 – D latch with enable

6.3.4 The example of the flip-flops

In a computer circuit we do not want the memory state to change at various
times when the enable signal is asserted. Instead, we like to synchronize all of the
state changes to happen at precisely the same moment and at regular intervals. In
order to achieve this, two things are needed: 1) a synchronizing signal, and 2) a
memory circuit that is not level-sensitive. The synchronizing signal, of course, is the
clock, and the non-level-sensitive memory circuit is the flip-flop.
The clock is simply a very regular square wave signal.
We call the edge of the clock signal when it changes from 0 to 1 the rising
edge. Conversely, the falling edge of the clock is the edge when the signal changes
from 1 to 0 (fig. 6.3). We will use the symbol ↑ to denote the rising edge and ↓ for the
falling edge. In a computer circuit, either the rising edge or the falling edge of the
clock can be used as the synchronizing signal for writing data into a memory element.

46
This edge signal is referred to as the active edge of the clock. In all of our examples,
we will use the rising clock edge as the active edge. Therefore, at every rising edge,
data will be clocked or stored into the memory element.
A clock cycle is the time from one rising edge to the next rising edge or from
one falling edge to the next falling edge. The speed of the clock, measured in hertz
(Hz), is the number of cycles per second.
The speed of the clock is determined by how fast a circuit can produce valid
results.

Figure 6.3 – Clock Cycle

D Flip-Flop. Unlike the latch, a flip-flop is not level-sensitive, but rather edge-
triggered. In other words, data gets stored into a flip-flop only at the active edge of
the clock. An edge-triggered D flip-flop achieves this by combining in series a pair
of D latches. Figure 6.4 (a) shows a positive-edge-triggered D flip-flop, where two
D latches are connected in series. A clock signal Clk is connected to the E input of
the two latches: one directly, and one through an inverter.
The first latch is called the master latch. The master latch is enabled when Clk
= 0 because of the inverter, and so QM follows the primary input D. However, the
signal at QM cannot pass over to the primary output Q, because the second latch
(called the slave latch) is disabled when Clk = 0. When Clk = 1, the master latch is
disabled, but the slave latch is enabled so that the output from the master latch, QM,
is transferred to the primary output Q. The slave latch is enabled all the while that
Clk = 1, but its content changes only at the rising edge of the clock, because once Clk
is 1, the master latch is disabled, and the input to the slave latch, QM, will be
constant. Therefore, when Clk = 1 and the slave latch is enabled, the primary output
Q will not change because the input QM is not changing.
The circuit shown in Figure 6.4 (a) is called a positive-edge-triggered D flip-
flop because the primary output Q on the slave latch changes only at the rising edge
of the clock. If the slave latch is enabled when the clock is low (i.e., with the inverter
output connected to the E of the slave latch), then it is referred to as a negative-
edgetriggered flip-flop. The circuit is also referred to as a master-slave D flip-flop
because of the two D latches used in the circuit.
Figure 6.4 (b) shows the operation table for the D flip-flop. The symbol ↑
signifies the rising edge of the clock. When Clk is either at 0 or 1, the flip-flop retains
its current value (i.e., Q next = Q). Q next changes and follows the primary input D only
at the rising edge of the clock. The logic symbol for the positive-edge-triggered D
flip-flop is shown in Figure 6.4 (c). The small triangle at the clock input indicates that
the circuit is triggered by the edge of the signal, and so it is a flip-flop. Without the

47
small triangle, the symbol would be that for a latch. If there is a circle in front of the
clock line, then the flip-flop is triggered by the falling edge of the clock, making it a
negative-edgetriggered flip-flop. Figure 6.4 (d) shows a sample trace for the D flip-
flop. Notice that when Clk = 0, QM follows D, and the output of the slave latch, Q,
remains constant. On the other hand, when Clk = 1, Q follows QM, and the output of
the master latch, QM, remains constant.

Figure 6.4 – D flip-flop

D Flip-Flop with Enable. So far, with the construction of the different

memory elements, it seems like every time we add a new feature we have also lost a
feature that we need. The careful reader will have noticed that, in building the D flip-
flop, we have again lost the most important property of a memory element − it can no
longer remember its current content! At every active edge of the clock, the D flip-flop
will load in a new value. So how do we get it to remember its current value and not
load in a new value?
The answer, of course, is exactly the same as what we did with the D latch, and
that is by adding an enable input, E, through a 2-input multiplexer, as shown in figure
6.5 (a). When E = 1, the primary input D signal will pass to the D input of the flip-
flop, thus updating the content of the flip-flop at the active edge. When E = 0, the
current content of the flip-flop at Q is passed back to the D input of the flip-flop, thus
keeping its current value.
Notice that changes to the flip-flop value occur only at the active edge of the
clock. Here, we are using the rising edge as the active edge. The operation table and
the logic symbol for the D flip-flop with enable is shown in Figure 6.5 (b) and (c)
respectively.

48
 Figure 6.5 – D flip-flop with enable

6.3.5 VHDL for latches and flip-flops

VHDL does not have any explicit object for defining a memory element.
Instead, the semantics of the language provide for signals to be interpreted as a
memory element. In other words, the memory element is declared depending on how
these signals are assigned. Consider the different types of VHDL description of
different triggers (fig. 6.6, 6.7, 6.8).
library IEEE; library IEEE;
use IEEE.std_logic_1164.all; use IEEE.std_logic_1164.all;
entity d_latch_en is
entity rs_latch is port(enable, D: in std_logic;
port(R, S: in std_logic; Q :out std_logic);
Q, nQ :inout std_logic); end d_latch_en;
end rs_latch; architecture beh of d_latch_en is
begin
architecture Beh of rs_latch is process (enable, D)
begin begin
Q<=R nor nQ; if (enable = '1') then Q <= D;
nQ<=S nor Q; end if;
end Beh; end process;
end beh;
Figure 6.6 – RS-latch Figure 6.7 –D latch with enable
(data flow model) (behavioural model)

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity mux is
port(x1,x2,x3: in std_logic; y :out std_logic);
end mux;
architecture Beh of mux is begin
process (x1,x2,x3) begin
if (x3='0') then y<=x1;
else y<=x2;
end if;

49
 end process;
end Beh;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity dff is
port(dd, clk: in std_logic; qq :out std_logic);
end dff;
architecture Beh of dff is begin
process (clk,dd) begin
if (clk'event and clk='1') then qq<=dd;
end if;
end process;
end Beh;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity dff_en is
port(E, D, CLK: in std_logic; Q :inout std_logic);
end dff_en;
architecture Behavioral of dff_en is
component mux is
port(x1,x2,x3: in std_logic; y :out std_logic);
end component;
component dff is
port(dd, clk: in std_logic; qq :out std_logic);
end component;
signal s1:std_logic;
begin
el_1: mux port map(x1=>Q,x2=>D,x3=>E,y=>s1);
el_2: dff port map(dd=>s1, clk=>CLK, qq=>Q);
end Behavioral;
Figure 6.8 –D flip-flop with enable
(structural model)

6.3.6 Principles of simulation in WebPack (only for WebPack 10.1 )

Functional simulation is done before the design is implemented to verify the

logic you have described is correct. This allows a designer to find and fix any bugs in
the design before spending time with subsequent steps. Project Navigator provides
an integrated flow with the ISE Simulator that allows simulations to be run from
Project Navigator.
Steps of simulation:
1. Create a project in the regular manner like you did during previous labs
according to your task. So, you will need *.vhd file!

50
 2. Check your Project Options (figure 6.9) (double click on your project
xc3s500e-5fg320 in the Source window):

Figure 6.9 – Project properties

3. Change the option of sources to Behavioral simulation (fig. 6.10). It will

allow to carry out simulation using either a test program or drawn waveform.

Figure 6.10 – Options of source

4. Create a new file with Test Bench Waveform, save it with the name *_tbw
(fig. 6.11). It will create a new waveform, where you can set you input stimuli by
hand.

51
 Figure 6.11 – New source wizard

Check the information about this new file. If correct, click Finish.

5. After creating the file, you will see the option of inputs types choosing (fig.
6.12). Be careful to choose the right type, and chose the delay. Delays are necessary
for offsetting the time, when you will see the results and the time, when new inputs
will be set.

Figure 6.12 – Initial timing and clock wizard

6. After finishing, you will see the window with prepared timing scale (fig.
6.13).

52
 Figure 6.13 – Timing diagram

You should assign input waveforms ONLY for inputs. Outputs are calculated
automatically. The blue shaded areas that proceed correspond to the Input Setup
Time. Toggle inputs variable to define the input stimulus for the design as follows:
click on the blue cell at 10 ns (for example) to assert first input high ('1'). Then click
on the blue cell at approximately the 20 ns (for example) to assert first input low
('0'). Time you can choose what you want. Repeat this operation for all input signals.
You will get such picture (fig. 6.14).

Figure 6.14 – Inputs assignment

7. Change the tab bottom of the project to Process and Source, like on picture
(fig. 6.15).

Figure 6.15 – Main window

53
 8. Choose the Testbench Waveform source file. You should see the option of
Model Simulation under Xilinx ISE Simulator Property. Press on Simulate
Behavioral Model (fig. 6.16).

Figure 6.16 – Simulation result

9. After finishing simulation, you will see the result of output calculation,
Analyze the results in correspondence to the given inputs (fig. 6.17). For example,

Figure 6.17 – Analysis of RS-latch simulation

54
 NOTE: Starting in 11.1, Xilinx® will no longer support the Test Bench
Waveform Editor. When a project with a test bench waveform (TBW) is upgraded
to 11.1- 14.6, the TBW will be automatically converted to an HDL test bench and
added to the project. Xilinx recommends using HDL test benches for new projects.

6.3.7 In-lab assignment

 The number of your variant pick up according to the serial number in your
register (table 6.1).

Table 6.1 − Variants

№ Type Enable Type Type of
description
1. RS yes latch data flow
2. RS yes flip-flop behavioral
3. RS (negated RS) no latch structural
4. RS (negated RS) no flip-flop behavioral
5. D yes latch structural
6. D no flip-flop structural
7. D no latch data flow
8. D no flip-flop behavioral
9. RS no latch structural
10. RS no flip-flop behavioral
11. RS (negated RS) yes latch behavioral
12. RS (negated RS) yes flip-flop behavioral
13. D yes latch data flow
14. D yes flip-flop behavioral
15. D no latch structural

 For your type of sequential circuit create transition table (truth table) and
do not forget to draw schematic.
 Synthesize your project and check the RTL schematic. If your circuit what
you draw before doesn't match with RTL circuit, try to correct your VHDL-model!
 Verify the VHDL models by simulating them on all possible modes in
Xilinx WebPack. Check that your VHDL model works as expected and compare it
with the truth table given in the pre-lab. Verify each entry. If the VHDL model does
not work properly, check and correct it. When you modify any VHDL file, you
should update the simulator.
 Record the waveforms. You can capture a screen of the waveforms and
save them as a file for insertion in your report.

6.6 Contents of the report

The report has to contain the individual task, the truth table, the Carnaugh map,
the interface with inputs and outputs (block circuit), the VHDL model with

55
comments, the results of synthesis in WebPack software (RTL circuit) and the result
of the simulation.

6.5 Control questions and tasks

1. What is the difference between latch and flip-flop?

2. What does the term “enable signal” mean?
3. What does the term “sequential logic” mean?
4. What is the difference between rising and falling edge?
5. Write the VHDL code for given type of the trigger.

7 COUNTERS AND SHIFTER BASED ON TRIGGER

7.1 Purpose of the work

The goal of this lab is to understand the operation and control of a shifter which
based on trigger, to learn the procedure of behavioral and structural VHDL
description and to develop VHDL model of a n-bit shifter.

7.2 Instructions for the independent work organization

Before the work it is necessary to study theoretical material and lecture notes.

7.3 The order of work and guidelines for its implementation

7.3.1 General theory

A counter is a sequential circuit that – counts. That means it proceeds through a

pre-defined sequence of states where the state of the circuit is determined by the
states of all its flip flops. As every state of the circuit can be given a number we can
say that a counter produces a sequence of numbers.
Shift registers, like counters, are a form of sequential logic. Sequential logic,
unlike combinational logic is not only affected by the present inputs, but also, by the
prior history. In other words, sequential logic remembers past events.
Shift registers produce a discrete delay of a digital signal or waveform. A
waveform synchronized to a clock, a repeating square wave, is delayed by "n"discrete
clock times, where "n" is the number of shift register stages. Thus, a four stage shift
register delays "data in" by four clocks to "data out". The stages in a shift register
are delay stages, typically type "D" Flip-Flops or type "JK" Flip-flops.

56
 7.3.2 Design entry

The design will be described in VHDL. Select Start→Programs→Xilinx

Design Tools →ISE Design Suite14.6 → ISE Design Tools→ ProjectNavigator.
All instructions you can find in the lab № 1.

7.3.3 The example of the shift register

Let's consider a synchronous shift register based on the D-triggers, which

implements the operation of the logical shift to the right. For example, 1100 (12) →
0110 (6). Scheme this register is shown in Fig 7.1.

Figure 7.1 – Shift register based on D- flip-flops

The shift register consists of D-flip-flops with common synchronization (CLK),

and output (Q) of the previous trigger is associated with data input (D) of the next
trigger. In the asynchronous mode if reset = 0 we set register in «0» (reset).
Sequential recording of information to the high bit (signal data) and its shift is carried
out on the rising edge of clock when reset = 1. The truth table is shown in table 7.1.

Table 7.1 − The truth table

RESET CLK DATA Q1 Q2 Q3 Q4
initial
0 X X 0 0 0 0
state
0 0 0 0 0
1 1 0 0 0
shift
1 1 1 1 0 0
0 0 1 1 0
No X 0 1 1 0 storage

Let’s consider two types of the VHDL–code for shift register.

Behavioral description Structural description
library IEEE; library IEEE;
use IEEE.std_logic_1164.all; use IEEE.std_logic_1164.all;
entity D_tr is
entity reg1 is port (Clk : in STD_LOGIC; port (D,Clk,reset :in STD_LOGIC;

57
 data : in STD_LOGIC; Q :out STD_LOGIC);
reset : in STD_LOGIC; end D_tr;
Q1,Q2,Q3,Q4 : out architecture behav of D_tr is
STD_LOGIC); begin
end reg1; process (clk, reset) begin
if (reset ='0' ) then Q<='0';
architecture reg1_arch of reg1 is elsif (clk'event and clk = '1') then Q<= D;
signal sq1,sq2,sq3,sq4: STD_LOGIC; end if;
begin end process;
process (Clk, reset) is end behav;
begin
if ( reset = '0' ) then
sq1 <='0'; sq2<='0'; sq3<='0'; sq4<='0'; library IEEE;
elsif (rising_edge(Clk)) then use IEEE.std_logic_1164.all;
sq1<=data; entity registr is
sq2<=sq1; port (CLK : in STD_LOGIC;
sq3<=sq2; DATA : in STD_LOGIC;
sq4<=sq3; RESET : in STD_LOGIC;
end if; Q1,Q2,Q3,Q4 : out STD_LOGIC);
Q1<=sq1; end registr;
Q2<=sq2;
Q3<=sq3; architecture registr_arch of registr is
Q4<=sq4;
component D_tr
end process; port (D,clk,reset :in STD_LOGIC;
end reg1_arch; Q :out STD_LOGIC);
end component;

signal sq1,sq2,sq3,sq4: STD_LOGIC;

begin
tr1:D_tr port map (D=>DATA, clk=>CLK,
reset=>RESET, Q=>sq1);
tr2:D_tr port map (D=>sq1, clk=>CLK,
reset=>RESET, Q=>sq2);
tr3:D_tr port map (D=>sq2, clk=>CLK,
reset=>RESET, Q=>sq3);
tr4:D_tr port map (D=>sq3, clk=>CLK,
reset=>RESET, Q=>sq4);
Q1<=sq1;
Q2<=sq2;
Q3<=sq3;
Q4<=sq4;
end registr_arch;

The results of simulation will be as it is shown in figure 7.2.

58
 Figure 7.2 – The waveform of the shift register

7.3.4 In-lab assignment

 The number of your variant pick up according to the serial number in your
register (table 7.2). The task will contain: type of the circuit – multiplexer
(demultiplexer) and variants of the VHDL description.

Table 7.2 − Variants

The number Type of
№ Task Description of tasks of outputs VHDL-
description
Shift Similarly to the shift register in Figure 1
register on
1. 3 bits behavioral
the D-flip-
flops
Shift Similarly to the shift register in Figure 1
register on
2. 2 bits behavioral
the D-flip-
flops
Shift Similarly to the shift register in Figure 1
register on
3. 3 bits structural
the D-flip-
flops
Shift Similarly to the shift register in Figure 1
register on
4. 2 bits structural
the D-flip-
flops
Generator Similarly to the shift register in Figure 1,
"running 1" but the output Q4 is connected to the
on the D- input data of the first discharge (DATA).
5. 4 bit behavioral
flip-flops The first trigger sets to "1" when reset=0 ,
and all another triggers sets to "0".

Continuation of the table 7.2

59
 Generator Similarly to the shift register in Figure 1,
"running 0 " but the output Q4 is connected to the input
6. on the D-flip- data of the first discharge (DATA). The 4 bit behavioral
flops first trigger sets to "0" when reset=0 , and
all another triggers sets to "1".
Generator Similarly to the shift register in Figure 1,
"checkerboard but the output Q4 is connected to the input
7. " on the D- data of the first discharge (DATA).The 4 bit behavioral
flip-flops even triggers sets to "0" when reset=0 , and
the odd triggers sets to "1" when reset=0.
Johnson Similarly to the shift register in Figure 1,
counter but the inverting output Q4 is connected
( generator of to the input data of the first discharge
8. 4 bit Behavioral
adjacent code (DATA). The first trigger sets to "1" when
on the D-flip- reset=0 , and all another triggers sets to
flops) "0".
Generator Similarly to the shift register in Figure 1,
"running 1" but the output Q4 is connected to the input
9. on the D-flip- data of the first discharge (DATA). The 4 bit structural
flops first trigger sets to "1" when reset=0 , and
all another triggers sets to "0".
Generator Similarly to the shift register in Figure 1,
"running 0 " but the output Q4 is connected to the input
10. on the D-flip- data of the first discharge (DATA). The 4 bit structural
flops first trigger sets to "0" when reset=0 , and
all another triggers sets to "1".
Generator Similarly to the shift register in Figure 1,
"checkerboard but the output Q4 is connected to the input
11. " on the D- data of the first discharge (DATA).The 4 bit structural
flip-flops even triggers sets to "0" when reset=0 , and
the odd triggers sets to "1" when reset=0.
Johnson Similarly to the shift register in Figure 1,
counter but the inverting output Q4 is connected
( generator of to the input data of the first discharge
12. 4 bit structural
adjacent code (DATA). The first trigger sets to "1" when
on the D-flip- reset=0 , and all another triggers sets to
flops) "0".

 For your type of sequential circuit create truth table; Do not forget to draw
schematics.
 Synthesize your project and check the RTL schematic. If your circuit
what you draw before doesn't match with RTL circuit, try to correct your VHDL-
model!
 Verify the VHDL models by simulating them on all possible modes in
Xilinx WebPack. Check that your VHDL model works as expected and compare it
with the truth table given in the pre-lab. Verify each entry. If the VHDL model does

60
not work properly, check and correct it. When you modify any VHDL file, you
should update the simulator.
 Record the waveforms. You can capture a screen of the waveforms and
save them as a file for insertion in your report.

7.4 Contents of the report

The report has to contain the individual task, the truth table, the Carnaugh map,
the interface with inputs and outputs (block circuit), the VHDL model with
comments, the results of synthesis in WebPack software (RTL circuit) and the result
of the simulation.

7.5 Control questions and tasks

1. What types of shifting do you know?

2. What kind of triggers we can you for shift register design?
3. What does the term “no rising edge” mean?
4. What does the term “initial state” mean?
5. Create the VHDL description of the given types of shift register or counter.

8 FINITE STATE MACHINE

8.1 Purpose of the work

The goal of this lab is to understand the operation of a finite state machine, to
learn the development of a finite state machine, to experimentally check the VHDL
model.

8.2 Instructions for the independent work organization

Before the work it is necessary to study theoretical material and lecture notes.

8.3 The order of work and guidelines for its implementation

8.3.1 General theory

Finite state machine (FSM) or finite state automaton (plural: automata) or

simply a state machine is a model of behaviour composed of a finite number of states,
transitions between those states, and actions.
A state stores information about the past, i.e. it reflects the input changes from
the system start to the present moment. A transition indicates a state change and is
described by a condition that would need to be fulfilled to enable the transition. An
action is a description of an activity that is to be performed at a given moment.

61
 In addition to their use in modeling reactive systems presented here, finite state
automata are significant in many different areas, including electrical engineering,
linguistics, computer science, philosophy, biology, mathematics, and logic.
There are two different groups: Acceptors/Recognizers and Transducers.
Acceptors and recognizers (also sequence detectors) produce a binary output, saying
either yes or no to answer whether the input is accepted by the machine or not. All
states of the FSM are said to be either accepting or not accepting. At the time when
all input is processed, if the current state is an accepting state, the input is accepted;
otherwise it is rejected.
Here is a structural model of the automaton (fig. 8.1).

Figure 8.1 − Structural model of the automaton

Next_state function is named f, output function is named g (fig. 8.2).

Figure 8.2 − Block circuit of the automaton

Outputs are depicted as Z(t), Delay is depicted as ∆.

8.3.2 Design entry

The design will be described in VHDL. Select Start→Programs→Xilinx

Design Tools →ISE Design Suite14.6 → ISE Design Tools→ ProjectNavigator.
All instructions you can find in the lab № 1.

8.3.3 The example of the FSM

The specification is often in the form of a verbal and a graphical description of

the behavior of the circuit. This description needs to be interpreted in order to find a

62
state diagram or state table as the first step of the design procedure. In this section, an
example illustrates the construction of a state diagram for a circuit.
This sequence-recognizing circuit is to have one input X and one output Z. In
addition, it has direct resets on its flip-flops to initialize the state of the circuit to all
zeros. The circuit is to recognize the occurrence of the sequence of bits “1000” on X
by making Z equal to ‘1’ when the previous three inputs to the circuit were “100” and
current input is ‘0’. Otherwise, Z equals ‘0’. The circuit should distinguish the
necessary sequence wherever it occurs in a longer one.
The formulation of any state diagram should allow recognizing the necessary
sequence. It means that there should be states to "remember" something about the
history of past inputs. For the sequence “1000” in order to be able to produce the
output value 1 coincident with the final ‘0’ in the sequence, the circuit must be in a
state that "remembers" that the previous three inputs were “100”. With this concept
in mind, we begin to formulate the state diagram by defining an arbitrary state – say,
A – as the state in which none of the first portion of the sequence to be recognized
has occurred. If ‘1’ occurs on the input, since ‘1’ is the first bit in the sequence, the
event must be "remembered," and the state after the clock pulse cannot be A. So, a
second state B is established to represent the occurrence of the first ‘1’ in the
sequence. Further, to represent the occurrence of the first ‘1’ in the sequence, a
transition is placed from A to B labeled with ‘1’. Since this is not the end of the
sequence “1000”, its output is ‘0’. This initial portion of the state diagram is given in
Figure 8.3 (a).
1/0
A B

(a)
1/0 0/0
A B C

(b)
1/0 0/0 0/0
A B C D

(c)

(d)

63
 (e)
Figure 8.3 – Finding a state diagram for a sequence recognizer

The next bit of the sequence is ‘0’. When this ‘0’ occurs in the state B, a state
is needed to represent the occurrence of a 1 and a 0 in a row at the input. So, a state C
and the associated transition are added, as shown in Figure 8.3 (b). The next bit of the
sequence is ‘0’. When this ‘0’ occurs in the state C, a state is needed to represent the
occurrence of ‘1’ and ‘0’ in a row followed by ‘0’. So, the state D with a transition
having a 0 input and 0 output is added (Figure 8.3 (c)). Since state D represents the
occurrence of “100” as the previous three input bit values, we need the state E to
recognize the last ‘0’ in an input row. Now we are ready to produce the output ‘1’,
because recognizing is completed.
We need five states, since last ‘0’ input cannot be the first bit in the sequence
to be recognized, so we cannot come back to the state A from the state D directly.
In Figure 8.3 (c), all transitions are specified for each state for only one of the
two possible input values. Consider the state A with the ‘0’ input as the first bit in the
sequence. If it is so, we should wait for the input ‘1’. So, we stay in the state A.
Consider the state B. We have already used the transition with ‘0’ as the input.
If we have ‘1’ as the input, this ‘1’ can be the first ‘1’ in the sequence. So, we should
stay in the state B and wait for the next input ‘0’.
Consider the state C. If we have ‘1’ as the input, the current sequence is
canceled and this 1 can be the first in the next recognizing sequence. So, we return to
the state B and wait for the next ‘0’.
The same situation is with the input 1 in the state D. Note that in all considered
transitions the circuit output equals to ‘0’.
Let’s look at the state E. If we are in this state, it means that the current
sequence is already recognized. If the input is ‘1’, then we go to the state B to wait
for the next ‘0’. If the input is ‘0’, then we go to the state A to wait for the first ‘1’ in
the sequence.
Important to note that output in the state E is set to ‘1’, regardless what the next
input will be.

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 The resulting partial state diagram, which completely represents the occurrence
of the sequence to be recognized, is shown in Figure 8.3 (d).
According to the state diagram, we can complete a state table (table 8.1).

Table 8.1 − State table

Current state Input (X) Next state Output (Z)
0 A 0
A
1 B 0
0 C 0
B
1 B 0
0 D 0
C
1 B 0
0 E 0
D
1 B 0
0 A 1
E
1 B 1

Now, we can create the behavioral VHDL-model of Sequence Recognizer.

Code of this model is shown below.
library IEEE;--used library
use IEEE.std_logic_1164.all; -- used package

entity state_machine is
port(reset, clk, x : in std_logic; z : out std_logic); -- input and output signals
end state_machine;

architecture behavioral of state_machine is

type statetype is (A, B, C, D, E); --enumerated type
signal state, next_state :statetype;
begin

output_process: process (state, x) is --process to calculate output value

begin
case state is
when A => if x = '0' then
z <= '0'; else z <= '0'; end if;
when B => if x = '0' then z <= '0';
else z <= '0'; end if;
when C => if x = '1'
then z <= '0'; else z <= '0'; end if;
when D => if x = '0' then
z <= '0'; else z <= '0'; end if;
when E => if x = '0' then
z <= '1'; else z <= '1'; end if;
end case;
end process output_process;

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 next_state_process: process (state, x) is -- process to evaluate next state
begin
case state is
when A => if x = '0' then next_state <= A;
elsif x = '1' then next_state <= B; end if;
when B => if x = '0' then next_state <= C;
elsif x = '1' then next_state <= B; end if;
when C => if x = '0' then next_state <= D;
elsif x = '1' then next_state <= B; end if;
when D => if x= '0' then next_state <= E;
elsif x = '1' then next_state <= B; end if;
when E => if x= '0' then next_state <= A;
elsif x = '1' then next_state <= B; end if;
end case; end process next_state_process;

clk_process: process(reset, clk) is --process to organize storage

begin
if reset = '1' then state <= statetype'left;
elsif rising_edge(clk) then state <= next_state; end if;
end process clk_process;
end architecture behavioral;

The architecture in this description consists of three distinct processes, which

can execute simultaneously and interact via shared signal values.
Process 3 describes the storage of the state. The description is like that
of the positive-edge triggered D flip-flop. Process 1 is the only one of the
three processes that contains storage. The sensitivity list contains clock signal
and reset signal.
Process 2 describes the next state function. The sensitivity list in this
case contains signals X and state. It describes combinational logic to calculate
the next state as the function of previous state and the input value.
Process 1 describes the output function. The same case statement
framework as in Process 2 with state as the expression is used. Instead of
assigning state names to next state, values 0 and 1 are assigned to Z. This
example is a Mealy state machine, in which the output is a function of the
circuit inputs, that’s why the input X appears in the sensitivity list.
Together, the three processes used for the sequence recognizer describe
the state storage, the next state function, and the output function for a
sequential circuit. Since these are all of the components of a sequential circuit
at the state diagram level, the description is complete.
Now we determine the sequence to apply to verify the state diagram
thoroughly.
A sequence that passes through each of the transitions for each input value on
the transition in the state diagram in figure 8.3 is devised to verily that the next state

66
and the output are correct. In addition, at the end of the sequence, the master-reset R
is used to reset flip-flops in the circuit from 1 to 0. The sequence, shown in figure 8.3
(a), applies the values listed for R and X at successive clock cycles. The respective
states and output values, as determined from the state diagram, are also shown.

8.3.4 The features of the simulation

Stimuli on X should be developed according to the design functionality. In this

case we provided reset and clock signals, and some predefined input sequence which
contained the one, the recognized was suppose to “catch”. Simulation is done for
checking functional correctness of the model.
For running the simulation you have to repeat all actions, like in previous labs.
You will see the waveform, BUT WITHOUT THE INTERNAL SIGNAL “STATE”,
it will be difficult to analyze the results of simulation (fig. 8.4)

Figure 8.4 – Waveform of sequence recognizer without state signal

That’s why after first try of simulation you have to repeat the following actions
(fig. 8.5).

Figure 8.5 – Simulation instance and objects

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 Don’t forget to SAVE ALL ( ). After that you have to repeat the
simulation as shown on the picture (fig. 8.6).

Figure 8.6 – Source and processes windows

During the simulation you can see the following message (figure 8.7).

Figure 8.7 – ISE simulator message

Press yes and simulation will continue. The final result you have to analyze and
compare with state table or with state diagram (figure 8.8).

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 Figure 8.8 − A trace of the operation of the state machine

8.3.5 In-lab assignment

 The number of your variant pick up according to the serial number in your
register (table 8.2).

Table 8.2 − Variants

№ Type of sequence
1. 0000
2. 0001
3. 0010
4. 0011
5. 0100
6. 0101
7. 0110
8. 0111
9. 1001
10. 1010
11. 1011
12. 1100
13. 1101
14. 1110
15. 1111

 Create a project of the sequence recognizer according to your variant

using three processes to describe the finite state machine in VHDL. Be sure that you
have obtained the table of transitions for the circuit according to you variant. Draw a
state diagram.
 Verify the VHDL model by simulating them on all possible modes in
Xilinx WebPack. Prove that your circuit recognizes the necessary sequence, and do
not recognize any of the rest.
 Record the waveforms. You can capture a screen of the waveforms and
save them as a file for insertion in your report.

69
 8.4 Contents of the report

The report has to contain the individual task, the state, the state diagram, the
VHDL model with comments and the results simulation.

8.5 Control questions and tasks

1. What does the term “FSM” mean?

2. How many states do you need if you have to recognize 6 bits?
3. What is the deference between state and next_state signal?
4. Draw the state table and diagram for given task.
5. Create a VHDL-description of given Sequence Recognizer.

9 CODE CONVERTERS DESIGN

9.1 Purpose of the work

The goal of this lab is to become familiar with different codes and to learn the
description of such combinational circuit in VHDL.

9.2 Instructions for the independent work organization

Before the work it is necessary to study theoretical material and lecture notes.

9.3 The order of work and guidelines for its implementation

9.3.1 General theory

A symbolic representation of data/ information is called code. The base or radix

of the binary number is 2. Hence, it has two independent symbols. The symbols used
are 0 and 1. A binary digit is called as a bit. A binary number consists of sequence of
bits, each of which is either a 0 or 1. Each bit carries a weight based on its position
relative to the binary point. The weight of each bit position is one power of 2 greater
than the weight of the position to its immediate right. e. g. of binary number is
100011 which is equivalent to decimal number 35.
Numeric codes represent numeric information i.e. only numbers as a series of
0’s and 1’s. Numeric codes used to represent decimal digits are called Binary Coded
Decimal (BCD) codes. A BCD code is one, in which the digits of a decimal number
are encoded-one at a time into group of four binary digits. There are a large number
of BCD codes in order to represent decimal digits 0, 1, 2 …9, it is necessary to use a
sequence of at least four binary digits. Such a sequence of binary digits which
represents a decimal digit is called code word.

70
 The availability of a large variety of codes for the same discrete elements of
information results in the use of different codes by different digital systems. It is
some time necessary to use the output of one system as the input to the other. The
conversion circuit must be inserted between the two systems if each uses different
codes for the same information. Thus a code converter is a circuit that makes the two
systems compatible even though each uses the different code.

9.3.2 Design entry

The design will be described in VHDL. Select Start→Programs→Xilinx

Design Tools →ISE Design Suite14.6 → ISE Design Tools→ ProjectNavigator.
All instructions you can find in the lab № 1.

9.3.3 The example of the code converter

The converter converts the received input codewords to other codewords

recorded from the output. As an example of the converter let’s consider a device that
converts the BCD to the code with the addition of 3 (8421 → 8421+3) (fig. 9.1).
The truth table is showed in figure 9.1.

Figure 9.1 − Truth table

For each output (y1, y2, y3, y4) let’s create a Carnaugh map (fig. 9.2).

71
 Figure 9.2 − Carnaugh map

After minimization we will get the minimal DNF (sum of products, SOP) for
each output:
y1= x1 x3 x4∨x1 x2∨x1 x2x4∨ x1 x2x3 ;
y2=x2 x3 x4∨x2 x4∨ x2 x3 ;
y3= x3 x4∨x3x4 ;
y4=x4 ;
Now we can draw the combinational circuit (fig. 9.3).

Figure 9.3 − Combinational circuit with 4 outputs

You can see the following VHDL template for our design:

72
 Library IEEE;
use IEEE.std_logic_1164.all;
entity converter is
port ( x1,x2,x3,x4: in STD_LOGIC;
y1,y2,y3,y4: out STD_LOGIC );
end converter;
architecture beh of converter is
begin
y1 <= ((not x1) and (not x3) and (not x4)) or (x1 and (not x2)) or ((not x1) and
x4) or ((not x1) and x2 and x3);
y2 <= (x2 and (not x3) and (not x4)) or ( (not x2) and x4 ) or ((not x2) and x3);
y3 <= ( (not x3) and (not x4)) or (x3 and x4) ;
y4 <= x4;
end beh;

9.3.4 In-lab assignment

 The number of your variant pick up according to the serial number in your
register (table 9.1).

Table 9.1 − Variants

convert
№ variant Logic base
from to
1. 8421 8421+5 OR-NOT
2. 8421+2 6421 AND-NOT
3. 8421-5 8421+1 OR-NOT
4. 8421 2421 AND-NOT
5. 6421 2421 OR-NOT
6. 6421 6421+3 AND-NOT
7. 2421 2421+5 OR-NOT
8. 6421 8421-5 AND-NOT
9. 6421+4 8421+1 OR-NOT
10. 8421-2 6421 AND-NOT
11. 8421+6 2421 OR-NOT

 Represent your functions in another logic base, according to your variant.

 Draw the circuitry of your model.
 Run a synthesis of VHDL-model
 Create the ucf-file and run an implementation.
 Program your project.
 Prepare your report.

9.4 Contents of the report

73
 The report has to contain the individual task, the truth table, the Carnaugh map,
the VHDL model with comments and the results of synthesis in WebPack software
(RTL circuit).

9.5 Control questions and tasks

1. What is the difference between combinational and sequential circuit?

2. Simplify Boolean expression using Boolean rules.
3. What is the difference between BCD and 8421 codes?
4. Give the BCD format codes 8421, 7536, 2421 and 5421, respectively for the
following decimal numbers: 9, 12, 6.
5. Create a VHDL description of given code converter using behavioral and
structural styles.

REFERENCES

1. Parhami B. Computer Arithmetic: Algorithms and Hardware Designs / B.

Parhami.– New York: Oxford University Press, 2000.– 490 pp.
2. Brown S. Fundamentals of Digital Logic with VHDL Design /Stephen
Brown, Zvonko Vranesic.– New York:Kluwer Press, 2000.– 767 pp.
3. Hwang K. Computer Arithmetic, Principles, Architecture, and Design /K.
Hwang.– New York, NY: John Wiley & Sons, 1979.– 423 pp.
4. Koren I. Computer Arithmetic Algorithms/Israel Koren. –2nd ed.– Canada:
A.K. Peters Ltd, 2002.– 296 pp.
5. IEEE Standard VHDL Language Reference Manual: ANSI/IEEE Std
1076–1993. – June 1994.–New York : IEEE.
6. Cohen B. VHDL Coding Styles and Methodologies /B.Cohen.–Boston,
MA: Kluwer Academic, 1995.– 455 pp.

74
 Educational edition

GUIDELINES

FOR LABORATORY WORK

by discipline “COMPUTER LOGIC”

for full-time students

of specialty 6.050102 “Computer engineering”

Redactor: Syrevitch Yevgeniya

Kucherenko Dariia

План 2013, поз.

Пiдп. до друку _______ Формат 60×84 1/16. Спосіб друку – ризографія.

Умов.друк.арк. Облiк. – вид.арк Тираж 25 прим.
Зам. № Цiна договiрна.

ХНУРЕ. Україна. 61166 Харків, просп. Леніна, 14

Надруковано в навчально-науковому
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61166 Харків, просп. Леніна, 14