University of Technology Michatronics Branch: Wasan Shakir Mahmood 4 - Stage Supervisor: Layla Hattim

UNIVERSITY OF TECHNOLOGY
MICHATRONICS BRANCH
WASAN SHAKIR MAHMOOD
STAGE_4
Supervisor: Layla Hattim
:Introduction
VHDL is a description language for digital electronic circuits that is used in different
levels of abstraction. The VHDL acronym stands for VHSIC (Very High Speed
Integrated Circuits) Hardware Description Language. This means that VHDL can be
used to accelerate the design process. It is very important to point out that VHDL is
NOT a programming language. Therefore, knowing its syntax does not necessarily
mean being able to designing digital circuits with it. VHDL is an HDL (Hardware
Description Language), which allows describing both asynchronous and synchronous
:circuits. For this purpose, we shall
.Think in terms of gates and flip-flops, not in variables or functions •
.Avoid combinatorial loops and conditional clocks •
Know which part of the circuit is combinatorial and which one is sequential •
?Why to use an HDL
To discover problems and faults in the design before actually implementing it in •

.hardware. • The complexity of an electronic system grows exponentially
For this reason, it is very convenient to build a prototype of the circuit previously to
.its manufacturing process
It makes easy for a team of developers to work together. In particular, VHDL •

allows not only describing the structure of the circuit (description from more simple
sub circuits), but also the specification of the functionality of a circuit using
directives, in a similar way as most standard programming languages do. The most
important aim of an HDL is to be able to simulate the logical behavior of a circuit by
means of a description language that has many similarities with software description
languages. Digital circuits described in VHDL can be simulated using simulation tools
that reproduce the operation of the involved circuit. For this purpose, developers use
a set of rules standardized by the IEEE, which explain the syntax of the language, as
well as how to simulate it. In addition, there are many tools that transform a VHDL
code into a downloadable that can be used to program a reconfigurable device. This
process is named synthesis. The way a given tool carries out the synthesis process is
.very particular, and it greatly differs from what other synthesis tools do
: FPGA IC
Field Programmable Gate Arrays or FPGAs in short are pre-fabricated Silicon devices
that consists of a matrix of reconfigurable logic circuitry and programmable
interconnects arranged in a two-dimensional array. The programmable Logic Cells
can be configured to perform any digital function and the programmable
interconnects (or switches) provide the connections among different logic cells.
Using an FPGA, you can implement any custom design by specifying the logic or
function of each logic block and setting the connection of each programmable
switch. Since this process of designing a custom circuit is done in the field rather
than in a fab, the device is known as “Field Programmable”.
The following image shows a typical internal structure of an FPGA in a very broad
sense.
the core of the FPGA is made up of configurable logic cells and programmable
interconnections. These are surrounded by a number of programmable IO blocks,
.which are used to talk to the external world
Components of an FPGA:
Let us now take a closer look at the structure of an FPGA. Typically, an FPGA
consists of three basic components. They are:
 Programmable Logic Cells (or Logic Blocks) – responsible for implementing

the core logic functions.
 Programmable Routing – responsible for connecting the Logic Blocks.
 IO Blocks – which are connected to the Logic Blocks through the routing and
help to make external connections.
Logic Block:
 The Logic Block in Xilinx based FPGAs are called as Configurable Logic Blocks
or CLB while the similar structures in Altera based FPGAs are called Logic
Array Blocks or LAB. Let us use the term CLB for this discussion. A CLB is the
basic component of an FPGA, which provides both the logic and storage
functionalities. The basic logic block can be anything like a transistor, a NAND
gate, Multiplexors, Look-up Table (LUT), a PAL like structure or even a
processor. Both Xilinx and Altera use Look-up Table (LUT) based logic blocks
to implement the logic as well as the storage functionalities.
 A Logic Block can be made up of a single Basic Logic Element or a set of
interconnected Basic Logic Elements, where a Basic Logic Element is a
combination of a Look-up table (which is in turn made up of SRAM and
Multiplexors) and a Flip-flop.

 A LUT with ‘n’ inputs consists of 2n configuration bits, which are implemented
by SRAM Cells. Using these 2n SRAM Bits, the LUT can be configured to
implement any logical function.
Routing:
If the computational functionality is provided by the Logic Blocks, then the
programmable routing network is responsible for interconnection these logic blocks.
The Routing Network provides interconnections between one logic block to other as
well as between the logic block and the IO Block to completely implement a custom
circuit.
Basically, the routing network consists of connecting wires with programmable

switches, which can be configured using any of the programming technologies.
There are basically two types of routing architectures. They are:
 Island Style Routing (also known as Mesh Routing)
 Hierarchical Routing
In island style routing architecture, the logic blocks are arranged in a two-
dimensional array and are interconnected using a programmable routing network.
This type of routing is widely used in commercial FPGAs.
Many logic blocks are confined to a local set of connections and hierarchical routing
architecture makes use of this feature by dividing the logic blocks into several
groups or clusters. If the logic blocks are residing in the same cluster, then the
hierarchical routing connects them in a low level of hierarchy.
If the logic blocks are residing in different clusters, then wiring is done over a higher
level of hierarchy.
: FPGA KITS
Spartan3AN FPGA Project kit -1
The Spartan3AN FPGA Project kit provides as a powerful, self-contained

development platform for designs targeting the new Spartan-3AN FPGA from Xilinx.
It features a 50K logic gate, on-board USB Programmer, More I/O pins at the 2 sides
of Stick board and 1Mb Internal flash memory, making it the perfect platform to
experiment with any new design.
Also it is crafted to use with breadboard for ease of interfacing .
On- Board Features includes:
 8 Nos. of LED’S
 8-Nos. of DIP switches (Digital Inputs)
 2-Nos. of Push Button (Digital Inputs)
 Reset switch
 USB-UART Port
 2-Channel UART
 48- Pin I/O Connector 2 sides
2-Xilinx Spartan 6 FPGA Board
Most experts advise students and beginners to use this board because it is
affordable and straightforward to use. Some of the features of the development
board include onboard I2C, UART, and a VGA port for serial communications, a PS/2
keyboard port, Switches, eight seven-segment LEDs, twelve single LEDs, and VHDL
sample code.
The development board has incredible English documentation and positive reviews
from different students. In addition, it is a more affordable choice for beginners as
compared to other development boards of the same calibre.
The only setback with the Spartan 6 development board is that it is not compatible
with the Xilinx ISE, which enables users to download programming files to the
development board.
Even though the Xilinx ISE can generate the programming file, it will require another
file downloader to download the data into the development board. Sadly, the
downloader in this development board is also not compatible with FPGA
programming through USB or JTAG cable. As such, they use parallel download
cables, which are the old LPT Port, and JTAG. So, students will have to look for a
computer with LPT port to download files into the development board.
EDGE Spartan 6 FPGA board-3
is the low cost and feature rich development board with Xilinx Spartan 6 FPGA. The FPGA kit
consist of 26 External I/O, USB UART, USB JTAG, WiFi, Bluetooth, SPI FLASH, ADC, DAC,
LCD, 7 segment, VGA, PS2, Buzzer, Temperature Sensor and LDR. It also provides additional
.interface like CMOS Camera and TFT Display at the expansion connectors
EDGE FPGA kit is ready to use Laboratory kit for ECE Curriculum. It can be useful for
.developing basic to intermediate level digital circuits
Advantage of EDGE FPGA kit is easy to implement plenty of applications ranging from
.Wireless control, Image/video Processing, Internet of Things without additional interfaces
:VHDL Programming Example
Priority Encoder-1
entity priority is
port (I : in bit_vector(7 downto 0); --inputs to be prioritised
A : out bit_vector(2 downto 0); --encoded output
GS : out bit); --group signal output
end priority;
architecture v1 of priority is
begin
process (I)
begin
GS <= '1'; --set default outputs
A <= "000";
if I(7) = '1' then
A <= "111";
elsif I(6) = '1' then
A <=elsif I(5) = '1' then
A <= "101";
A <= "100";
A <= "011";
A <= "010";
A <= "001";
A <= "000";
else
GS <= '0';
end if;
end process;
;end v1
Barrel Shifter – entity-2
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
entity bs_vhdl is
port ( datain: in std_logic_vector(31 downto 0);
direction: in std_logic;
rotation : in std_logic;
count: in std_logic_vector(4 downto 0);
dataout: out std_logic_vector(31 downto 0));
;end bs_vhdl
Incrementer - entity-3
library IEEE;
use IEEE.std_logic_unsigned.all;
entity incrementer is
generic (width : integer := 8);
port ( datain: in std_logic_vector(width-1 downto 0);
control: in std_logic;
dataout: out std_logic_vector(width-1 downto 0);
flag: out std_logic);
;end incrementer
4-BCD to 7-Seg Decoder – entity
library IEEE;
use IEEE.std_logic_unsigned.all;
entity DISPLAY_DECODER is
port ( VALUE : in bit_vector(3 downto 0); -- Bit 3 is MSB
ZERO_BLANK : in bit;
DISPLAY : out bit_vector(6 downto 0); -- 7 bit signal
ZERO_BLANK_OUT : out bit);
;end DISPLAY_DECODER
AND gate with internal variable -5
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
ENTITY And_Gate_Variables is
PORT ( A : IN STD_LOGIC;
B : IN STD_LOGIC;
Z : OUT STD_LOGIC);
END ENTITY And_Gate_Variables;
ARCHITECTURE Behavioural OF And_Gate_Variables IS
BEGIN
AndGate_Process: PROCESS(A, B)
VARIABLE Tmp: STD_LOGIC;
BEGIN
Tmp := (A AND B);
Z <= Tmp;
END PROCESS;
;END ARCHITECTURE Behavioural

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UNIVERSITY OF TECHNOLOGY

WASAN SHAKIR MAHMOOD

Supervisor: Layla Hattim

.Think in terms of gates and flip-flops, not in variables or functions •

.Avoid combinatorial loops and conditional clocks •

?Why to use an HDL

To discover problems and faults in the design before actually implementing it in •

It makes easy for a team of developers to work together. In particular, VHDL •

 Programmable Logic Cells (or Logic Blocks) – responsible for implementing

Basically, the routing network consists of connecting wires with programmable

The Spartan3AN FPGA Project kit provides as a powerful, self-contained

Also it is crafted to use with breadboard for ease of interfacing .

On- Board Features includes:

AND gate with internal variable -5

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