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Java Applets Support for an Asynchronous-Mode Learning of Digital Design

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 Java Applets Support for an Asynchronous-Mode Learning of
Digital Design and Test
A. Jutman, A. Sudnitson, R. Ubar H.-D.Wuttke
Department of Computer Engineering Department of Information Technology
Tallinn Technical University Ilmenau Technical University
Raja 15, Tallinn 12618 Ilmenau
ESTONIA GERMANY
alsu@cc.ttu.ee Dieter.Wuttke@theoinf.tu-ilmenau.de

Abstract – A system for teaching design and test of digital The core of the teaching system presented are several
devices and systems at different levels of design flow is Java-applets running on any browser connected to the
presented. The greater part of the system is intended mainly Internet. The use of Java applets can encourage
to illustrate register-transfer level problems in control asynchronous distance learning and thus overcome the
intensive digital systems such as investigation of trade-offs
limitations inherent in traditional instructional techniques.
between the system’s speed and the cost of hardware, control
part decomposition, simulation, fault simulation, test Java applets can help create an interactive environment of
generation, built-in self-test, and some others. A conception “leaning by doing”. Beyond their ability to better convey
of training system for teaching the IEEE 1149.1 Boundary certain concepts, the applets can increase motivation and
Scan standard is presented. The system is implemented in instill greater interest among students [4]-[6].
the form of Java applets and can be freely accessed through The paper is structured as follows. In Section II, we
the Internet. The latter makes it easy for the students to describe the main teaching concept of the system under
improve their learning records using the opportunities of consideration. In Section III, we describe an applet for
asynchronous mode of education via the Internet. teaching principles of Boundary Scan technique important
for SoC design. Section IV is devoted to the register-
I. INTRODUCTION transfer level (RT-level) design and simulation. Section V
describes the applets developed for teaching some
The pace of progress in integrated circuits and system theoretical problems of the finite state machine (FSM)
design has been dictated by the push from application decomposition. Finally, some conclusions are presented.
trends and the pull from technology improvements.
Entering the System-on-a-Chip (SoC) era is a real II. GENERAL TEACHING CONCEPT
challenge for VLSI and system design courses. The more
complex are the electronic systems, the more important We apply the “learning by doing” paradigm in the
are the problems of digital design and test at different Internet-based distance learning taking into account
levels of design flow [1], [2]. To cope with today’s available computer and network resources.
demands, the engineering curricula and learning There are several phases of the learning process
technologies must be constantly updated. supported by the educational system we offer:
The recent years have seen a rapid emergence and § the reading (or listening) phase;
broad acceptance of distance learning technologies. These
technologies can be divided into two categories: § the replication phase (students can use the interactive
synchronous or asynchronous. Both terms describe a type worksheets from any computer connected to the
of communication between the instructor and the learners. Internet and they are able to gain their own
Although synchronous technologies (video experience with the modules);
teleconferencing, online chat and telephone conference § the examination phase (the interactive worksheets are
calls) are very useful, the constraint of real time good summary of problems the solution of which are
communication is very limiting for most distance learners. necessary to the test);
A more attractive alternative is asynchronous distance § the practice phase (the students have to solve digital
learning. Asynchronous distance learning is the form of systems problems; to develop required logic design
distance learning where the communication between the skills they can use the interactive worksheets like a
instructor and the learners is not required to occur in real set of tools supporting several phases of the process).
time. Web-based instruction is the most attractive form of
The learning process initially presents the knowledge of
asynchronous distance learning because it can incorporate
the domain and progressively enhances the learner’s
synchronous and asynchronous technologies [3].
competence in the application of that knowledge in a
In this paper we offer a set of tools which support the
working environment. For each phase, there exists a
learning process in computer engineering area. As they
special application service allowing different views on
are placed on the Web, every student or trainee throughout
actions. To implement the software system’s architecture
the world is able to gain access to these tools. On the one
we should follow four main requirements [4]:
hand, teachers can demonstrate different examples and
1) possibility to run under various operating systems;
procedures of related topics using computer simulated
2) implementation of new modules without changing the
living pictures during their lessons [4]. On the other hand,
rest of the system;
students can use the same simulations on their home
computers. 3) realizing a client-server architecture;
 Fig. 1 Boundary Scan applet main window

4) using the same source to generate worksheets to important standards that have to be taught to future
prevent inconsistency after modifications. designers and test engineers. One of such standards is the
These requirements determine the use the applet IEEE Std 1149.1 “Test Access Port and Boundary-Scan
concept of the Java language. Java is a natural choice of Architecture” developed by Joint Test Action Group
the programming language by the client because of its (JTAG): Interface system between electronic components,
flexibility of Graphic User Interface (GUI) design, assemblies and systems, and external or built-in test
convenient network programming, and platform equipment to provide those components, assemblies and
independence. The latter is especially significant since it systems with testability attributes [8]. A Boundary Scan
allows the same applet program to run on client computers (BS) device manipulation is quite a tricky exercise.
of different platforms. Therefore, only a system, which allows instant simulation
The foundation for the teaching concept presented here and illustration of all the student’s steps can help learning
is a Java applet of a special type, which we call “Living and easy finding all possible mistakes and
Pictures” [4]. Those applets simulate tricky, quite misunderstandings, which otherwise would likely be
complicated situations of the learning subject in a missed out. To learn this complex standard Texas
graphical form on the computer screen. The graphics is Instruments company has developed a training system
self-explanatory and provides interaction possibilities. By called ScanEducator [9].
using these possibilities the students can generate All mentioned advantages of the Java environment are
examples that are interesting enough to encourage their at the same time the advantages of our teaching system
own experiments but not too complicated for learning. against the ScanEducator, which works under DOS only
In our teaching system [7] we succeeded to combine and must be installed locally instead of running over
and illustrate many different problems related to control Internet. Another difference is that ScanEducator has only
intensive digital design and test. a couple of chips to work with, while our system is
provided with a lot of built-in examples. We also decided
III. APPLET FOR LEARNING PRINCIPLES OF to allow users to generate their own examples by creating
BOUNDARY SCAN TECHNIQUE a fully custom chip or board. Moreover, our applet has a
specific fault insertion and diagnosis possibility.
Printed Circuit Boards (PCBs) are the most valuable part The BS architecture implies the introduction of scan
of electronics hardware. Over the years, PCBs have chains in such a way, that each pin of each chip receives
become loaded with more components and hence have an internal control point. The standard defines also the
become increasingly complex and expensive. The testing Test Access Port (TAP) and the TAP Controller [8]. All
of PCBs as an important part of the manufacturing test these structures do not seem that complicated if their
requires new solutions as well. There are some new, very operation is dynamically illustrated.
 Fig. 2. RT-level design applet window

The applet (Fig. 1) allows several working modes: IV. RT-LEVEL DESIGN AND TEST APPLET
§ design/editing of BS structures inside the target chip
using the BSDL language [8]; RT-level is characterized by
§ design/description of the target board that consists of § a digital system is viewed as divided into a data
several chips; subsystem (data-path) and control subsystem
(control-path);
§ simulation of work of TAP Controller, scan register
§ the state of the data-path is defined by the contents of
and other BS registers;
a set of registers;
§ insertion and diagnosis of interconnection faults. § the function of the system is performed as a sequence
In the Edit Board mode, each chip on the board can be of register transfers (in one or more clock cycles);
defined and redefined. New chips can be also created and § a register transfer is a transformation performed on a
inserted. The applet reads the description of BS structures datum while the datum is transferred from one
using Boundary Scan Description Language (BSDL) register to another;
format, which is a part of the standard now. Such BSDL § the sequence of register transfers is controlled by the
descriptions are widely available for free via the Internet. control-path.
This makes the work with the applet easier and more The RT-level design and test applet allows to solve and
exciting, since the student can visualize the operation of illustrate many problems related to RT-level control
many well-known chips with BS available in the market. intensive digital design and test [2].
The latter may be interesting also for test engineers who The range of problems includes:
need to check or debug their BS designs. 1) design of a data-path and control part;
The simulation of the chip’s work can be done in two 2) investigation of trade-offs between speed and
modes. The first one, the TAP Controller Mode, provides hardware cost;
a very detailed illustration of operation of BS registers and 3) RT-level simulation;
the TAP controller. This mode is intended for beginners 4) fault simulation;
and for teachers, helping to understand all the needed 5) test generation;
basics. The other mode, the Command Mode, can be used 6) design for testability and BIST (Built-In Self-Test).
for faster simulation with different predefined input data The system (Fig. 2) consists of the following parts:
and for the fault diagnosis. There is a possibility of § Schematic View panel provides the schematic
random or specific fault insertion. The operation of the representation of the design and the graphical
faulty device can be then simulated and the fault can be simulation data. The structure of the data-path is
diagnosed. reflected there.
 Fig.3. FSM decomposition applet

§ Microprogram table is used to define the control-path architectures are implemented: Logic BIST mode
of the system. During simulation this panel shows based on using random test pattern generator (TPG)
which part of the microprogram is currently executed. and signature analyzer (SA), or Circular BIST mode
§ Simulation and Test tab-panels. based on using combined TPG/SA scan-path register
§ Simulation Results tab-panel is the place where the [8]. Both modes can be implemented in two ways:
results of simulation or test are stored. different settings for each combinational circuit to be
§ Fault simulation module provides fault simulation for tested, or the same setting for all circuits. The aim of
the data path and its units. the student’s work is to find best settings.
§ BIST module provides the basis to experiment with The applet has a flexible design. The RT-level system
embedded self-test facilities. model, shown in Fig. 1 is not mandatory. Should any
other model be used, it must be only specified in a form of
The teaching system is designed to operate in several text-files. Then it can be loaded just as easily as the
working modes: original one.
1) The Design / Simulation mode is used to define data- The applet has a built-in extendable collection of
path (its internal structure is reflected in the examples implementing different algorithms. They help
schematic view) and control-path of the system. The users to understand the principles of the system operation.
control-path, which implements Mealy FSM, is For connecting the system to other applications as well as
defined in the microprogram table. This mode allows for providing users with a possibility to save the results of
to run RT-level fault-free simulation, which can be their work for further use the applet has a data
executed for a single set of input data (step-by-step or import/export capability.
at once) as well as for all the sequence of input
operands at once. In the step-by-step mode each row V. APPLETS FOR CONTROL PART
of the microprogram is executed separately and DECOMPOSITION
results are constantly updated in schematic view
panel. This mode is useful for illustration of the The formal description of the control unit is a FSM which
design work and for debugging. generates control signals to activate different operations in
2) In the Test Mode the applet is capable to perform fault specific clock cycles. FSMs have been widely used also to
simulation of the designed system. The fault express algorithms, communication protocols, digital
simulation can be carried out at both functional and systems, sequential logic circuits, and sequential logic
gate-level. The fault coverage information is provided cells.
both for the whole data path and for each single unit This part of the learning system focuses on a specific
under test. In this mode gate-level schematics for a but comprehensive problem of decomposition of FSMs.
selected unit is displayed, which allows to perform Decomposition has been a classic problem of discrete
manual local test patterns generation. system theory for many years. FSM decomposition is a
3) BIST module provides the basis to experiment with topic that waxes and wanes in importance. The
embedded self-test facilities. Two modes of BIST fundamental works were done in the 1960s. During the
beginning of the VLSI era FSM decomposition became The system is implemented in the form of Java applets
less interesting, and is becoming more important again and can be freely accessed through the Internet. The use
with pervasive use of programmable logic and low power of the web-based media allows individual learning in
applications in digital design. A large hardware behavioral accordance with the students’ own needs. The principal
description is decomposed into several smaller ones. One message of the conception is to inspire students to learn,
goal is to make the synthesis problem more tractable by and to prepare them for developing problem-solving
providing smaller sub-problems that can be solved strategies.
efficiently. Another goal is to create descriptions that can
be synthesized into a structure that meets the design
constraints. In the past, synthesis focused on quality VII. ACKNOWLEDGMENT
measures based on area and performance. The continuing
decrease in feature size and increase in chip density in This work is partially supported by the Thuringian
recent years have given rise to considering decomposition Ministry of Science, Research and Art (project DILDIS),
theory for low power as new dimension of the design by EU V Framework projects (IST-2001-37592 and IST-
process. 2000-30193), and by the Estonian Science Foundation
Theoretical background of our system is the automata (G5643 and G4300).
decomposition theory, which uses partition pair algebra
proposed in [10]. The importance of this theory lies in the VIII. REFERENCES
fact that it provides a direct link between algebraic
relationships and physical realizations of finite state [l] M.L. Bushnell, V.D. Agrawal, Essentials of
machines. The mathematical foundation of this theory Electronic Testing for Digital Memory and Mixed-
rests on algebraization of the concept of “information” in Signal Circuits, Kluwer Academic Publishers,
a machine. It supplies the algebraic formalism necessary Dordrecht: 2000, p. 690.
to study problems pertaining to the flow of this [2] M. Ercegovac, T. Lang, and J. H. Moreno,
information in machines as they operate. As a part of Introduction to Digital Systems, John Wiley & Sons,
engineering mathematics it falls squarely in the NJ: 1999, p. 498.
interdisciplinary area of applied algebra. [3] J. E. Gilbert, Arthur: an Intelligent Tutoring System
The problem of quality-driven synthesis corresponds to with Adaptive Instruction, Ph.D. thesis, University of
the optimal decomposition of a state machine reduced to a Cincinnati, 2000, p. 75.
choice of partitions on the set of states of the prototype [4] R.Ubar, H.-D.Wuttke, "Action Based Learning
machine. Here, we are concerned with solving complex System For Teaching Digital Electronics And Test",
combinatorial tasks arising from the process of design. 3rd European Workshop on Microelectronics
In this part of the learning tool set, different applets for Education" (EWME 2000), Aix-en-Provence, Kluwer
studying the basics of the decomposition theory of FSMs Academic Publishers, May 18-19, 2000, pp. 107-110.
have been developed [7]. The applet on construction of a
FSMs network (Fig. 3) allows experimenting with [5] L. Anido, M. Llamas, and M.J. Fernandez, “Internet-
decomposition of the prototype machine. Different based learning by doing,” IEEE Trans. on Education,
partitions can be chosen to decompose the given FSM to vol. 44, no. 2, May 2001, p. 18.
meet different design restrictions. [6] R.M. Ford, J. Bondzie, and P. Kitcho, “Java applets
The developed set of applets can be used for teaching the for microelektronics education,” IEEE Trans. on
basics of automata theory. Further basic applets in this Education, vol. 44, no. 2, May 2001, p. 10.
area can be found at [11]. [7] Teaching system URL:
http://www.pld.ttu.ee/dildis/automata/applets
VI. CONCLUSION [8] H. Bleeker, P. van den Eijnden, F. de Jong,
Boundary-Scan Test: A Practical Approach, Kluwer
The importance of teaching digital design and test is Academic Publishers, Dordrecht: 1993, p. 225.
increasing with the growing complexity of electronic
systems. [9] Texas Instruments’ Scan Educator URL:
In this paper, we present a conception of how to http://www.ti.com/sc/data/jtag/scanedu.exe
improve the skills of the students studying digital design [10] J. Hartmanis and R. E. Stearns. Algebraic Structure
and test related topics. We apply a learning method based Theory of Sequential Machines, Prentice-Hall, Engl.
on using the so-called “living pictures”. The goal of this Cliffs, 1966, p. 209.
method is to put interactive teaching modules on the [11] Teaching system URL:
Internet so that they can be used in asynchronous-mode http://kauai.theoinf.tu-
learning of digital design and test. ilmenau.de/forschung/projekte/sane/uebersicht_de.htm

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