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    Module of D Flip Flop

    Uploaded by

    Gurdeep Singh
    This document contains code for a D flip-flop module and a test bench module to test the D flip-flop. The D flip-flop module contains an entity with inputs for a data signal, clock signal, and bidirectional outputs for the Q and Q-not signals. The test bench instantiates the D flip-flop module and provides a stimulus process that applies different input patterns to the D and clock signals over time and checks the outputs.

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd

    Module of D Flip Flop

    Uploaded by

    Gurdeep Singh
    34 views11 pages
    This document contains code for a D flip-flop module and a test bench module to test the D flip-flop. The D flip-flop module contains an entity with inputs for a data signal, clock signal, and bidirectional outputs for the Q and Q-not signals. The test bench instantiates the D flip-flop module and provides a stimulus process that applies different input patterns to the D and clock signals over time and checks the outputs.

    Original Description:

    this is a journal entry

    Original Title

    d flip flop

    Copyright

    © © All Rights Reserved

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    This document contains code for a D flip-flop module and a test bench module to test the D flip-flop. The D flip-flop module contains an entity with inputs for a data signal, clock signal, and bidirectional outputs for the Q and Q-not signals. The test bench instantiates the D flip-flop module and provides a stimulus process that applies different input patterns to the D and clock signals over time and checks the outputs.

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    34 views11 pages

    Module of D Flip Flop

    Uploaded by

    Gurdeep Singh
    This document contains code for a D flip-flop module and a test bench module to test the D flip-flop. The D flip-flop module contains an entity with inputs for a data signal, clock signal, and bidirectional outputs for the Q and Q-not signals. The test bench instantiates the D flip-flop module and provides a stimulus process that applies different input patterns to the D and clock signals over time and checks the outputs.

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    of 11

    Module Of d Flip Flop -

    library IEEE;

    use IEEE.STD_LOGIC_1164.ALL;

    entity d2f is

    Port ( d : in STD_LOGIC;

    clk : in STD_LOGIC;

    Q : inout STD_LOGIC;

    Qn : inout STD_LOGIC);

    end d2f;

    architecture Behavioral of d2f is

    SIGNAL A,B: STD_LOGIC;

    begin

    A<= d NAND clk;

    B<= (NOT d)NAND clk;

    Q<=A NAND Qn;

    Qn<=B NAND Q;

    end Behavioral;
    Output -
    Test bench d flip flop -
    LIBRARY ieee;

    USE ieee.std_logic_1164.ALL;

    ENTITY d2fff IS

    END d2fff;

    ARCHITECTURE behavior OF d2fff IS

    COMPONENT d2f

    PORT(

    d : IN std_logic;

    clk : IN std_logic;

    Q : INOUT std_logic;

    Qn : INOUT std_logic

    );

    END COMPONENT;

    --Inputs

    signal d : std_logic := '0';

    signal clk : std_logic := '0';

    --BiDirs
    signal Q : std_logic;

    signal Qn : std_logic;

    BEGIN

    -- Instantiate the Unit Under Test (UUT)

    uut: d2f PORT MAP (

    d => d,

    clk => clk,

    Q => Q,

    Qn => Qn

    );

    -- Clock process definitions

    -- clk_process :process

    -- begin

    -- clk <= '0';

    -- wait for clk_period/2;

    -- clk <= '1';

    -- wait for clk_period/2;

    -- end process;

    -- Stimulus process

    stim_proc: process
    begin

    -- hold reset state for 100 ns.

    wait for 100 ns;

    clk<='0';

    d<='1';

    wait for 100 ns;

    clk<='0';

    d<='0';

    wait for 100 ns;

    clk<='0';

    d<='0';

    wait for 100 ns;

    clk<='1';

    d<='1';

    wait for 100 ns;

    clk<='1';

    d<='0';

    wait for 100 ns;

    clk<='1';

    d<='1';
    wait for 100 ns;

    clk<='1';

    d<='0';

    wait for 100 ns;

    wait;

    end process;

    Output -
    Module Of T Flip Flop -
    library IEEE;

    use IEEE.STD_LOGIC_1164.ALL;

    entity TFF is

    Port ( T : in STD_LOGIC;

    clk : in STD_LOGIC;

    clr : in STD_LOGIC;

    Q : out STD_LOGIC);

    end TFF;

    architecture Behavioral of TFF is

    signal A: STD_LOGIC;
    begin

    process(clk,clr)

    begin

    if clr='1' then

    A<='0';

    elsif (clk='1') then

    if T='0' then

    A<=A;

    elsif T='1' then

    A<=not(A);

    end if;

    end if;

    end process;

    Q<=A;

    end Behavioral;
    Output -

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