Experiment No.

1
AIM: Design the following combinational circuits using VHDL and test the circuits using test
bench and verify them on FPGA platform.
1. Multiplexer
2. Demultiplexer
3. Encoder
4. Decoder
5. Half adder
6. Half subtractor
7. Full adder
8. Full subtractor
VHDL CODE:
MULTIPLEXER:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity mux1 is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : in STD_LOGIC;
d : in STD_LOGIC;
s : in STD_LOGIC_vector(1 downto 0);
y : out STD_LOGIC);
end mux1;
architecture Behavioral of mux1 is
begin
process(s,a,b,c,d)
begin
case s is
when "00"=>y<=a;
when "01"=>y<=b;
when "10"=>y<=c;
when others=>y<=d;
end case;
end process;
end Behavioral;
Test bench:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY mux_tb_vhd IS
END mux_tb_vhd;
ARCHITECTURE behavior OF mux_tb_vhd IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT mux1
PORT( a : IN std_logic;
b : IN std_logic;
c : IN std_logic;
d : IN std_logic;
s : IN std_logic_vector(1 downto 0);
y : OUT std_logic
);
END COMPONENT;
--Inputs
SIGNAL a : std_logic := '0';
SIGNAL b : std_logic := '0';
SIGNAL c : std_logic := '0';
SIGNAL d : std_logic := '0';
SIGNAL s : std_logic_vector(1 downto 0) := (others=>'0');
--Outputs
SIGNAL y : std_logic;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: mux1 PORT MAP(
a => a,
b => b,
c => c,
d => d,
s => s,
y => y
);
tb : PROCESS
BEGIN
-- Wait 100 ns for global reset to finish
wait for 10 ns;
s<="00";
a<='1';
wait for 5 ns;
s<="01";
b<='0';
wait for 5 ns;
s<="10";

c<='1';
wait for 5 ns;
s<="11";
d<='1';
wait for 5 ns;
wait; -- will wait forever
END PROCESS;
END;
Simulation result:

Demux
VHDL code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity demx is
Port ( a : in STD_LOGIC;
s : in STD_LOGIC_vector(1 downto 0);
w : out STD_LOGIC;
x : out STD_LOGIC;
y : out STD_LOGIC;
z : out STD_LOGIC);
end demx;
architecture Behavioral of demx is
begin
process(s,a)
begin
if (s="00")then
w<=a;
elsif(s="01")then
x<=a;
elsif(s="10")then

y<=a;
else
z<=a;
end if;
end process;

end Behavioral;
Test bench:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY demux_tb_vhd IS
END demux_tb_vhd;
ARCHITECTURE behavior OF demux_tb_vhd IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT demx
PORT( a : IN std_logic;
s : IN std_logic_vector(1 downto 0);
w : OUT std_logic;
x : OUT std_logic;
y : OUT std_logic;
z : OUT std_logic);
END COMPONENT;
--Inputs
SIGNAL a : std_logic := '0';
SIGNAL s : std_logic_vector(1 downto 0) := (others=>'0');
--Outputs
SIGNAL w : std_logic;
SIGNAL x : std_logic;
SIGNAL y : std_logic;
SIGNAL z : std_logic;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: demx PORT MAP(
a => a,
s => s,
w => w,
x => x,
y => y,
z => );
tb : PROCESS
BEGIN

-- Wait100ns for global reset to finish

s<="00";
a<='1';
wait for 10 ns;
s<="01";
a<='0';
wait for 10 ns;
s<="10";
a<='0';
wait for 10 ns;
s<="11";
a<='1';
wait for 10 ns;
wait; -- will wait forever
END PROCESS;
END;
Simulation result:

Decoder:
VHDL code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity dec is
Port ( d : in STD_LOGIC_vector(1 downto 0);
en : in STD_LOGIC;
y : out STD_LOGIC_vector(3 downto 0));
end dec;
architecture Behavioral of dec is
begin
process(d,en)
begin
if (en='1')then
case d is
when"00"=>y<="1000";

when"01"=>y<="0100";
when"10"=>y<="0010";
when others=>y<="0001";
end case;
end if;
end process;
end Behavioral;
Test bench:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY dec_tb_vhd IS
END dec_tb_vhd;
ARCHITECTURE behavior OF dec_tb_vhd IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT dec
PORT( d : IN std_logic_vector(1 downto 0);
en : IN std_logic;
y : OUT std_logic_vector(3 downto 0));
END COMPONENT;
--Inputs
SIGNAL en : std_logic := '0';
SIGNAL d : std_logic_vector(1 downto 0) := (others=>'0');
--Outputs
SIGNAL y : std_logic_vector(3 downto 0);
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: dec PORT MAP(
d => d,
en => en,
y => y);
tb : PROCESS
BEGIN
en<='0';
d<="11";
wait for 100 ns;
-- Wait 100 ns for global reset to finish
en<='1';
d<="00";
wait for 100 ns;
d<="01";
wait for 100 ns;

d<="10";
wait for 100 ns;
d<="11";
wait for 100 ns;
-- Place stimulus here
wait; -- will wait forever
END PROCESS;
END;
Simulation result:

Encoder:
VHDL code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity enc is
Port ( d : in STD_LOGIC_vector(3 downto 0);
en : in STD_LOGIC;
y : out STD_LOGIC_vector(1downto 0));
end enc;
architecture Behavioral of enc is
begin
process(en,d)
begin
if(en='1')then
case d is
when "1000"=>y<="00";
when "0100"=>y<="01";
when "0010"=>y<="10";
when "0001"=>y<="11";
when others=>y<="zz";
end case;
end if;

end process;
end Behavioral;
Test bench:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY enc_tb_vhd IS
END enc_tb_vhd;
ARCHITECTURE behavior OF enc_tb_vhd IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT enc
PORT( d : IN std_logic_vector(3 downto 0);
en : IN std_logic;
y : OUT std_logic_vector(1 downto 0));
END COMPONENT;
--Inputs
SIGNAL en : std_logic := '0';
SIGNAL d : std_logic_vector(3 downto 0) := (others=>'0');
--Outputs
SIGNAL y : std_logic_vector(1 downto 0);
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: enc PORT MAP(
d => d,
en => en,
y => y);
tb : PROCESS
BEGIN
en<='1';
d<="1000";
-- Place stimulus here
wait for 50ns;
d<="0100";
wait for 50ns;
d<="0010";
wait for 50ns;
d<="0001";
wait for 50ns;
wait; -- will wait forever
END PROCESS;
END;

Simulation result:

Half adder:
VHDL code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ha is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
sum : out STD_LOGIC;
carry : out STD_LOGIC);
end ha;
architecture Behavioral of ha is
begin
sum <= a xor b;
carry <= a and b;
end Behavioral;
Test bench:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY ha_tb_vhd IS
END ha_tb_vhd;
ARCHITECTURE behavior OF ha_tb_vhd IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT ha
PORT( a : IN std_logic;
b : IN std_logic;
sum : OUT std_logic;

carry : OUT std_logic);

END COMPONENT;
--Inputs
SIGNAL a : std_logic := '0';
SIGNAL b : std_logic := '0';
--Outputs
SIGNAL sum : std_logic;
SIGNAL carry : std_logic;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: ha PORT MAP(
a => a,
b => b,
sum => sum,
carry => carry);
tb : PROCESS
BEGIN
a<='0';
b<='0';
-- Wait 100 ns for global reset to finish
wait for 100 ns;
a<='0';
b<='1';
wait for 100 ns;
a<='1';
b<='0';
wait for 100 ns;
a<='1';
b<='1';
wait for 100 ns;
-- Place stimulus here
wait; -- will wait forever
END PROCESS;
END;
Simulation result:

Half substracter:
VHDL code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity hs is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
diff : out STD_LOGIC;
bor : out STD_LOGIC);
end hs;
architecture Behavioral of hs is
begin
process(a,b)
begin
if(a='0' and b='0')then
diff<='0';
bor<='0';
elsif(a='0' and b='1')then
diff<='1';
bor<='1';
elsif(a='1' and b='0')then
diff<='1';
bor<='0';
else
diff<='0';
bor<='0';
end if;
end process;
end Behavioral;
Test bench:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY hs_tb_vhd IS
END hs_tb_vhd;
ARCHITECTURE behavior OF hs_tb_vhd IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT hs
PORT( a : IN std_logic;

b : IN std_logic;
diff : OUT std_logic;
bor : OUT std_logic);
END COMPONENT;
--Inputs
SIGNAL a : std_logic := '0';
SIGNAL b : std_logic := '0';
--Outputs
SIGNAL diff : std_logic;
SIGNAL bor : std_logic;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: hs PORT MAP(
a => a,
b => b,
diff => diff,
bor => bor);
tb : PROCESS
BEGIN
a<='0';
b<='0';
-- Wait 100 ns for global reset to finish
wait for 100 ns;
a<='0';
b<='1';
wait for 100 ns;
a<='1';
b<='0';
wait for 100 ns;
a<='1';
b<='1';
wait for 100 ns;
wait; -- will wait forever
END PROCESS;
END;
Simulation result:

Full adder:
VHDL code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity fulladd is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
cin : in STD_LOGIC;
sum : out STD_LOGIC;
carry : out STD_LOGIC);
end fulladd;
architecture Behavioral of fulladd is
begin
sum<=a xor b xor cin;
carry<=(a and b) or (b and cin) or (cin and a);
end Behavioral;
Test bench:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY fulladd_tb_vhd IS
END fulladd_tb_vhd;
ARCHITECTURE behavior OF fulladd_tb_vhd IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT fulladd
PORT( a : IN std_logic;
b : IN std_logic;
cin : IN std_logic;
sum : OUT std_logic;
carry : OUT std_logic);
END COMPONENT;
--Inputs
SIGNAL a : std_logic := '0';
SIGNAL b : std_logic := '0';
SIGNAL cin : std_logic := '0';
--Outputs
SIGNAL sum : std_logic;
SIGNAL carry : std_logic;
BEGIN

-- Instantiate the Unit Under Test (UUT)

uut: fulladd PORT MAP(a => a,
b => b,
cin => cin,
sum => sum,
carry => carry);
tb : PROCESS
BEGIN
-- Wait 100 ns for global reset to finish
wait for 10 ns;
a<='0';
b<='0';
cin<='0';
wait for 50 ns;
a<='0';
b<='0';
cin<='1';
wait for 50 ns;
a<='0';
b<='1';
cin<='0';
wait for 50 ns;
a<='0';
b<='1';
cin<='1';
wait for 50 ns;
a<='1';
b<='0';
cin<='0';
wait for 50 ns;
wait; -- will wait forever
END PROCESS;
END;
Simulation result:

Full substracter:
VHDL code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity full_sub is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : in STD_LOGIC;
dif : out STD_LOGIC;
bor : out STD_LOGIC);
end full_sub;
architecture Behavioral of full_sub is
begin
dif<=a xor b xor c;
bor<=((not a)and b) or (b and c) or (c and (not a));
end Behavioral;
Test bench:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY fullsub_tb_vhd IS
END fullsub_tb_vhd;
ARCHITECTURE behavior OF fullsub_tb_vhd IS
COMPONENT full_sub
PORT( a : IN std_logic;
b : IN std_logic;
c : IN std_logic;
dif : OUT std_logic;
bor : OUT std_logic);
END COMPONENT;
--Inputs
SIGNAL a : std_logic := '0';
SIGNAL b : std_logic := '0';
SIGNAL c : std_logic := '0';
--Outputs
SIGNAL dif : std_logic;
SIGNAL bor : std_logic;
BEGIN
-- Instantiate the Unit Under Test (UUT)

uut: full_sub PORT MAP(a => a,

b => b,
c => c,
dif => dif,
bor => bor);
tb : PROCESS
BEGIN
-- Wait 100 ns for global reset to finish
wait for 100 ns;
a<='0';
b<='0';
c<='0';
wait for 50 ns;
a<='0';
b<='0';
c<='1';
wait for 50 ns;
a<='0';
b<='1';
c<='0';
wait for 50 ns;
a<='0';
b<='1';
c<='1';
wait for 50 ns;
a<='1';
b<='0';
c<='0';
wait for 50 ns;
wait; -- will wait forever
END PROCESS;
END;
Simulation result:

Conclusion and observations:

The programs for all the entities are designed and the results are verified on the FPGA.

Experiment No. 2
AIM : Design an eight bit ALU using VHDL and test it on FPGA.
VHDL code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity alu is
Port ( a : in STD_LOGIC_vector(7 downto 0);
b : in STD_LOGIC_vector(7 downto 0);
s : in STD_LOGIC_vector(2 downto 0);
y : out STD_LOGIC_vector(7 downto 0));
end alu;
architecture Behavioral of alu is
begin
process(s)
begin
case s is
when "000"=>y<=a+b;
when "001"=>y<=a-b;
when "010"=>y<=b-a;
when "011"=>y<=a and b;
when "100"=>y<=a or b;
when "101"=>y<=a xor b;
when "110"=>y<=a nor b;
when others=>y<=a nand b;
end case;
end process;
end Behavioral;
Test bench:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY alu_tb_vhd IS
END alu_tb_vhd;
ARCHITECTURE behavior OF alu_tb_vhd IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT alu
PORT( a : IN std_logic_vector(7 downto 0);
b : IN std_logic_vector(7 downto 0);

s : IN std_logic_vector(2 downto 0);

y : OUT std_logic_vector(7 downto 0));
END COMPONENT;
--Inputs
SIGNAL a : std_logic_vector(7 downto 0) := (others=>'0');
SIGNAL b : std_logic_vector(7 downto 0) := (others=>'0');
SIGNAL s : std_logic_vector(2 downto 0) := (others=>'0');
--Outputs
SIGNAL y : std_logic_vector(7 downto 0);
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: alu PORT MAP( a => a,
b => b,
s => s,
y => y);
tb : PROCESS
BEGIN
s<="000";
a<="10011101";
b<="01101011";
-- Wait 100 ns for global reset to finish
wait for 100 ns;
s<="001";
a<="10011101";
b<="01101011";
wait for 100 ns;
s<="010";
a<="10011101";
b<="01101011";
wait for 100 ns;
s<="011";
a<="10011101";
b<="01101011";
wait for 100 ns;
s<="100";
a<="10011101";
b<="01101011";
wait for 100 ns;
s<="101";
a<="10011101";
b<="01101011";
wait for 100 ns;
s<="110";
a<="10011101";
b<="01101011";
wait for 100 ns;

s<="111";
a<="10011101";
b<="01101011";
wait for 100 ns;
wait; -- will wait forever
END PROCESS;
END;
Simulation result:

Conclusion and observations:

The working of ALU is done and the simulations are studied and the results are verified
on FPGA.

Experiment No. 3
AIM : To design all Flip Flops using VHDL and test them on FPGA.
T flip flop:
VHDL code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity tf is
Port ( t : in STD_LOGIC;
reset:in std_logic;
clk : in STD_LOGIC;
q : out STD_LOGIC);
end tf;
architecture Behavioral of tf is
signal x:std_logic;
begin
process(clk,t,reset)
begin
if (reset='1')then
x<='0';
elsif(clk'event and clk='1')then
x<=x;
if(t='1')then
x<=not x;
end if;
end if;
end process;
q<=x;
end Behavioral;
Test bench:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY tff_tb_vhd IS
END tff_tb_vhd;
ARCHITECTURE behavior OF tff_tb_vhd IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT tf
PORT( t : IN std_logic;

reset : IN std_logic;
clk : IN std_logic;
q : OUT std_logic);
END COMPONENT;
--Inputs
SIGNAL t : std_logic := '0';
SIGNAL reset : std_logic := '0';
SIGNAL clk : std_logic := '0';
--Outputs
SIGNAL q : std_logic;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: tf PORT MAP(t => t,
reset => reset,
clk => clk,
q => q);
tb : PROCESS
BEGIN
-- Wait 100 ns for global reset to finish
wait for 100 ns;
t<='0';
reset<='1';
wait for 50 ns;
t<='1';
reset<='0';
wait for 50 ns;
t<='0';
reset<='0';
wait for 50 ns;
t<='1';
reset<='0';
wait for 50 ns;
wait; -- will wait forever
END PROCESS;
clk<=not clk after 25 ns;
END;
Simulation result:

D flip flop:
VHDL code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity df is
Port ( reset : in STD_LOGIC;
clk : in STD_LOGIC;
data : in STD_LOGIC;
q : out STD_LOGIC);
end df;
architecture Behavioral of df is
begin
process(clk,data,reset)
begin
if(reset='0')then
q<='0';
elsif (clk'event and clk='1')then
q<=data;
end if;
end process;
end Behavioral;
Test bench:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY dff_tb_vhd IS
END dff_tb_vhd;
ARCHITECTURE behavior OF dff_tb_vhd IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT df
PORT( reset : IN std_logic;
clk : IN std_logic;
data : IN std_logic;
q : OUT std_logic);
END COMPONENT;
--Inputs
SIGNAL reset : std_logic := '0';
SIGNAL clk : std_logic := '0';

SIGNAL data : std_logic := '0';

--Outputs
SIGNAL q : std_logic;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: df PORT MAP(reset => reset,
clk => clk,
data => data,
q => q);
tb : PROCESS
BEGIN
-- Wait 100 ns for global reset to finish
wait for 100 ns;
data<='1';
reset<='0';
wait for 20 ns;
data<='1';
reset<='1';
wait for 20 ns;
data<='0';
reset<='1';
wait for 20 ns;
data<='1';
reset<='1';
wait for 20 ns;
data<='1';
reset<='1';
wait for 20 ns;
data<='0';
reset<='1';
wait for 20 ns;
wait; -- will wait forever
END PROCESS;
clk<=not clk after 10 ns;
END;
Simulation result:

SR flip flop:
VHDL code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity srff is
Port ( r : in STD_LOGIC;
s : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
q : out STD_LOGIC;
qbar : out STD_LOGIC);
end srff;
architecture Behavioral of srff is
signal q_temp : STD_LOGIC;
begin
process(r,s,clk,rst)
begin
if (rst='1') then
q_temp<='0';
elsif (clk='1' and clk' event) then
if(r='0' and s='0') then
q_temp<=q_temp;
elsif(r='0' and s='1') then
q_temp<='1';
elsif(r='1' and s='0') then
q_temp<='0';
else
q_temp<='X';
end if;
end if;
end process;
q<=q_temp;
qbar<=not q_temp;
end Behavioral;
Test bench :
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY tb_srff_vhd IS

END tb_srff_vhd;
ARCHITECTURE behavior OF tb_srff_vhd IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT srff
PORT( r : IN std_logic;
s : IN std_logic;
clk : IN std_logic;
rst : IN std_logic;
q : OUT std_logic;
qbar : OUT std_logic);
END COMPONENT;
--Inputs
SIGNAL r : std_logic := '0';
SIGNAL s : std_logic := '0';
SIGNAL clk : std_logic := '0';
SIGNAL rst : std_logic := '0';
--Outputs
SIGNAL q : std_logic;
SIGNAL qbar : std_logic;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: srff PORT MAP(r => r,
s => s,
clk => clk,
rst => rst,
q => q,
qbar => qbar);
tb : PROCESS
BEGIN
-- Wait 100 ns for global reset to finish
wait for 100 ns;
rst<='1';
r<='0'; s<='0';
wait for 20 ns;
r<='0'; s<='1';
wait for 20 ns;
r<='1'; s<='0';
wait for 20 ns;
r<='1'; s<='1';
wait for 20 ns;
rst<='0';
r<='0'; s<='0';
wait for 20 ns;
r<='0'; s<='1';
wait for20 ns;

r<='1'; s<='0';
wait for 20 ns;
r<='1'; s<='1';
wait for 20 ns;
r<='1'; s<='0';
wait for 20 ns;
wait; -- will wait forever
END PROCESS;
clk<= not clk after 10 ns;
END;
Simulation result:
JK flip flop:
VHDL code :
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity jkff is
Port ( j : in STD_LOGIC;
k : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
q : out STD_LOGIC;
qbar : out STD_LOGIC);
end jkff;
architecture Behavioral of jkff is
signal q_temp : STD_LOGIC;
begin
process(j,k,clk,rst)
begin
if (rst='1') then
q_temp<='0';
elsif (clk='1' and clk' event) then
if(j='0' and k='0') then
q_temp<=q_temp;
elsif(j='0' and k='1') then
q_temp<='1';
elsif(j='1' and k='0') then
q_temp<='0';
elsif(j='1' and k='1') then
q_temp<=not q_temp;
else
q_temp<='X';

end if;
end if;
end process;
q<=q_temp;
qbar<=not q_temp;
end Behavioral;
TEST BENCH :
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY tb_jkff_vhd IS
END tb_jkff_vhd;
ARCHITECTURE behavior OF tb_jkff_vhd IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT jkff
PORT( j : IN std_logic;
k : IN std_logic;
clk : IN std_logic;
rst : IN std_logic;
q : OUT std_logic;
qbar : OUT std_logic);
END COMPONENT;
--Inputs
SIGNAL j : std_logic := '0';
SIGNAL k : std_logic := '0';
SIGNAL clk : std_logic := '0';
SIGNAL rst : std_logic := '0';
--Outputs
SIGNAL q : std_logic;
SIGNAL qbar : std_logic;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: jkff PORT MAP( j => j,
k => k,
clk => clk,
rst => rst,
q => q,
qbar => qbar);
tb : PROCESS
BEGIN
-- Wait 100 ns for global reset to finish
wait for 100 ns;

rst<='1';
j<='0'; k<='0';
wait for 20 ns;
j<='0'; k<='1';
wait for 20 ns;
j<='1'; k<='0';
wait for 20 ns;
j<='1'; k<='1';
wait for 20 ns;
rst<='0';
j<='0'; k<='0';
wait for 20 ns;
j<='0'; k<='1';
wait for 20 ns;
j<='1'; k<='0';
wait for 20 ns;
j<='1'; k<='1';
wait for 20 ns;
j<='1'; k<='0';
wait for 20 ns;
wait; -- will wait forever
END PROCESS;
clk<= not clk after 10 ns;
END;

Simulation result:

Conclusion and observations:

The flip=flops have been designed and tested on FPGA.

Experiment No. 4
AIM : To design all synchronous and asynchronous counters.
1. Synchronous reset
2. Asynchronous reset
3. Loadable counter
4. Up-down counter
Synchronous reset counter:
VHDL code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity sync_counter is
Port ( reset : in STD_LOGIC;
en : in STD_LOGIC;
clk : in STD_LOGIC;
q : out STD_LOGIC_vector(3 downto 0));
end sync_counter;
architecture Behavioral of sync_counter is
signal temp:std_logic_vector(3 downto 0);
begin
q<=temp(3 downto 0);
process(clk,reset)
begin
if(en='1') then
if (clk'event and clk='1')then
if(reset='1')then
temp <="0000";
else
temp<=temp+1;
end if;
end if;
end if;
end process;
end Behavioral;
Test bench:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY sync_tb_vhd IS
END sync_tb_vhd;

ARCHITECTURE behavior OF sync_tb_vhd IS

-- Component Declaration for the Unit Under Test (UUT)
COMPONENT sync_counter
PORT( reset : IN std_logic;
en : IN std_logic;
clk : IN std_logic;
q : OUT std_logic_vector(3 downto 0));
END COMPONENT;
--Inputs
SIGNAL reset : std_logic := '0';
SIGNAL en : std_logic := '0';
SIGNAL clk : std_logic := '0';
--Outputs
SIGNAL q : std_logic_vector(3 downto 0);
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: sync_counter PORT MAP(reset => reset,
en => en,
clk => clk,
q => q);
clk<=not clk after 25 ns;
tb : PROCESS
BEGIN
-- Wait 100 ns for global reset to finish
en<='0';
wait for 50 ns;
en<='1';
reset<='1';
wait for 50 ns;
en<='1';
reset<='0';
wait for 50 ns;
wait; -- will wait forever
END PROCESS;
END;
Simulation result:

Asynchronous reset counter:

VHDL code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity async_counter is
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
q : out STD_LOGIC_vector(3 downto 0);
en : in STD_LOGIC);
end async_counter;
architecture Behavioral of async_counter is
signal temp:std_logic_vector(3 downto 0);
begin
q<=temp(3 downto 0);
process(clk,reset,en)
begin
if(en='1') then
if(reset='1') then
temp <="0000";
elsif(clk'event and clk='1') then
temp<=temp+1;
end if;
end if;
end process;
end Behavioral;
Test bench:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY async_tb_vhd IS
END async_tb_vhd;
ARCHITECTURE behavior OF async_tb_vhd IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT async_counter
PORT( clk : IN std_logic;
reset : IN std_logic;
en : IN std_logic;
q : OUT std_logic_vector(3 downto 0));

END COMPONENT;
--Inputs
SIGNAL clk : std_logic := '0';
SIGNAL reset : std_logic := '0';
SIGNAL en : std_logic := '0';
--Outputs
SIGNAL q : std_logic_vector(3 downto 0);
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: async_counter PORT MAP(clk => clk,
reset => reset,
q => q,
en => en);
tb : PROCESS
BEGIN
-- Wait 100 ns for global reset to finish
en<='0';
reset<='0';
wait for 50 ns;
en<='1';
reset<='1';
wait for 50 ns;
en<='1';
reset<='0';
wait for 50 ns;
wait; -- will wait forever
END PROCESS;
clk<=not clk after 10 ns;
END;
Simulation result:

Up-down counter:
VHDL code:
library IEEE;

use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity up_down is
Port ( ud : in STD_LOGIC;
clk : in STD_LOGIC;
res : in STD_LOGIC;
en : in STD_LOGIC;
oup : out STD_LOGIC_vector(3 downto 0));
end up_down;
architecture Behavioral of up_down is
signal temp:integer:=0;
begin
Process(clk,res,ud)
begin
if(en='1') then
if(res='1') then
temp<=0;
elsif(clk'event and clk='1') then
if(ud='1') then
temp<=temp+1;
elsif(ud='0') then
temp<=temp-1;
end if;
end if;
end if;
end process;
oup<=conv_std_logic_vector(temp,4);
end Behavioral;
Test bench:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY up_down_tb_vhd IS
END up_down_tb_vhd;
ARCHITECTURE behavior OF up_down_tb_vhd IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT up_down
PORT( ud : IN std_logic;
clk : IN std_logic;
res : IN std_logic;

en : IN std_logic;
oup : OUT std_logic_vector(3 downto 0));
END COMPONENT;
--Inputs
SIGNAL ud : std_logic := '0';
SIGNAL clk : std_logic := '0';
SIGNAL res : std_logic := '0';
SIGNAL en : std_logic := '0';
--Outputs
SIGNAL oup : std_logic_vector(3 downto 0);
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: up_down PORT MAP(ud => ud,
clk => clk,
res => res,
en => en,
oup => oup);
clk<=not clk after 10 ns;
tb : PROCESS
BEGIN
-- Wait 100 ns for global reset to finish
en<='0';
res<='1';
wait for 50 ns;
en<='1';
res<='0';
ud<='1';
wait for 300 ns;
en<='1';
res<='0';
ud<='0';
wait for 50 ns;
wait; -- will wait forever
END PROCESS;
END;
Simulation result:

Lodable counter:
VHDL code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity loadable is
Port ( clk : in STD_LOGIC;
res : in STD_LOGIC;
en : in STD_LOGIC;
load : in STD_LOGIC_VECTOR (3 downto 0);
load_en : in STD_LOGIC;
q : out STD_LOGIC_VECTOR (3 downto 0));
end loadable;
architecture Behavioral of loadable is
signal temp:integer:=0;
begin
Process(clk,res,load_en)
begin
if(en='1') then
if(load_en='1') then
temp<=conv_integer(load);
end if;
if(res='1') then
temp<=0;
elsif(clk'event and clk='1') then
temp<=temp+1;
end if;
end if;
end process;
q<=conv_std_logic_vector(temp,4);
end Behavioral;
Test bench:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY lodable_tb_vhd IS
END lodable_tb_vhd;
ARCHITECTURE behavior OF lodable_tb_vhd IS
-- Component Declaration for the Unit Under Test (UUT)

COMPONENT loadable
PORT( clk : IN std_logic;
res : IN std_logic;
en : IN std_logic;
load : IN std_logic_vector(3 downto 0);
load_en : IN std_logic;
q : OUT std_logic_vector(3 downto 0));
END COMPONENT;
--Inputs
SIGNAL clk : std_logic := '0';
SIGNAL res : std_logic := '0';
SIGNAL en : std_logic := '0';
SIGNAL load_en : std_logic := '0';
SIGNAL load : std_logic_vector(3 downto 0) := (others=>'0');
--Outputs
SIGNAL q : std_logic_vector(3 downto 0);
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: loadable PORT MAP(clk => clk,
res => res,
en => en,
load => load,
load_en => load_en,
q => q);
clk<=not clk after 10 ns;
tb : PROCESS
BEGIN
-- Wait 100 ns for global reset to finish
en<='0';
res<='X';
load_en<='0';
wait for 25 ns;
en<='1';
res<='0';
load_en<='0';
wait for 25 ns;
en<='1';
res<='1';
load_en<='0';
wait for 25 ns;
en<='1';
res<='0';
load_en<='0';
wait for 25 ns;
en<='1';

res<='0';
load_en<='0';
wait for 25 ns;
en<='1';
res<='0';
load_en<='0';
wait for 25 ns;
en<='1';
load_en<='1';
load<="0101";
res<='0';
wait for 25 ns;
en<='1';
res<='0';
load_en<='0';
wait for 25 ns;
en<='1';
res<='0';
load_en<='0';
wait for 25 ns;
en<='1';
res<='0';
load_en<='0';
wait for 25 ns;
en<='1';
res<='0';
load_en<='0';
wait for 25 ns;
en<='1';
res<='0';
load_en<='0';
wait for 25 ns;
en<='1';
res<='0';
load_en<='0';
wait for 25 ns;
en<='1';
res<='0';
load_en<='0';
wait for 25 ns;
-- Place stimulus here
wait; -- will wait forever
END PROCESS;
END;
Simulation result:

Conclusion and observations:

The counters have been tested on FPGA.

Experiment No. 5
AIM : To design barrel shifter using VHDL and Test it on FPGA.
VHDL CODE :
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity barrel_shifter is
Port ( s : in STD_LOGIC_vector(1 downto 0);
a : in STD_LOGIC_vector(3 downto 0);
y : out STD_LOGIC_vector(3 downto 0));
end barrel_shifter;
architecture Behavioral of barrel_shifter is
begin
process(s,a)
begin
case s is
when "00" =>
y <= a;
when "01" =>
y(0) <= a(3);
y(3 downto 1) <= a(2 downto 0);
when "10" =>
y(3 downto 2) <= a(1 downto 0);
y(1 downto 0) <= a(3 downto 2);
when "11" =>
y(2 downto 0) <= a(3 downto 1);
y(3) <= a(0);
when others =>
y <= a;
end case;
end process;
end Behavioral;
Test bench:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY barrel_shifter_tb_vhd IS
END barrel_shifter_tb_vhd;
ARCHITECTURE behavior OF barrel_shifter_tb_vhd IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT barrel_shifter
PORT( s : IN std_logic_vector(1 downto 0);
a : IN std_logic_vector(3 downto 0);
y : OUT std_logic_vector(3 downto 0));
END COMPONENT;
--Inputs
SIGNAL s : std_logic_vector(1 downto 0) := (others=>'0');
SIGNAL a : std_logic_vector(3 downto 0) := (others=>'0');
--Outputs
SIGNAL y : std_logic_vector(3 downto 0);
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: barrel_shifter PORT MAP(s => s,
a => a,
y => y);
tb : PROCESS
BEGIN
a<="1011";
wait for 100 ns;
S<="00";
wait for 100 ns;
S<="01";
wait for 100 ns;
S<="10";
wait for 100 ns;
S<="11";
wait for 100 ns;
a<="1010";
S<="00";
wait for 100 ns;
S<="01";
wait for 100 ns;
S<="10";
wait for 100 ns;
S<="11";
wait for 100 ns;
wait; -- will wait forever
END PROCESS;
END;
Simulation result:

Conclusion and observations:

The Barrel shifter is studied and plotted on FPGA kit.

Experiment No. 6
AIM : To design BCD to Seven Segment Display decoder on FGPA.
VHDL CODE :
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity bcd_sevenseg is
Port ( bcd : in STD_LOGIC_vector(3 downto 0);
seg : out STD_LOGIC_vector(1 to 7));
end bcd_sevenseg;
architecture Behavioral of bcd_sevenseg is
begin
process(bcd)
begin
case bcd is
--abcdefg
when "0000"=>seg<="1111110";
when "0001"=>seg<="0110000";
when "0010"=>seg<="1101101";
when "0011"=>seg<="1111001";
when "0100"=>seg<="0110011";
when "0101"=>seg<="1011011";
when "0110"=>seg<="1011111";
when "0111"=>seg<="1110000";
when "1000"=>seg<="1111111";
when "1001"=>seg<="1110011";
when others=>seg<="-------";
end case;
end process;
end Behavioral;
Test bench:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY bcd_sevenseg_tb_vhd IS
END bcd_sevenseg_tb_vhd;
ARCHITECTURE behavior OF bcd_sevenseg_tb_vhd IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT bcd_sevenseg
PORT( bcd : IN std_logic_vector(3 downto 0);

seg : OUT std_logic_vector(1 to 7));

END COMPONENT;
--Inputs
SIGNAL bcd : std_logic_vector(3 downto 0) := (others=>'0');
--Outputs
SIGNAL seg : std_logic_vector(1 to 7);
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: bcd_sevenseg PORT MAP(bcd => bcd,
seg => seg);
tb : PROCESS
BEGIN
-- Wait 100 ns for global reset to finish
bcd<="0000";
wait for 25 ns;
bcd<="0001";
wait for 25 ns;
bcd<="0010";
wait for 25 ns;
bcd<="0011";
wait for 25 ns;
bcd<="0100";
wait for 25 ns;
bcd<="0101";
wait for 25 ns;
bcd<="0110";
wait for 25 ns;
bcd<="0111";
wait for 25 ns;
bcd<="1000";
wait for 25 ns;
bcd<="1001";
wait for 25 ns;
wait; -- will wait forever
END PROCESS;
END;
Simulation result:

Conclusions and observations:

The seven segment decoder is made and is tested on FPGA.

Experiment No. 7
AIM : To study and design various types of fast adders using structural modelling in VHDL and
test it on FPGA.
VHDL code:
Carry look ahead adder
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity carry_look_ahead is
Port ( a : in STD_LOGIC_vector(7 downto 0);
b : in STD_LOGIC_vector(7 downto 0);
cin : in STD_LOGIC;
sum : out STD_LOGIC_vector(7 downto 0);
carry_out : out STD_LOGIC);
end carry_look_ahead;
architecture Behavioral of carry_look_ahead is
SIGNAL h_sum :STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL carry_generate : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL carry_propagate : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL carry_in_internal : STD_LOGIC_VECTOR(7 DOWNTO 1);
begin
h_sum <=a XOR b;
carry_generate <= a AND b;
carry_propagate <= a OR b;
PROCESS (carry_generate,carry_propagate,carry_in_internal)
BEGIN
carry_in_internal(1) <= carry_generate(0) OR (carry_propagate(0) AND cin);
inst: FOR i IN 1 TO 6 LOOP
carry_in_internal(i+1) <= carry_generate(i) OR (carry_propagate(i) AND
carry_in_internal(i));
END LOOP;
carry_out <= carry_generate(7) OR (carry_propagate(7) AND carry_in_internal(7));
END PROCESS;
sum(0) <= h_sum(0) XOR cin;
sum(7 DOWNTO 1) <= h_sum(7 DOWNTO 1) XOR carry_in_internal(7 DOWNTO 1);
end Behavioral;
Test bench:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;

ENTITY carry_look_ahead_tb_vhd IS
END carry_look_ahead_tb_vhd;
ARCHITECTURE behavior OF carry_look_ahead_tb_vhd IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT carry_look_ahead
PORT( a : IN std_logic_vector(7 downto 0);
b : IN std_logic_vector(7 downto 0);
cin : IN std_logic;
sum : OUT std_logic_vector(7 downto 0);
carry_out : OUT std_logic);
END COMPONENT;
--Inputs
SIGNAL cin : std_logic := '0';
SIGNAL a : std_logic_vector(7 downto 0) := (others=>'0');
SIGNAL b : std_logic_vector(7 downto 0) := (others=>'0');
--Outputs
SIGNAL sum : std_logic_vector(7 downto 0);
SIGNAL carry_out : std_logic;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: carry_look_ahead PORT MAP(a => a,
b => b,
cin => cin,
sum => sum,
carry_out => carry_out);
tb : PROCESS
BEGIN
-- Wait 100 ns for global reset to finish
wait for 100 ns;
a<= "00001111";
b <= "00101100";
cin <= '0';
wait for 50ns;
a<= "11111111";
b <= "11111111";
cin <= '0';
wait for 50ns;
a<= "10001111";
b <= "10101100";
cin <= '0';
wait for 50ns;
a<= "01101101";
b <= "00000100";
cin <= '0';
wait for 50ns;

a<= "01101111";
b <= "11011000";
cin <= '0';
wait for 50ns;
a<= "00110011";
b <= "01011100";
cin <= '0';
wait for 50ns;
wait; -- will wait forever
END PROCESS;
END;
Simulation result:

Conclusion and observations:

The fast adder is made and is tested on FPGA kit.

Experiment No. 8
AIM : Design a Melay and Moore machine on FPGA which detects the sequences 1101 and
1001 for both overlapping and non-overlapping.
Melay 1001
VHDL code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity meal_1001 is
Port ( sequence : in STD_LOGIC;
clk : in STD_LOGIC;
reset : in STD_LOGIC;
oup : out STD_LOGIC);
end meal_1001;
architecture Behavioral of meal_1001 is
type state_t is(start,A,B,C);
signal nxt:state_t;
signal pres:state_t;
begin
process(clk,reset)
begin
if(reset='1') then
pres<=start;
elsif(clk'event and clk='1') then
pres<=nxt;
end if;
end process;
process(pres,sequence)
begin
case pres is
when start=>
if(sequence='1') then
nxt<=A;
oup<='0';
end if;
when A=>
if(sequence='0') then
nxt<=B;
oup<='0';
else
nxt<=A;
oup<='0';
end if;

when B=>
if(sequence='0') then
nxt<=C;
oup<='0';
else
nxt<=A;
oup<='0';
end if;
when C=>
if(sequence='1') then
nxt<=start;
oup<='1';
else
nxt<=start;
oup<='0';
end if;
end case;
end process;
end Behavioral;
Test bench:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY meal_1001_tb_vhd IS
END meal_1001_tb_vhd;
ARCHITECTURE behavior OF meal_1001_tb_vhd IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT meal_1001
PORT( sequence : IN std_logic;
clk : IN std_logic;
reset : IN std_logic;
oup : OUT std_logic);
END COMPONENT;
--Inputs
SIGNAL sequence : std_logic := '0';
SIGNAL clk : std_logic := '0';
SIGNAL reset : std_logic := '0';
--Outputs
SIGNAL oup : std_logic;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: meal_1001 PORT MAP( sequence => sequence,

clk => clk,

reset => reset,
oup => oup);
clk<=not clk after 20 ns;
tb : PROCESS
BEGIN
reset<='0';
sequence<='1';
wait for 25 ns;
reset<='0';
sequence<='1';
wait for 25 ns;
reset<='0';
sequence<='0';
wait for 25 ns;
reset<='0';
sequence<='0';
wait for 25 ns;
reset<='0';
sequence<='1';
wait for 25 ns;
reset<='0';
sequence<='1';
wait for 25 ns;
reset<='0';
sequence<='0';
wait for 25 ns;
reset<='0';
sequence<='1';
wait for 25 ns;
reset<='0';
sequence<='1';
wait for 25 ns;
reset<='0';
sequence<='0';
wait for 25 ns;
-- Place stimulus here
wait; -- will wait forever
END PROCESS;
END;
Simulation result:

Melay 1101
VHDL code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity meal_1101 is
Port ( seq : in STD_LOGIC;
res : in STD_LOGIC;
clk : in STD_LOGIC;
oup : out STD_LOGIC);
end meal_1101;
architecture Behavioral of meal_1101 is
type state_t is(start,A,B,C);
signal nxt:state_t;
signal pres:state_t;
begin
process(clk,res)
begin
if(res='1') then
pres<=start;
elsif(clk'event and clk='1') then
pres<=nxt;
end if;
end process;
process(pres,seq)
begin
case pres is
when start=>
if(seq='1') then

nxt<=A;
oup<='0';
end if;
when A=>
if(seq='1') then
nxt<=B;
oup<='0';
else
nxt<=start;
oup<='0';
end if;
when B=>
if(seq='0') then
nxt<=C;
oup<='0';
else
nxt<=B;
oup<='0';
end if;
when C=>
if(seq='1') then
nxt<=start;
oup<='1';
else
nxt<=start;
oup<='0';
end if;
end case;
end process;
end Behavioral;
Test bench:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY meal_1101_tb_vhd IS
END meal_1101_tb_vhd;
ARCHITECTURE behavior OF meal_1101_tb_vhd IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT meal_1101
PORT( seq : IN std_logic;
res : IN std_logic;
clk : IN std_logic;

oup : OUT std_logic);

END COMPONENT;
--Inputs
SIGNAL seq : std_logic := '0';
SIGNAL res : std_logic := '0';
SIGNAL clk : std_logic := '0';
--Outputs
SIGNAL oup : std_logic;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: meal_1101 PORT MAP(seq => seq,
res => res,
clk => clk,
oup => oup);
clk<= not clk after 20 ns;
tb : PROCESS
BEGIN
res<='1';
seq<='0';
wait for 40 ns;
res<='0';
seq<='1';
wait for 40 ns;
res<='0';
seq<='1';
wait for 40 ns;
res<='0';
seq<='0';
wait for 40 ns;
res<='0';
seq<='1';
wait for 40 ns;
res<='0';
seq<='1';
wait for 40 ns;
res<='0';
seq<='0';
wait for 40 ns;
res<='0';
seq<='1';
wait for 40 ns;
res<='0';
seq<='1';
wait for 40 ns;
res<='0';
seq<='0';

wait for 40 ns;

-- Place stimulus here
wait; -- will wait forever
END PROCESS;
END;
Simulation result:

Moore 1001:
VHDL code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity moore_1001 is
Port ( inp : in STD_LOGIC;
clk : in STD_LOGIC;
res : in STD_LOGIC;
oup : out STD_LOGIC);
end moore_1001;
architecture Behavioral of moore_1001 is
type state_t is(start,A,B,C,D);
signal nxt:state_t;
signal pres:state_t;
begin
process(clk,res)
begin
if(res='1') then
pres<=start;
elsif(clk'event and clk='1') then
pres<=nxt;
end if;

end process;
process(pres,inp)
begin
case pres is
when start=>
if (inp='1') then
nxt<=A;
oup<='0';
else
nxt<=start;
oup<='0';
end if;
when A=>
if(inp='0') then
nxt<=B;
oup<='0';
else
nxt<=A;
oup<='0';
end if;
when B=>
if(inp='0') then
nxt<=C;
oup<='0';
else
nxt<=start;
oup<='0';
end if;
when C=>
if(inp='1') then
nxt<=D;
oup<='0';
else
nxt<=start;
oup<='0';
end if;
when D=>
oup<='1';
end case;
end process;
end Behavioral;
Test bench:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;

USE ieee.numeric_std.ALL;
ENTITY moore_1001_tb_vhd IS
END moore_1001_tb_vhd;
ARCHITECTURE behavior OF moore_1001_tb_vhd IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT moore_1001
PORT( inp : IN std_logic;
clk : IN std_logic;
res : IN std_logic;
oup : OUT std_logic);
END COMPONENT;
--Inputs
SIGNAL inp : std_logic := '0';
SIGNAL clk : std_logic := '0';
SIGNAL res : std_logic := '0';
--Outputs
SIGNAL oup : std_logic;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: moore_1001 PORT MAP(inp => inp,
clk => clk,
res => res,
oup => oup);
clk<=not clk after 20 ns;
tb : PROCESS
BEGIN
res<='1';
inp<='0';
wait for 40 ns;
res<='0';
inp<='1';
wait for 40 ns;
res<='0';
inp<='0';
wait for 40 ns;
res<='0';
inp<='0';
wait for 40 ns;
res<='0';
inp<='1';
wait for 40 ns;
wait; -- will wait forever
END PROCESS;
END;

Simulation result:

Moore 1101
VHDL code
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity moore_1101 is
Port ( inp : in STD_LOGIC;
clk : in STD_LOGIC;
res : in STD_LOGIC;
oup : out STD_LOGIC);
end moore_1101;
architecture Behavioral of moore_1101 is
type state_t is(start,A,B,C,D);
signal nxt:state_t;
signal pres:state_t;
begin
process(clk,res)
begin
if(res='1') then
pres<=start;

elsif(clk'event and clk='1') then

pres<=nxt;
end if;
end process;
process(pres,inp)
begin
case pres is
when start=>
if (inp='1') then
nxt<=A;
oup<='0';
else
nxt<=start;
oup<='0';
end if;
when A=>
if(inp='1') then
nxt<=B;
oup<='0';
else
nxt<=start;
oup<='0';
end if;
when B=>
if(inp='0') then
nxt<=C;
oup<='0';
else
nxt<=B;
oup<='0';
end if;
when C=>
if(inp='1') then
nxt<=D;
oup<='0';
else
nxt<=start;
oup<='0';
end if;
when D=>
oup<='1';
end case;
end process;
end Behavioral;

Test bench:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY moore_1101_tb_vhd IS
END moore_1101_tb_vhd;
ARCHITECTURE behavior OF moore_1101_tb_vhd IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT moore_1101
PORT( inp : IN std_logic;
clk : IN std_logic;
res : IN std_logic;
oup : OUT std_logic);
END COMPONENT;
--Inputs
SIGNAL inp : std_logic := '0';
SIGNAL clk : std_logic := '0';
SIGNAL res : std_logic := '0';
--Outputs
SIGNAL oup : std_logic;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: moore_1101 PORT MAP(inp => inp,
clk => clk,
res => res,
oup => oup);
clk<= not clk after 20 ns;
tb : PROCESS
BEGIN
res<='1';
inp<='0';
wait for 40 ns;
res<='0';
inp<='1';
wait for 40 ns;
res<='0';
inp<='1';
wait for 40 ns;
res<='0';
inp<='0';
wait for 40 ns;
res<='0';
inp<='1';

wait for 40 ns;

wait; -- will wait forever
END PROCESS;
END;
Simulation result:

Conclusion and observations:

The moore and mealey machines for the sequences 1001 and 1101 are designed and
tested on FPGA.

Experiment No. 9
AIM : To design PIPO,SIPO,SIPO,SISO circuits using VHDL and test it on FPGA.
VHDL code:
PIPO:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity pipo is
Port ( a : in STD_LOGIC_vector(3 downto 0);
res : in STD_LOGIC;
en : in STD_LOGIC;
clk : in STD_LOGIC;
y : out STD_LOGIC_vector(3 downto 0));
end pipo;
architecture Behavioral of pipo is
signal op:std_logic_vector(3 downto 0);
begin
process(clk, res)
begin
if(res = '0') then
op <= "0000";
elsif(clk'event and clk = '1') then
if (en = '1') then
op <=a;
end if;
end if;
END PROCESS;
y<=op;
end Behavioral;
Test bench:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY pipo_tb_vhd IS
END pipo_tb_vhd;
ARCHITECTURE behavior OF pipo_tb_vhd IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT pipo
PORT( a : IN std_logic_vector(3 downto 0);

res : IN std_logic;
en : IN std_logic;
clk : IN std_logic;
y : OUT std_logic_vector(3 downto 0));
END COMPONENT;
--Inputs
SIGNAL res : std_logic := '0';
SIGNAL en : std_logic := '0';
SIGNAL clk : std_logic := '0';
SIGNAL a : std_logic_vector(3 downto 0) := (others=>'0');
--Outputs
SIGNAL y : std_logic_vector(3 downto 0);
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: pipo PORT MAP(a => a,
res => res,
en => en,
clk => clk,
y => y);
clk<=not clk after 20 ns;
tb : PROCESS
BEGIN
res<='0';
en<='0';
a<="1010";
wait for 40 ns;
res<='1';
en<='1';
a<="0101";
wait for 40 ns;
res<='1';
en<='1';
a<="1100";
wait for 40 ns;
wait; -- will wait forever
END PROCESS;
END;
Simulation result:

PISO:
VHDL code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity piso is
Port ( a : in STD_LOGIC_vector(3 downto 0);
clk : in STD_LOGIC;
res : in STD_LOGIC;
en : in STD_LOGIC;
ldr : in STD_LOGIC;
y : out STD_LOGIC);
end piso;
architecture Behavioral of piso is
signal op:std_logic_vector(3 downto 0);
begin
process(clk, Res)
begin
if(Res = '0') then
op <= "0000";
elsif(clk'event and clk = '1') then
if(ldr='1') then
op <= a;
end if;
if (en = '1') then
op(3 downto 1) <= op(2 downto 0);
op <= a;
end if;
end if;

END PROCESS;
y<=op(3);
end Behavioral;
Test bench:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY piso_tb_vhd IS
END piso_tb_vhd;
ARCHITECTURE behavior OF piso_tb_vhd IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT piso
PORT( a : IN std_logic_vector(3 downto 0);
clk : IN std_logic;
res : IN std_logic;
en : IN std_logic;
ldr : IN std_logic;
y : OUT std_logic);
END COMPONENT;
--Inputs
SIGNAL clk : std_logic := '0';
SIGNAL res : std_logic := '0';
SIGNAL en : std_logic := '0';
SIGNAL ldr : std_logic := '0';
SIGNAL a : std_logic_vector(3 downto 0) := (others=>'0');
--Outputs
SIGNAL y : std_logic;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: piso PORT MAP(a => a,
clk => clk,
res => res,
en => en,
ldr => ldr,
y => y);
clk<=not clk after 20 ns;
tb : PROCESS
BEGIN
a<="1010";
res<='0';
en<='0';
ldr<='0';

wait for 40 ns;

a<="1100";
res<='1';
en<='0';
ldr<='0';
wait for 40 ns;
a<="1100";
res<='1';
ldr<='1';
en<='1';
wait for 40 ns;
res<='0';
wait; -- will wait forever
END PROCESS;
END;
Simulation result:

SIPO:
VHDL code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity sipo is
Port ( a : in STD_LOGIC;
clk : in STD_LOGIC;
res : in STD_LOGIC;
en : in STD_LOGIC;
y : out STD_LOGIC_vector(3 downto 0));
end sipo;
architecture Behavioral of sipo is

signal op:std_logic_vector(3 downto 0);

begin
process(clk, res)
begin
if(res = '0') then
op <= "0000";
elsif(clk'event and clk = '1') then
if (en = '1') then
op(3 downto 1) <= op(2 downto 0);
op(0) <=a;
end if;
end if;
END PROCESS;
y<=op;
end Behavioral;
Test bench:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY sipo_tb_vhd IS
END sipo_tb_vhd;
ARCHITECTURE behavior OF sipo_tb_vhd IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT sipo
PORT( a : IN std_logic;
clk : IN std_logic;
res : IN std_logic;
en : IN std_logic;
y : OUT std_logic_vector(3 downto 0));
END COMPONENT;
--Inputs
SIGNAL a : std_logic := '0';
SIGNAL clk : std_logic := '0';
SIGNAL res : std_logic := '0';
SIGNAL en : std_logic := '0';
--Outputs
SIGNAL y : std_logic_vector(3 downto 0);
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: sipo PORT MAP(a => a,
clk => clk,
res => res,

en => en,
y => y);
clk<=not clk after 20 ns;
tb : PROCESS
BEGIN
a<='1';
res<='0';
en<='0';
wait for 40 ns;
a<='1';
res<='1';
en<='1';
wait for 40 ns;
res<='0';
a<='1';
res<='0';
en<='1';
wait for 40 ns;
wait; -- will wait forever
END PROCESS;
END;
Simulation result:

SISO:
VHDL CODE:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity siso is
Port ( a : in STD_LOGIC;
clk : in STD_LOGIC;

res : in STD_LOGIC;
en : in STD_LOGIC;
y : out STD_LOGIC);
end siso;
architecture Behavioral of siso is
signal op:std_logic;
begin
process(clk, Res)
begin
if(Res = '0') then
op <= '0';
elsif(clk'event and clk = '1') then
if (en = '1') then
--op(3 downto 1) <= op(2 downto 0);
op<=a;
end if;
end if;
y<=op;
END PROCESS;
end Behavioral;
Test bench:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY siso_tb_vhd IS
END siso_tb_vhd;
ARCHITECTURE behavior OF siso_tb_vhd IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT siso
PORT( a : IN std_logic;
clk : IN std_logic;
res : IN std_logic;
en : IN std_logic;
y : OUT std_logic);
END COMPONENT;
--Inputs
SIGNAL a : std_logic := '0';
SIGNAL clk : std_logic := '0';
SIGNAL res : std_logic := '0';
SIGNAL en : std_logic := '0';
--Outputs

SIGNAL y : std_logic;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: siso PORT MAP( a => a,
clk => clk,
res => res,
en => en,
y => y);
clk<=not clk after 20 ns;
tb : PROCESS
BEGIN
a<='1';
res<='0';
en<='0';
wait for 40 ns;
a<='1';
res<='1';
en<='0';
wait for 40 ns;
a<='1';
res<='1';
en<='1';
wait for 40 ns;
a<='0';
res<='1';
en<='1';
wait for 40 ns;
wait; -- will wait forever
END PROCESS;
END;
Simulation result:

Conclusion and observations:

The different shift registers are studied and tested on FPGA.

Experiment No. 11
AIM : To design a RAM in one dimensional and two dimensional in VHDL style.
VHDL code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ram1d is
Port ( data : inout STD_LOGIC_vector(7 downto 0);
rd : in STD_LOGIC;
wr : in STD_LOGIC;
chip_sel : in STD_LOGIC;
address : in STD_LOGIC_vector(7 downto 0));
end ram1d;
architecture Behavioral of ram1d is
type ram_array is array(0 to 255) of std_logic_vector(7 downto 0);
signal ram:ram_array;
begin
data<=ram(conv_integer(address)) when rd='1' and chip_sel='1' else "00000000";
ram(conv_integer(address))<=data when wr='1' and chip_sel='1' else"00000000";
end Behavioral;
Test bench:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY ram1d_tb_vhd IS
END ram1d_tb_vhd;
ARCHITECTURE behavior OF ram1d_tb_vhd IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT ram1d
PORT( rd : IN std_logic;
wr : IN std_logic;
chip_sel : IN std_logic;
address : IN std_logic_vector(7 downto 0);
data : INOUT std_logic_vector(7 downto 0));
END COMPONENT;
--Inputs
SIGNAL rd : std_logic := '0';
SIGNAL wr : std_logic := '0';
SIGNAL chip_sel : std_logic := '0';

SIGNAL address : std_logic_vector(7 downto 0) := (others=>'0');

--BiDirs
SIGNAL data : std_logic_vector(7 downto 0);
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: ram1d PORT MAP(data => data,
rd => rd,
wr => wr,
chip_sel => chip_sel,
address => address);
tb : PROCESS
BEGIN
chip_sel<='0' ; wait for 50 ns ;
chip_sel<='1'; wait for 50 ns ;
wr<='1'; wait for 50 ns ;
rd<='0' ; wait for 50 ns ;
data <="01010101" ;wait for 50 ns ;
chip_sel<='1' ; wait for 50 ns ;
wr<='0'; wait for 50 ns ;
rd<='1' ; wait for 50 ns ;
address <="00001111" ;wait for 50 ns ;
wait; -- will wait forever
END PROCESS;
END;
Simulation Result:

Conclusion and observations:

The 1D RAM is studied and tested.

Experiment No. 12
AIM : To writhe VHDL code for IO read and Write.
VHDL code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity fulladder is
Port ( inp: in STD_LOGIC_VECTOR(2 downto 0);
sum : out STD_LOGIC;
cout : out STD_LOGIC);
end fulladder;
architecture Behavioral of fulladder is
begin
sum<=inp(0) xor inp(1) xor inp(2);
cout<=(inp(0) and inp(1)) or (inp(2) and inp(0)) or (inp(1) and inp(2));
end Behavioral;

Test bench:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
use std.textio.all;
ENTITY tb_textio_vhd IS
END tb_textio_vhd;
ARCHITECTURE behavior OF tb_textio_vhd IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT fulladder is
Port ( inp : in STD_LOGIC_VECTOR(2 downto 0);
sum : out STD_LOGIC;
cout : out STD_LOGIC);
end COMPONENT;
FUNCTION str2vec(str : string) RETURN std_logic_vector IS
VARIABLE vtmp: std_logic_vector(str'RANGE);
BEGIN
FOR i IN str'RANGE LOOP
IF str(i) = '1' THEN
vtmp(i) := '1';

ELSIF str(i) = '0' THEN

vtmp(i) := '0';
ELSE
vtmp(i) := 'X';
END IF;
END LOOP;
RETURN vtmp;
END str2vec;
--Inputs
SIGNAL inp : std_logic_vector(2 downto 0);
--Outputs
SIGNAL sum : std_logic;
SIGNAL cout : std_logic;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut:fulladder PORT MAP(inp => inp,
sum=>sum,
cout=>cout);
read_input: process
file c_file_handle: text;
variable C: line;
variable cont: string(1 to 3);
begin
wait for 100 ns;
file_open(c_file_handle, "test_file.txt", READ_MODE);
while not endfile(c_file_handle) loop
readline(c_file_handle, C) ;
read(C,cont);
inp <= str2vec(cont);
wait for 100ns;
end loop;
file_close(c_file_handle);
end process;
END;
Simulation result:

Conclusion and observations:

The text IO is made and is tested on a file and the output is verified.

Experiment No. 13
AIM : To design an arbiter on FPGA.
VHDL code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity arbiter is
Port ( req1 : in STD_LOGIC;
req2 : in STD_LOGIC;
req3 : in STD_LOGIC;
gnt1 : out STD_LOGIC;
gnt2 : out STD_LOGIC;
gnt3 : out STD_LOGIC;
reset : in STD_LOGIC;
clk : in STD_LOGIC);
end arbiter;
architecture Behavioral of arbiter is
type state_t is(idle,s1,s2,s3);
signal state:state_t;
begin
process(clk,reset)
begin
if(reset='1') then
state<=idle;
gnt1<='0';gnt2<='0';gnt3<='0';
elsif(clk'event and clk='1') then
case state is
when idle=>
if(req1='1') then
gnt1<='1';
state<=s1;
elsif(req1='0' and req2='1') then
gnt2<='1';
state<=s2;
elsif(req1='0' and req2='0' and req3='1') then
gnt3<='1';
state<=s3;
end if;
when s1=>
if(req1='0') then
gnt1<='0';
state<=idle;
end if;

when s2=>
if(req2='0') then
gnt2<='0';
state<=idle;
end if;
when s3=>
if(req3='0') then
gnt3<='0';
state<=idle;
end if;
end case;
end if;
end process;
end Behavioral;
Test Bench:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY arbiter_tb_vhd IS
END arbiter_tb_vhd;
ARCHITECTURE behavior OF arbiter_tb_vhd IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT arbiter
PORT( req1 : IN std_logic;
req2 : IN std_logic;
req3 : IN std_logic;
reset : IN std_logic;
clk : IN std_logic;
gnt1 : OUT std_logic;
gnt2 : OUT std_logic;
gnt3 : OUT std_logic);
END COMPONENT;
--Inputs
SIGNAL req1 : std_logic := '0';
SIGNAL req2 : std_logic := '0';
SIGNAL req3 : std_logic := '0';
SIGNAL reset : std_logic := '0';
SIGNAL clk : std_logic := '0';
--Outputs
SIGNAL gnt1 : std_logic;
SIGNAL gnt2 : std_logic;
SIGNAL gnt3 : std_logic;

BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: arbiter PORT MAP(req1 => req1,
req2 => req2,
req3 => req3,
gnt1 => gnt1,
gnt2 => gnt2,
gnt3 => gnt3,
reset => reset,
clk => clk);
tb : PROCESS
BEGIN
reset<='1';
req1<='1';
req2<='0';
req3<='1';
wait for 10 ns;
reset<='0';
req1<='1';
req2<='1';
req3<='1';
wait for 10 ns;
reset<='0';
req1<='0';
req2<='0';
req3<='1';
wait for 20 ns;
reset<='0';
req1<='0';
req2<='1';
req3<='0';
wait for 25 ns;
wait; -- will wait forever
END PROCESS;
clk<=not clk after 10 ns;
END;
Simulation result:

Conclusion and observations:

The arbiter circuit is designed and result is shown by simulation window. The same is
tested it on FPGA.

Experiment No 14
Aim: To study different types of Multipliers.
VHDL Code
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity multip is
Port ( x : in STD_LOGIC_VECTOR (2 downto 0);
y : in STD_LOGIC_VECTOR (2 downto 0);
p : out STD_LOGIC_VECTOR (5 downto 0));
end multip;
architecture Behavioral of multip is
component and_2 is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
y : out STD_LOGIC);
end component;
component fa is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
ci:in std_logic;
sum : out STD_LOGIC;
cout: out STD_LOGIC);
end component;
signal z1,z2,z3,z4,z5,z6,z7,z8:std_logic;
signal c1,c2,c3,c4,c5:std_logic;
signal s1,s2:std_logic;
begin
u1: and_2 port map(a=>x(0),b=>y(0),y=>p(0));
u2: and_2 port map(a=>x(0),b=>y(1),y=>z1);
u3: and_2 port map(a=>x(1),b=>y(0),y=>z2);
u4: and_2 port map(a=>x(0),b=>y(2),y=>z3);
u5: and_2 port map(a=>x(1),b=>y(1),y=>z4);
u6: and_2 port map(a=>x(2),b=>y(0),y=>z5);
u7: and_2 port map(a=>x(1),b=>y(2),y=>z6);
u8: and_2 port map(a=>x(2),b=>y(1),y=>z7);
u9: and_2 port map(a=>x(2),b=>y(2),y=>z8);
u10: fa port map(a=>z1,b=>z2,ci=>'0',sum=>P(1),cout=>c1);
u11: fa port map(a=>z3,b=>z4,ci=>c1,sum=>s1,cout=>c2);
u12: fa port map(a=>s1,b=>z5,ci=>'0',sum=>P(2),cout=>c3);
u13: fa port map(a=>z6,b=>z7,ci=>c2,sum=>s2,cout=>c4);
u14: fa port map(a=>'0',b=>s2,ci=>c3,sum=>P(3),cout=>c5);

u15: fa port map(a=>z8,b=>c3,ci=>c5,sum=>P(4),cout=>P(5));

end Behavioral;
Test Bench:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
use std.textio.all;
ENTITY tb_textio_vhd IS
END tb_textio_vhd;
ARCHITECTURE behavior OF tb_textio_vhd IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT multip
PORT( x : IN std_logic_vector(2 downto 0);
y : IN std_logic_vector(2 downto 0);
p : OUT std_logic_vector(5 downto 0));
END COMPONENT;
FUNCTION str2vec(str : string) RETURN std_logic_vector IS
VARIABLE vtmp: std_logic_vector(str'RANGE);
BEGIN
FOR i IN str'RANGE LOOP
IF str(i) = '1' THEN
vtmp(i) := '1';
ELSIF str(i) = '0' THEN
vtmp(i) := '0';
ELSE
vtmp(i) := 'X';
END IF;
END LOOP;
RETURN vtmp;
END str2vec;
--Inputs
SIGNAL x : std_logic_vector(2 downto 0) := (others=>'0');
SIGNAL y : std_logic_vector(2 downto 0) := (others=>'0');
--Outputs
SIGNAL p : std_logic_vector(5 downto 0);
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: multip PORT MAP(x => x,
y => y,
p => p);
read_input: process
file c_file_handle: text;
variable C: line;
variable cont: string(1 to 7);
begin
wait for 100 ns;
file_open(c_file_handle, "test_file.txt", READ_MODE);

while not endfile(c_file_handle) loop

readline(c_file_handle, C) ;
read(C,cont);
x <= str2vec(cont(1 to 3));
y <=str2vec(cont(5 to 7));
wait for 100ns;
end loop;
file_close(c_file_handle);
end process;
END;
Simulation Result: