TD VHDL

Exercice 1 :
1)
S1 = NOT (A XOR B)
S2 = NOT D OR (C AND D)
S = S2 AND (E XOR S1)
2) Proposer un code VHDL du circuit ci-dessus en utilisant une description Flot de
donnés

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity MU_FLOT is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
C : in STD_LOGIC;
D : in STD_LOGIC;
E : in STD_LOGIC;
S1 : inout STD_LOGIC;
S2 : inout STD_LOGIC;
S : out STD_LOGIC);
end MU_FLOT;
architecture Behavioral of MU_FLOT is
begin
S1 <= NOT(A XOR B);
S2 <= NOT D OR (C AND D);
S <= S2 AND (E XOR S1);

end Behavioral;
3) Donner le code VHDL qui décrit le fonctionnement du circuit ci-dessus en utilisant
l’instruction d’assignation sélective <CASE>.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity MU_CASE is
Port ( AB : in STD_LOGIC_VECTOR(1 downto 0);
CD : in STD_LOGIC_VECTOR(1 downto 0);
E : in STD_LOGIC;
Se : inout STD_LOGIC_VECTOR(1 downto 0);
S : out STD_LOGIC);
end MU_CASE;
architecture Behavioral of MU_CASE is
begin
PROCMU1 : PROCESS(AB, CD, Se)
begin
CASE AB is
WHEN "00"=>Se(0)<= '1';
WHEN "11"=>Se(0)<= '1';
WHEN OTHERS =>Se(0) <= '0';
end CASE;
CASE CD is
WHEN "00"=>Se(1)<= '1';
WHEN "01"=>Se(1)<= '1';
WHEN "11"=>Se(1)<= '1';
WHEN OTHERS =>Se(1) <= '0';
end CASE;
CASE Se is
WHEN "01"=>S<= E;
WHEN "11"=>S<= NOT E;
WHEN OTHERS =>S <= '0';
end CASE;
end PROCESS;
end Behavioral;
4) Donner le code VHDL qui décrit le fonctionnement du circuit ci-dessus en utilisant
une description Structurelle.

5)
 Code globale :
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_1164.ALL;
entity Testt is
Port ( E0 : in STD_LOGIC;
E1 : in STD_LOGIC;
E2 : in STD_LOGIC;
E3 : in STD_LOGIC;
SEL : in STD_LOGIC_VECTOR(1 downto 0);
S : out STD_LOGIC);
end Testt;
architecture Behavioral of Testt is
signal S1 : STD_LOGIC;
signal S2 : STD_LOGIC;
signal D : STD_LOGIC_VECTOR(1 downto 0):=S1&S2;
component AND_4 IS
PORT( A : in STD_LOGIC;
B : in STD_LOGIC;
C : in STD_LOGIC;
D : in STD_LOGIC;
SEL2 : in STD_LOGIC_VECTOR(1 downto 0);
Q : out STD_LOGIC );
END COMPONENT;
begin
MUX1 : AND_4 PORT MAP ( '1' , '0' , '0' , '1' , SEL , S1 );
MUX2 : AND_4 PORT MAP ( '1' , '1' , '0' , '1' , SEL , S2 );
MUX3 : AND_4 PORT MAP ( '0' , E1 , '0' , NOT(E3) , D , S );
end Behavioral;

Définition de component :
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity AND_4 is
 Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
C : in STD_LOGIC;
D : in STD_LOGIC;
SEL2 : in STD_LOGIC_VECTOR (1 downto 0);
Q : out STD_LOGIC);
end AND_4;
architecture Behavioral of AND_4 is
BEGIN
PROCESS(SEL2)
begin
CASE SEL2 IS
WHEN "00" => Q<= A ;
WHEN "01" => Q<= B ;
WHEN "10" => Q<= C ;
WHEN "11" => Q<= D ;
WHEN OTHERS => Q<= '0';
END CASE ;
END PROCESS ;
end Behavioral;

Exercice 2 :
3) Proposer un code VHDL décrivant ce comparateur.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity test is
Port ( A : in STD_LOGIC_VECTOR (1 downto 0);
B : in STD_LOGIC_VECTOR (1 downto 0);
Eg : out STD_LOGIC;
Dif : out STD_LOGIC;
Sup : out STD_LOGIC;
 Inf : out STD_LOGIC);
end test;
architecture Behavioral of test is
BEGIN
process(A , B)
begin
if (A<B) then Inf <= '1';
Sup <= '0';
Eg <= '0';
Dif <= '1';
elsif(A>B) then Inf <= '0';
Sup <= '1';
Eg <= '0';
Dif <= '1';
elsif (A /= B)then INF <= '0';
Sup <= '0';
Eg <= '0';
Dif <= '1';
else Inf <= '0';
Sup <= '0';
Eg <= '1';
Dif <= '0';
end if;
end process;
end Behavioral;

Exercice 3 :
4)Donner un Code VHDL décrivant le circuit ci-dessus en utilisant une description
Comportementale

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity cccc is
Port (
E : in STD_LOGIC_VECTOR (3 downto 0);
 S : OUT STD_LOGIC_VECTOR (6 downto 0);
AN : OUT STD_LOGIC_VECTOR (7 downto 0) );
end cccc;
architecture Behavioral of cccc is
BEGIN
AN <= "11111110" ;
PROCESS(E)
begin
case E is
when "0000" => S <= NOT"1111110" ;
when "0001" => S <= NOT"0110000" ;
when "0010" => S <= NOT"1101101" ;
when "0011" => S <= NOT"1111001" ;
when "0100" => S <= NOT"0110011" ;
when "0101" => S <= NOT"1011011" ;
when "0110" => S <= NOT"1011111" ;
when "0111" => S <= NOT"1110000" ;
when "1000" => S <= NOT"1111111" ;
when "1001" => S <= NOT"1111011" ;
WHEN OTHERS => S <= NOT"0000000" ;
END CASE ;
end PROCESS ;
end Behavioral;

Exercice 4 :
1)Donner une description VHDL (comportementale) du circuit ci-dessus.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity test is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
SEL : in STD_LOGIC;
S : out STD_LOGIC);
end test;
architecture Behavioral of test is
signal S1 : STD_LOGIC;
signal S2 : STD_LOGIC;
BEGIN
S1 <= '0' WHEN A=B ELSE '1' ;
S2 <= '1' WHEN A='1' AND B='1' ELSE '0' ;
PROCESS(SEL)
begin
CASE SEL IS
WHEN '0' => S<= S1 ;
WHEN '1' => S<= S2 ;
WHEN OTHERS => S<= '0' ;
END CASE;
END PROCESS;
end Behavioral;

2) Donner une description VHDL (structurelle) du circuit ci-dessus en développant

cinq fichiers (.VHDL).

Code global
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity TEST is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
SEL : in STD_LOGIC;
S : out STD_LOGIC;
S1 : inout STD_LOGIC;
S2 : inout STD_LOGIC);
end TEST;
architecture Behavioral of TEST is
component XOR_2
PORT (
E1 : in STD_LOGIC;
E2 : in STD_LOGIC;
O : out STD_LOGIC );
 END component ;
component AND_2
PORT (
E1 : in STD_LOGIC;
E2 : in STD_LOGIC;
O : out STD_LOGIC );
END component ;
component MUX_2
PORT (
E1 : in STD_LOGIC;
E2 : in STD_LOGIC;
SELE: in STD_LOGIC;
O : out STD_LOGIC );
END component ;
begin
X : XOR_2 PORT MAP (A , B , S1 );
Y : AND_2 PORT MAP (A , B , S2 );
Z : MUX_2 PORT MAP (S1 , S2 , SEL , S);
Code définition de component Z :
end Behavioral;
library IEEE;

use IEEE.STD_LOGIC_1164.ALL;
Code definition de component X : Code définition de component Y :
entity MUX_2 is
library IEEE; library IEEE;
Port ( e1, e2, sele : in STD_LOGIC;
use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_1164.ALL;
o : out STD_LOGIC);
entity XOR_2 is entity AND_2 is
end MUX_2;
Port ( e1 : in STD_LOGIC; Port ( e1 : in STD_LOGIC;
architecture Behavioral of MUX_2 is
e2 : in STD_LOGIC; e2 : in STD_LOGIC;
begin
O : out STD_LOGIC); O : out STD_LOGIC);
process(sele)
end XOR_2; end AND_2;
begin
architecture Behavioral of XOR_2 is architecture Behavioral of AND_2 is
case sele is
begin begin
when '0' => O <= e1 ;
O <='0' WHEN e1=e2 ELSE '1' ; O <='1' WHEN e1= '1' AND e2= '1' ELSE '0' ;
when '1' => O <= e2 ;
end Behavioral; end Behavioral;
WHEN OTHERS => O <= '0' ;

END CASE;

END PROCESS;

end Behavioral;
 Exercice 5:
5)Ecrivez la description, en VHDL, correspondante en utilisant l'instruction conditionnelle «
if ».
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity test is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
SUP : out STD_LOGIC;
INF : out STD_LOGIC;
EGAL : out STD_LOGIC);
end test;
architecture Behavioral of test is
BEGIN
PROCESS(A,B)
begin
IF (A>B) THEN SUP<='1';
INF<='0';
EGAL<='0';
ELSIF (A<B) THEN SUP<='0';
INF<='1';
EGAL<='0';
ELSE SUP<='0';
INF<='0';
EGAL<='1';
END IF;
END PROCESS;
end Behavioral;

Exercice 7:
Cahier de charge 3:

Code global:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity ADD_4BITS is
Port ( A : in STD_LOGIC_VECTOR (3 downto 0);
B : in STD_LOGIC_VECTOR (3 downto 0);
S : out STD_LOGIC_VECTOR (3 downto 0);
RE : in STD_LOGIC;
RS : out STD_LOGIC);
end ADD_4BITS ;

architecture Behavioral of ADD_4BITS is

signal X0 , X1 , X2 :STD_LOGIC;
component ADD_2
port(
A,B,RE0 :in std_logic;
S,RS0 : out std_logic
);
end component;
begin
U1: ADD_2 PORT map(A(0),B(0),RE,S(0),X0);
U2: ADD_2 PORT map(A(1),B(1),X0,S(1),X1);
U3: ADD_2 PORT map(A(2),B(2),X1,S(2),X2);
U4: ADD_2 PORT map(A(3),B(3),X2,S(3),RS);
end Behavioral;
Déffinition de component:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity ADD_2 is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
RE0 : in STD_LOGIC;
S : out STD_LOGIC;
RS0 : out STD_LOGIC);
end ADD_2;
architecture Behavioral of ADD_2 is
begin
S <= A XOR B XOR RE0 ;
RS0 <= ( A AND B ) OR ( RE0 AND ( A XOR B ) );
end Behavioral;