Lecture14 - Envelope Tracking
Lecture14 - Envelope Tracking
Lecture14 - Envelope Tracking
Doherty Amplifier
Outphasing (LINC or Chireix) Amplifier
Envelope Tracking Amplifier
Envelope Elimination & Restoration Amplifier
Strategies for Reduction of DC Power For
Low output Power Operation
Iout
Iout
Vout Vout
V1 V2 V3
Vary bias current according to
Instantaneous power Vary bias current and voltage according to
“Dynamic biasing” Instantaneous power
“Envelope tracking and EER”
Iout
Vout
Envelope Tracking (ET) Technique
Voltage
Envelope Envelope
Detector Amplifier
0
Time
RF RF RF
Signal Amplifier Signal Out
In
Efficiency
For ET system
Efficiency
Pout (dBm)
Notation change:
here Vo=Vdd
Class B Amplifier Efficiency
Notation change:
here Vo=Vdd
Also,
In ET, try to keep Pout within 1-2 dB overdrive PA
of Poutmax (65-80%) all the time somewhat
Envelope & Power Supply Benefit of ET Architecture (2)
Voltage (normalized)
Constant Supply Voltage Envelope Tracking
Red: overvoltage
DYNAMICALLY VARYING
DRAIN VOLTAGE
Voltage
AMPLITUDE signal DC SUPPLY
0 VDD
AMPLIFIER
DRAIN Time
VOLTAGE
RF POWER Output
0
TRANSISTOR signal
saturated at
all times
Envelope and Phase Signals in EER
• EER separates the CDMA signal into two new signals
(Signal Decomposition):
Contains AM of
0
WCDMA signal CDMA signal
ET EER
DYNAMICALLY VARYING
DRAIN VOLTAGE
DC Drain voltage
Voltage
tracks AMPLITUDE signal DC SUPPLY
Supply envelope of
RF signal
0 VDD
Envelope Envelope AMPLIFIER
Detector Amplifier DRAIN Time
VOLTAGE
RF RF RF RF POWER Output
Signal Amplifier Signal 0 TRANSISTOR signal
In Out
saturated
at all
times
Comparison of EER and ET
60
Output PWR
efficiency
50
ET
Output Power (W), Efficiency (%)
40
Operating
Range EER
30
Operating
Point
20
Traditional PA
Operating 10
Range
0
0 0.5 1 1.5 2 2.5 3 3.5
Input power (W)
EER / ET Comparison
Potentially highest efficiency
Requires very accurate dynamic supply
EER Input drive power is greater
Leakage of input signal to output is a problem for low
output drive
Phase signal has very broad bandwidth
Time alignment of phase, envelope very critical
Magnitude (dB)
30
20
10
0
-10
-20
-30
-40
-50
-60
-20 -15 -10 -5 0 5 10 15 20
Frequency offset (MHz)
RF input envelope
Classical EER
RF input envelope is
optimized to achieve
trajectory with highest
efficiency and
linearity
Signal envelope
Burden of achieving accurate output
envelope is placed jointly on RF stage and on
dynamic power supply
EER / ET Advantages
•High efficiency
•Excellent thermal management for transistor
•Broad tunable bandwidth
EER / ET Challenges
•Vdd amplifier must be low cost, high efficiency, broad
bandwidth, high voltage
•RF stage must operate well over wide Vdd range
•Gain of RF stage tends to be lower (device in
compression to get high efficiency)
PA Efficiency Can Be Very High With ET
ET PA with Dual Switcher / HVHBT PA
Efficiency
Probability
PDF
WCDMA
6.6 dB PAPR
Pout=67W
Record
coupler
RF RF PA
signal
Vi Vo
Experimental Envelope Tracking Amplifier
Complex system including
RF stage, analog/digital dynamic power
supply, digital predistortion, up and down-
converters
DC
Drain Modulator
Predistortion
ET/EER and
DC/DC
Envelope
DAC
DSP
I
RF
Q Upcon
WCDMA Output
DAC PA
Drivers Final stage High Power
Downcon
RF Stage
ADC
F= 2.1 GHz
Constraint on Overall Efficiency
Both RF PA and dynamic power supply must be optimized
Composite Efficiency =
Vh Vbat time
Isw
-Vd
time
Vind time
Vbat-Vout
Idiode
time
-Vd-Vout
time
Efficiency can be high (85-95%)
Losses due to I2R & CV2 fsw (best to operate at low fsw)
Envelope Tracking on Different Time Scales
No tracking
Useful for power
Vdd(t) Fast tracking
variations on
power control
Signal time scale
(critical for
time handset power
amplifiers)
No tracking
time
Frequency Response Considerations
Cumulative
distribution
Frequency (MHz)
Signal BW=4MHz
Video amplifier
Dc-dc converter
Current Source
Voltage Source Low BW
High BW Eff > 90%
Eff = 50% VDC
VDC
Current
Envelope Sense g
Signal
s d
Switcher
Linear
Stage
Stage
Architecture Envelope
Signal
Current
Sense
s
g
Switcher
Linear
Stage
Stage
M5
Switching
Anti-shoot L
Through &
Gate
Stage
Drivers c
M6
Linear Stage
M3 M2
Rsen
Env_in
id
Sense & Control
OTA
ia OP AMP
M4 M1
R1 R2 To PA
Vout
2V/div
Overall
efficiency
reaches 50% !!
CSICS 2012
ET PA with Dual Switcher / HVHBT PA
Before DPD
Efficiency After DPD
After
Memory
Mitigation*
Probability