Ultra-Low Power Fast Multi-Channel 10-Bit ADC ASIC For Readout of Particle Physics Detectors
Ultra-Low Power Fast Multi-Channel 10-Bit ADC ASIC For Readout of Particle Physics Detectors
Ultra-Low Power Fast Multi-Channel 10-Bit ADC ASIC For Readout of Particle Physics Detectors
fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TNS.2016.2602391, IEEE
Transactions on Nuclear Science
1
Abstract—The design and measurement results of an ultra- – International Linear Collider or CLIC – Compact LInear
low power multi-channel fast 10-bit Analog-to-Digital Converter Collider), replacing the previously developed digitizer in older
(ADC) ASIC, developed for readout systems in future particle technology [3]. However, the architecture and parameters of
physics experiments, are discussed. An 8-channel prototype with
a PLL-based data serialization and a fast data transmission was the ASIC do not limit its application to this detector. In fact,
designed and fabricated in a 130 nm CMOS process. The ADC the ADC may be used in any readout ASIC requiring similar
converts analog data with sampling rates from about 10 kS/s resolution and sampling rate. For the LumiCal an important
to 40 MS/s, with power consumption proportional to sampling requirement is to have an ASIC operating in wide, power-
rate. The resulting Figure of Merit (FOM), for sampling rates 5– scalable sampling range. In the ILC detector implementation
40 MS/s, is 35–42 fJ/conv.-step, per ADC channel. Similar power
contribution is spent for fast data serialization and the largest a sampling rate of about 3 MS/s would be needed [4]. On
contribution goes to data transmission. A wide spectrum of static the other hand, for the beam-test runs, where the ILC-like
and dynamic measurements confirm very good performance trigger is usually not available, a much higher 20–25 MS/s
of this multi-channel ADC with ENOB∼9.2 bits, an excellent rate is favorable, which allows to sample the shape of the
channel uniformity, and negligible crosstalk. The ADC works front-end pulse and then to perform its deconvolution [2].
asynchronously and so it is not limited to systems with uniform
time sampling. The ADC is designed using dynamic circuitry Increasing the ADC sampling rate even further to 40 MS/s
which eliminates static power consumption (except leakage), as a one could extend its applicability to various Large Hadron
consequence it is ready for applications requiring power cycling. Collider (LHC) detector readout systems. In summary, the
ADC covering the sampling rate from single MS/s to 40 MS/s
Index Terms—Multi-channel ADC; SAR ADC; Ultra-low can be of interest for various newly developed readout systems.
power; Serialization; PLL. For the linear collider applications an important additional
requirement is to reduce as much as possible power dissipation
between beam trains, applying so called power cycling. Based
I. I NTRODUCTION
on the above considerations the main goal of this work was
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Vcm
GND
Vref Control signals
Bootstrapped Dynamic
switches comparator
32C 2C C 8C 2C 16C
Vin+ Asynchronous,
2C 10-bit
Split 6b/3b DAC dynamic
Vin 2C output
SAR logic
32C 2C C 8C 2C 16C
Sampling Vref
GND
clock Vcm
of channels should match the sensor segmentation, which rates 0.01–40 MS/s, and in the range 10–30 MS/s it achieves
for the LumiCal, containing 64 sensor pads in a sector, will the Effective Number of Bits (ENOB) 9.2–9.35 and the Figure
most probably be 64. In this design no special attention was of Merit (FOM) 34–37 fJ/conv.-step.
given to radiation hardness aspects, although the 130 nm
CMOS process should allow significant radiation immunity. B. Serializer
The detailed radiation hardness studies will be done in the To serialize the data from continuously running multi-
future. channel ADC, a multiple of the sampling clock is needed. In
commercial multi-channel ADCs a dedicated PLL is usually
used for this purpose. In the developed ASIC the PLL was
A. 10-bit ADC Channel Core
implemented but the serializer can be also configured to work
The ADCs performing successive approximations are in different ways.
among the most popular due to their simplicity and a very 1) Serializer Architecture: The output data from multi-
small number of mostly digital components. During last channel ADC can be serialized and sent out in different ways,
decade the improvements in Successive Approximation Reg- according to the selected serializer mode.
ister (SAR) ADC architecture have brought a continuous • Single channel mode – in this mode a 10-bit data of the
increase of their speed (presently beyond 300 MS/s for a selected channel is sent to ten parallel SLVS transmitters
10-bit ADC [5]) and a huge drop in dissipated power. As with the sampling clock frequency and so the readout and
discussed before, the latter is of crucial importance for future sampling frequency are the same.
high density detector readout systems, and for this reason the • Parallel mode without PLL – in this mode the 10-bit data
SAR architecture has been chosen in this work. of each channel is serialized and sent into a single SLVS
The design and measurement results of the SAR ADC core transmitter with an external readout clock 10-times faster
used in this work have been already presented in detail and than the ADC sampling clock. The ADC sampling clock
published [6]. Here we summarize only the main features. is obtained by division of the external readout clock.
The architecture of the implemented 10-bit ADC core is • Parallel mode with PLL – in this mode the 10-bit data
shown in Fig. 1. The ADC comprises an input sampling of each channel is serialized and sent into a single SLVS
circuitry, a Digital to Analogue Converter (DAC), a compara- transmitter with an internal readout clock 10-times faster
tor, and a SAR control logic. A fully differential solution is than the ADC sampling clock. The readout clock is
used to improve the immunity to digital cross-talk and other generated by an internal PLL which multiplies by ten
disturbances. A capacitive DAC eliminates the static power the ADC sampling clock.
and achieves the lowest power consumption. For the same • Serial mode without PLL – in this mode the 10-bit data
reason all transistor-based circuitry is dynamic. In result the from eight channels is serialized and sent into a single
ADC does not consume any power (except leakage) when SLVS transmitter with the external readout clock 80-
not converting and its power dissipation is proportional to times faster than the ADC sampling clock. The ADC
the sampling frequency. An asynchronous control logic is sampling clock is obtained by division of the external
implemented to eliminate the clock tree and to increase the readout clock.
conversion speed. The asynchronous operation together with • Serial mode with PLL – in this mode the 10-bit data from
the dynamic implementation enscan notures the power cycling. eight channels is serialized and sent into a single SLVS
To optimize the ADC speed a variable internal delay during transmitter with the internal readout clock 80-times faster
each bit processing was implemented. It can be set through than the ADC sampling clock. The ADC sampling clock
internal registers. is obtained dividing by ten the external clock, while the
The ADC core occupies a 950 µm x 146 µm area. It was readout clock is generated by the internal PLL which
verified [6] that the ADC core works properly for sampling multiplies the external clock by eight.
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of the ADC data sent from the chip. Since the implemented PFD D
CP LPF
synchronous data transmission works up to about 400 MHz
the ADC operation in serial modes is limited to sampling AFMS VO
...
...
os
and eight SLVS data transmitters, an additional start f rame os
sel
M1 M2 selB M11 vn
Vbias1 SLVSref
SLVS transmitter is used, which is needed to mark the begin- M12
ning of the 10-bit ADC sample.
M9
2) PLL: The PLL used for serialization of the multi- vn
MD
channel ADC data was designed as a general purpose ultra-low VSS
power (< 1mW at 1 GHz) circuit, which can operate in a very
wide MHz–GHz frequency range. Figure 3 shows the block Fig. 4. Schematic diagram of SLVS transmitter.
diagram of the developed PLL. It consists of a Phase and
Frequency Detector (PFD), a Charge Pump (CP) with a Low M11, M12 were added to the original scheme to allow very
Pass Filter (LPF), a single-ended Voltage-Controlled Oscillator low (≤ 400 mV) common-mode voltage. Since the transmitter
(VCO), a clock divider, and an Automatic Frequency Mode is the most power-consuming block and 10 SLVS transmitters
Setting (AFMS) block. It can operate with different division are needed to transmit 8-channel data output, the SLVS power
factors but for the multi-channel ADC only divisions by consumption may be varied by changing its bias current. In
8 (serial mode) and 10 (parallel mode) are used. For data addition the common-mode voltage is controlled by an external
serialization the readout frequency range 10–400 MHz is used reference voltage SLV Sref .
in this work. The PLL operation was positively verified before For the SLVS receiver, a self-biasing amplifier configuration
its implementation in the multi-channel ADC ASIC. The proposed in [10] was implemented, as shown in Fig. 5. In
design and measurements of the prototype PLL are discussed default operating conditions the simulated power consumption
in detail in [7]. of the transmitter and receiver is about 2.1 mW and 0.6 mW
3) Testability: To verify the serializer itself and the digital respectively. Simulations showed that for standard 100 Ω
transmission a known pattern can be sent to the serializer input termination and small capacitive load (∼2pF), the transmitter-
instead of ADC data. Two types of 10 bit-wide pattern are receiver chain can work up to about 2 GHz.
generated by a dedicated binary or pseudo-random internal
counters. The pseudo-random counters are linear feedback D. ASIC Integration, Floorplan and Layout
shift registers (LFSR) avoiding a forbidden state [8]. To avoid The layout of the prototype ASIC is optimized for multi-
generation of the same data in each channel, each binary channel architecture and consequently the vertical size of
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PLL because of full overlapping) were measured for the same signal
sent to all ADC inputs. The gains and offsets calculated for
each channel of prototype ASIC are presented in histograms
SAR ADC shown in Fig. 7. The gain and offset spreads were estimated
Serializer
8 channels
& slow to be about 0.2% and 1.5 LSB respectively, confirming very
control good uniformity of ADC channels.
2) INL & DNL Measurements: The ADC static perfor-
mance is quantified with the integral (INL) and differential
(DNL) nonlinearity measurements. Both parameters are ob-
tained with the histogramming method [11]. An example of
typical INL, DNL distributions is shown in Fig. 8.
Fig. 6. Layout of prototype ASIC. The maximum values of INL and DNL parameters in
function of sampling frequency are presented in Fig. 9.
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entries
3 3
2 2 1 LSB. The worst values appear only for few codes, when most
1 1 significant bits are changed (typical for SAR architecture). A
0 0
typical INL/DNL behavior can be better described by Root
433.75 434.25 434.75 435.25 435.75 506 508 510 512 514 516
Mean Square (RMS) value. The DN LRM S is about 0.25 LSB,
gain (LSB/V) offset (LSB)
while the IN LRM S is about 0.32 LSB.. The measured INL
Fig. 7. Histograms of gain and offset calculated from transfer curves (8 ADC in the sampling frequency range up to 35 MHz stays always
channels). between -1–1 LSB. At 40 MHz sampling the linearity starts
to deteriorate and the worst INL, DNL values exceed the -1–
1 1 LSB range. In fact, few missing codes per channel appear
0.5
often at 40 MHz sampling frequency for the codes close to
INL (LSB)
0.5
0
C. Dynamic Measurements
-0.5
-1 For the evaluation of dynamic circuit performance, Fast
0 128 256 384 512 640 768 896 1k
Code (LSB)
Fourier Transform (FFT) spectra were calculated from the
measurements done with a near full-scale sine input sig-
Fig. 8. Example of INL and DNL measured at 25 MHz sampling frequency nal [11]. The standard ADC metrics i.e. the Signal to Non Har-
for channel 3 and calculated using the histogramming method. monic Ratio (SNHR), the Total Harmonic Distortion (THD)
ratio, the Spurious Free Dynamic Range (SFDR) and the
ch0 ch2 ch4 ch6
ch1 ch3 ch5 ch7 Signal to Noise and Distortion Ratio (SINAD), were calculated
from the FFT spectrum. From these metrics the ENOB was
1.5
obtained. Since the measurements at high input signal fre-
1 quencies require significantly more effort (additional filtering),
systematic measurements for all ADC channels were done at
0.5 one fifth of Nyquist frequency, which is close to the mid-
INL (LSB)
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13 80.0 number of supply lines is limited. For this reason the ADC
resolution was studied (for exemplary ADC channel) for
12 74.0 different power supply configurations. The ENOB and SINAD
results versus sampling frequency are shown in Fig. 13. The
11 68.0
ENOB
(dB)
SINAD(ENOB) SNHR
THD SFDR
9.4 58.35
10 62.0
9.2 57.14
9 55.9
9 55.94
SINAD (dB)
Separated
ENOB
8.8 ADC_ana+ADC_dig 54.74
8 49.9 ADC_ana+ADC_dig+ADC_Vref
0 5 10 15 20 25 30 35 40 ADC_all+SER
Sampling frequency (MHz) 8.6 53.53
8.4 52.33
Fig. 10. ADC dynamic performance of channel 6 as a function of sampling
frequency obtained with input signal frequency 1/10th of sampling frequency. 8.2 51.12
8 49.92
0 5 10 15 20 25 30 35 40
9.4 58.35 Sampling frequency (MHz)
9.2 57.14 Fig. 13. ENOB and SINAD for channel 3 measured for different configura-
tions of supply and reference voltage.
9 55.94
SINAD (dB)
ENOB
8.8 ch0 ch2 ch4 ch6 54.74 curve Separated is the reference corresponding to the already
ch1 ch3 ch5 ch7
8.6 53.53 presented measurements. The ADC ana + ADC dig curve
was obtained merging the analog and digital supply lines of the
8.4 52.33
ADC. For curve ADC ana + ADC dig + ADC V ref also
8.2 51.12 the reference voltage was connected together with analog and
8 49.92
digital power supply lines. To obtain the last ADC all+SER
0 5 10 15 20 25 30 35 40
curve not only the ADC power supply lines but also the digital
Sampling frequency (MHz)
ASIC supply (serializer and slow control) line was merged.
Fig. 11. ADC dynamic performance: ENOB and SINAD as a function It is seen that the configuration of power supply lines has
of sampling rate obtained with input signal frequency 1/10th of sampling almost no effect on the ENOB. Only when all supply lines
frequency.
are connected together the effect of the order of 0.05 LSB is
seen.
Figure 12 presents the ENOB and SINAD behavior as a To verify the robustness of the design and to check the
function of input frequency, measured for two channels at possibility of further power saving the sensitivity of ADC
25 MHz sampling frequency. The ENOB is above 9.2 bits and resolution to absolute power supply value was studied. In
Fig. 14 the ENOB and SINAD are presented versus supply
voltage for two exemplary channels at 10 MHz and 25 MHz
9.4 58.35 sampling frequency. Increasing the power supply from nom-
inal 1.2 V to 1.5 V practically does not change the ADC
9.2 57.14
9 55.94
SINAD (dB)
ENOB
Fig. 12. ENOB and SINAD in function of input sine frequency at 25MHz 8.2 51.12
sampling frequency.
8 49.92
0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5
it is rather flat in the whole range. At Nyquist input frequency Supply (V)
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Power (mW)
ADC_dig
power supply. In principle, lower power supply may be used 4 0.5
to minimize the power consumption, but this possibility is not 3 0.375
exploited in this work.
2 0.25
ADC_ana
1 0.125
D. Crosstalk Measurements ADC_Vcm
ADC_Vref
0 0
To study the crosstalk effect a sine signal was sent to 0 5 10 15 20 25 30 35 40
Sampling frequency (MHz)
one ADC channel and all channels outputs were measured.
Example results of such measurement are shown in Fig. 15 for Fig. 16. Power consumption of multi-channel ADC.
the cases with and without the signal on channel 2. It is seen
that for nearest neighbors the crosstalk signal is attenuated
more than by 70 dB and its effect is smaller than the noise one can place both the analog front-end and the ADC in each
seen in some other channels. Practically the crosstalk effect channel of readout ASIC, without affecting dramatically the
may be neglected. overall power consumption. Such solution will greatly simplify
further digital processing of experimental data.
60 2) Multi-Channel ADC with Serialization and Data Trans-
50 mission: The power contribution of main blocks of the ASIC
40 performing ADC conversion, serialization, and data transmis-
30 with sine sion, has also been verified. It was not the main objective
20
of this work but it was done to observe general trends and
RMS (dB)
10
draw basic conclusions on various contributions to the total
0
power consumption. In the case when DSP is applied directly
-10
-20
to the ADC data these considerations are less important. But
without sine
-30
even in such case, when the number of channels in readout
-40 ASIC will increase from 8 to 64 or more, the discussion about
-50 serialization scheme and data transmission will again become
0 1 2 3 4 5 6 7
channel
relevant.
Fig. 15. Measurement of crosstalk between ADC channels (sine on channel 2) 100 12.5
and ”raw” noise (all other channels on Vcm ) at 25 MHz sampling frequency.
SLVS at 150uA
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FOM (fJ/conv)
low frequencies is less relevant because it is due to leakage ADC+SER+SLVS(50uA)
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TABLE I
C OMPARISON WITH OTHER MULTI - CHANNEL ADC S
comparing the F OMADC from [3] to the presented design, • small 146 µm pitch of ADC core which simplifies the
a huge factor of about 25 is seen. This huge power saving is integration in a dense multi-channel readout system.
the main motivation for using modern SAR architectures for
conversion in high density multi-channel readouts of particle IV. C ONCLUSION
detectors. For applications with higher bandwidth of input The design and measurements of a fast ultra-low power
signal the obtained in this work F OMADC (measured at 10-bit multi-channel ADC, for applications in the readout of
0.2 Nyquist) may be underestimated. To estimate this effect particle physics detectors, are presented. The developed pro-
one can calculate F OMADC for 0.2, 0.5, and 1.0 Nyquist totype of 8-channel SAR ADC is fully functional and works
input at 25 MHz sampling frequency from Fig. 12, getting over a wide sampling frequency range 0.01–40 MHz. Its ultra-
respectively 36, 38, and 41 fJ/conv.-step. Since in the presented low power consumption is reflected by an excellent FOM of
design the internal reference is not included, some additional 35–42 fJ/conv.-step/channel in the sampling frequency range
power would need to be added for fair comparison with the 5–40 MHz. The performed measurements confirm good static
commercial designs. Nevertheless, it was shown, that using (INL<1 LSB, DNL∼1 LSB) and dynamic (SINAD ∼57.5 dB)
stable external power supply the additional reference is not performance, which is reflected in a good ENOB of 9.2 bits. In
necessary. addition the developed ADC uses asynchronous logic and fully
In addition to power efficiency, the presented multi-channel dynamic circuitry what allows for direct application of power
ADC ASIC comprises important features which are not or only cycling and asynchronous sampling, if needed. All mentioned
partially implemented in other designs: features make the ADC very flexible, allowing its use also as
• scalability of power with sampling rate over 3 orders a general purpose multi-channel ADC.
of magnitude (with PLL-based serializer the frequency The developed multi-channel ADC is a key block of a
range is smaller 1–40 MHz); prototype ASIC comprising also a PLL-based serialization and
• possibility of asynchronous operation which comes from a fast SLVS I/O interface for data transmission. All presented
asynchronous SAR ADC architecture (when using the measurement results were obtained using the data serialized
PLL-based serializer this feature cannot be used); per channel (at tenfold sampling frequency) and transmitted
• various serialization modes; by SLVS drivers to the FPGA-based acquisition system. It has
• very short Tpower on which is practically zero for the been shown that in such multi-channel ADC ASIC, comprising
ADC, since it uses fully dynamic circuitry, and 5–25µs the serialization and fast data transmission, the dominant
when the PLL-based serializer is used and the PLL is power contribution comes from the power hungry transmitters.
switched off; Nevertheless, the developed prototype dissipates per channel
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