Adi PHD 08
Adi PHD 08
Adi PHD 08
ANALOG-TO-DIGITAL CONVERTERS
By
Alma Delić-Ibukić
B.S. University of Maine, 2002
M.S. University of Maine, 2004
A THESIS
Submitted in Partial Fulfillment of the
Requirements for the Degree of
Doctor of Philosophy
(in Electrical Engineering)
Advisory Committee:
Signature:
Date:
DIGITAL BACKGROUND CALIBRATION TECHNIQUES FOR
ANALOG-TO-DIGITAL CONVERTERS
By Alma Delić-Ibukić
Due to consumer demand for wireless devices that support multimedia services rang-
ing from voice and data transfer to video on demand, there is a need for flexible and
adaptable base stations. These systems are typically implemented using a wide-band re-
ceiver that captures and digitizes the entire cellular band which contains multiple wire-
less standards. In order to digitize the entire cellular band, there is a requirement for
wide bandwidth, high-resolution analog-to-digital converters (ADCs). In general, these
ADCs are hard to realize and require some form of calibration to meet the requirements.
In this thesis, two novel digital background calibration techniques targeted for pipeline
and Π∆Σ architecture ADCs are reported. The two calibration schemes are realized
by introducing a redundancy in the system. For the pipeline architecture converters,
two extra stages located at the end of the pipeline are implemented and are active only
during calibration process. This calibration is suitable for implementation in a fully
monolithic pipeline ADCs. For the Π∆Σ architecture converters, an extra channel that
is linearly dependent on the Π∆Σ channels is implemented to correct for channel gain
mismatches. All channels are calibrated simultaneously, and calibration of the overall
system depends on the convergence rate of a recursive-least-squares algorithm.
ACKNOWLEDGMENTS
I would first like to thank my advisor Professor Donald M. Hummels for being a
great mentor and for introducing me to data converters. His support and technical guid-
ance throughout this project have been invaluable. He always managed to find some-
thing positive in every situation. His trust in me helped me move forward in my research
and most importantly helped me build confidence. It has been a privilege working with
him.
I would also like to thank Professor David E. Kotecki for patiently answering all
my Cadence questions and any other questions I always seemed to have. Your guidance
and advice have been greatly appreciated.
Thank you, Professor Ali Abedi for serving on my committee and especially for
making the resources of your lab available for the successful completion of my research.
Thank you, Professor Duane Hanselman and Professor Ali Ozluk for serving on
my committee and for sharing with me your knowledge of engineering and mathematics
throughout my education at the University of Maine.
I would like to thank Steven Turner for finding time to review my thesis and
provide valuable feedback. Also, I would like to thank Heidi Purrington for helping out
and doing an excellent job with the layout of an ADC test board.
Also, I would like to express my gratitude to my colleagues and friends, Thomas
Kenny, Thomas Pollard, Homer W. Slade, Bennett Meulendyk and Janice Duy for all
those productive days in Barrows Hall. I will truly miss you.
I would like to thank to my international friends, Metin Cakir, Sonia Aziz, San-
jeev Manandhar, Silvia Cordero-Sancho and Semra Ozdemir for being part of my life,
and sharing with me all my hardships and every one of my accomplishments.
Finally, and most importantly, I would like to express my gratitude to my family,
Nihada and Sead Delić-Ibukić, Judy Cox and my brother Dino for their love, support
ACKNOWLEDGMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ii
LIST OF TABLES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vi
Chapter
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2 Purpose of the Research . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.3 Thesis Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
6 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
6.1 Summary of Accomplishments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
6.2 Recommendations for Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
REFERENCES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
3.1 Sample propagation through the pipeline for the proposed real-
time digital calibration technique. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
A.1 Biasing circuit for OTA, CMFB and gain boosting ampli-
fiers. These will bias the fully differential tranconductance
amplifier and CMFB circuit in Figures 5.8 and 5.10. . . . . . . . . . . . . . . . . . . 170
A.2 1-bit DAC design. Transistors M 1 through M 4 are sized as
45µm/0.6µm. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
B.1 Test board schematics for data capture and FPGA interface
(i.e. Hadamard modulation sequence). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
B.2 Test board schematics for the supply and reference voltages
generation for two chips. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
B.3 Test board schematics for generation of a differential input
signal, clock signal and FPGA clock signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
B.4 Test board schematics for generation of a differential input
signal and clock signal (cont.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
B.5 Top copper layer of a printed circuit test board with silk
screen and top layer interconnects. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Introduction
Due to consumer demand for wireless devices that support multimedia services
ranging from voice and data transfers to video on demand, there is a need for flexible
and adaptable cellular base stations [2]. An initial base station design solution that
supports ever growing consumer demands relied on having multiple receivers, with each
receiver optimized for a given wireless standard. Figure 1.1 shows a traditional base
station receiver architecture [3]. The output of each receiver is sent to an Analog-to-
Digital Converter (ADC) followed by a Digital Signal Processor (DSP). Each channel
is tuned to a frequency band of a particular wireless standard. As the wireless standards
change and/or additional standards become available, this type of architecture requires
the physical layer of the base station to change increasing the cost/complexity of the
analog components [2–4]. Therefore, the above base station design is neither flexible
nor adaptable.
One way to fix the shortcomings of the traditional base station design requires
implementation of a wide-band receiver that captures and digitizes the entire cellular
band. Figure 1.2 shows the receiver architecture that employs this concept [2]. In the
analog domain, the received signal is filtered and converted from radio frequencies (RF)
to intermediate frequencies (IF), where the IF filter is sufficiently wide so the entire
cellular band passes through. This wide-band input signal is sent to a wide-bandwidth
IF sampling ADC. After being digitized, the input signal is processed by the DSP, where
the downconversion, baseband processing and channel recovery are implemented in the
digital domain. This type of receiver architecture for base station systems is known as a
software radio (SWR) or software defined radio (SDR) receiver because changes made
to the base station are carried out by reconfiguring software within the DSP processing
block [2–5].
I
Wide band Digital IF Channel 1
Wide−band Baseband
ADC
RF stage analog IF filter (downconversion and processing
Q
channel selection)
Wide bandwidth,
high−resolution ADC
Analog Domain
I
Digital IF Channel 2
Baseband
(downconversion and processing
channel selection) Q
I
Digital IF Channel n
Baseband
(downconversion and processing
Q
channel selection)
DSP processing
Figure 1.2: Software radio receiver architecture for a base station system using wide-
bandwidth IF sampling ADCs.
1.1 Background
Due to the push toward SWR base stations, there is a need for ADCs that run at
clock frequencies greater than 40 MHz with a resolution greater than 12 bits [2, 3, 6].
High-speed and high-resolution converters are often implemented using Nyquist-rate
converters, namely pipeline multistage ADC architecture converters. One of the rea-
sons is that the overall speed of the pipeline architecture converter is given by the speed
of a single low resolution stage. Also, the hardware complexity of the pipeline con-
verter is proportional to the number of bits resolved. Designs of pipelined architecture
−101 dBm
1.275GHz
870MHz
fo−2.8MHz
fo−1.6MHz
fo−800kHz
fo−600kHz
fo+600kHz
fo+800kHz
fo+1.6MHz
fo+2.8MHz
925MHz
935MHz
fo−3MHz
fo+3MHz
fo
Figure 1.3: Blocking profile for GSM 900 Base Transceiver Stations (BTS) [1].
ADCs have relied on high precision analog components, such as high-gain operational
amplifiers, and excellent capacitor matching to produce moderate resolution converters
(10-12 bits). While the pipeline ADCs built using CMOS process technology can ex-
ceed 100 MHz [7–10], their resolution does not exceed 12 bits. A pipeline architecture
ADC with a 14-bit resolution was reported in [11]. To achieve a 14-bit resolution, Yang
et. al. in [11], used a multi-bit per stage topology with careful design optimization.
However, even with the accomplishment in [11], if a pipeline converter with resolution
greater than 12-bits is needed some form of calibration technique is required.
Alternative converter architectures, such as oversampling delta-sigma (∆Σ) con-
verters, offer resolutions greater than 16-bits [12], require mostly digital circuitry, and
compared to Nyquist-rate converters, don’t rely on high precision analog components
[13]. The need for a high oversampling rate to achieve high linearity, limits the in-
put bandwidth of ∆Σ converters. For example, to achieve 18-bits of resolution, a ∆Σ
ADC described in [12] has an input bandwidth of 24 kHz and it operates at a sampling
rate of 6.1 MHz. Due to the limited bandwidth, ∆Σ ADCs are mostly used in applica-
tions such as digital audio. To keep the high linearity of ∆Σ ADCs and to increase the
Several digital calibration schemes suitable for pipeline and Hadamard modu-
lated parallel ∆Σ converters have been proposed and successfully implemented. Karan-
icolas et al. in [28] implemented a 15-bit digitally self-calibrated ADC. This was a
foreground digital calibration technique derived for a 1-bit per stage pipeline topol-
ogy and targeted toward pipeline ADCs. The calibration was successful in correcting
dominant errors in pipeline ADC architectures (i.e. DAC and interstage gain errors).
Even though it proved to be successful, this calibration technique required the converter
to be off-line during calibration. Digital background calibration techniques were re-
ported in [25, 44, 45, 50]. Calibration techniques in [25, 45] rely on complex digital
post-processing for extraction of calibration parameters and suffer from slow conver-
gence rate. In addition to the required digital post-processing in [44], this calibration
Architectures
00...11
S/H 00...10
00...01
t n 00...00
Analog Input
Sample and hold circuit Quantizer Discrete−time,
discrete−valued (digital) signal
Analog−to−Digital Converter
terms of effective number of bits (ENOB). The ENOB specification takes into account
noise and distortion errors that are present in A/D converters.
Unfortunately, the two distinct operations, i.e. sampling and quantization, that
govern the A/D conversion process work against each other when it comes to improving
converter performance. Figure 2.2 shows the performance of commercially available
ADCs manufactured and reported by Analog Devices Inc. and Texas Instruments Inc..
The data was obtained from the websites of surveyed companies in September 2007
[61,62]. The converter architectures plotted in Figure 2.2 include pipeline, ∆Σ and SAR
converters. The trade-off between resolution, expressed in terms of ENOB, and input
bandwidth FS /2 is evident. The three converter architectures dominate three distinct
regions of the plot. This in turn limits their applications. Ideally, for wide-bandwidth
and high-resolution applications such as software defined radio receivers, a converter
with the resolution of a ∆Σ ADC and the bandwidth of a pipeline ADC is required [2,5].
To increase resolution and bandwidth of pipeline and ∆Σ converters, the con-
verter architectures need to be modified and/or calibration techniques need to be em-
ployed. Figure 2.2 shows ∆Σ and pipeline architecture converters that were ‘optimized’
for bandwidth and resolution, respectively. While calibration techniques will be covered
in the subsequent chapters, the following sections give an overview of SAR, pipeline and
∆Σ converters. These architectures are then embedded in parallel architectures in order
18
16
ENOB (bits)
14
12
10
4
1 2 3 4 5 6 7 8 9 10
10 10 10 10 10 10 10 10 10 10
Sample Rate, FS, (samples/s)
Figure 2.2: Commercially available ADCs from Analog Devices, Inc. and Texas Instru-
ments Incorporated reported in September 2007.
The distinct region of input bandwidth and resolution occupied by SAR convert-
ers in today’s ADC market can be seen in Figure 2.2. Because of their simple architec-
ture, SAR converters are used in applications where resolution ranging from 8-18 bits
and input bandwidths ranging from 10 kHz to 2.5 MHz are required.
A typical SAR converter architecture is presented in Figure 2.3. An analog input
signal x(t) is sampled by a Sample and Hold (S/H) circuit to obtain a fixed voltage X.
This voltage is not allowed to change for the remainder of the conversion process. The
held sample is compared to a coarse analog representation based on the ‘current’ digital
representation. The difference is then routed to an ADC to measure the size of the
error. A SAR converter typically uses a single comparator to implement the ADC and
achieve high resolution. To accomplish this, a successive approximation register holds
the evolving digital representation of the input voltage. As the SAR register content is
refined, a digital-to-analog converter (DAC) is used to convert the current representation
to analog form. Each bit of the SAR register is assigned to a progressively smaller
binary sequence of weights (e.g. 1/4, 1/8, 1/16, ... 1/2n of full scale). In a ‘comparison
cycle’, the DAC output voltage is compared to the held sample value to determine the
appropriate value of the next bit of the digital representation. The first comparison gives
the most significant bit (MSB), and the process repeats until (after n comparison cycles)
the least significant bit (LSB) is determined. Because the overall n-bit resolution is not
obtained until n conversion cycles are passed, SAR converters require an internal clock
rate of nFS (S/H block runs at FS ) to produce a converter with n-bit resolution and FS /2
input bandwidth.
SAR converters are simple to implement, require small die area, and provide res-
olution which depends primarily on the linearity of digital-to-analog (DAC) converter.
DAC
r1 r2
X Stage 1 Stage 2 Stage N
q1 q2 qn
Digital Encoder
Digital Output
flash ADC (sub-ADC). The sub-ADC output qi is an integer value ranging from 0 to
2Bi − 1, where Bi is the number of resolvable bits for the given stage. Once the coarse
digital output is obtained, the value is passed on to the low resolution DAC (sub-DAC) to
form the analog equivalent of the coarse digital input sample. This voltage is subtracted
from the initial input sample giving the quantization error voltage, ei . The resulting
error voltage ei is scaled by the gain factor Gi and passed as a residual ri to the next
stage in the attempt to improve the digital representation of the input. The gain factor is
selected so the error voltage of the first stage doesn’t exceed the acceptable input range
of the next stage. For an ideal sub-ADC and sub-DAC, the gain factor can be selected
to be Gi = 2Bi . Selecting a gain factor as a power of two simplifies the logic of digital
encoder block.
For pipeline architecture converters, hardware complexity is directly propor-
tional to the number of bits resolved. Compared ot high resolution stages, low reso-
lution stages are easier to build and they occupy little real estate on silicon. In theory,
a pipeline converter with N -stages, where each stage contains a B-bit sub-ADC, will
produce a wide-bandwidth ADC with the overall resolution of n = N B bits using
Bi −bit Bi −bit
ADC DAC
qi (Bi −bit)
N (2B − 1) comparators. For example, a 2 bits per stage architecture requires 3 com-
parators per stage and a 4 bits per stage architecture requires 15 comparators per stage.
At the same time, low-resolution stages require more pipeline stages to obtain higher
final ADC resolution and vice versa.
In theory, with a given per stage resolution, one can build a pipeline A/D con-
verter with any resolution by cascading the appropriate number of stages. However, in
practice, monolithic, high-resolution pipeline ADCs are difficult to obtain due to ex-
traordinary component matching requirements. Component matching becomes increas-
ingly difficult as CMOS technologies are scaled to smaller geometries. Error sources
encountered in pipeline architecture converters and ways to cope with them are dis-
cussed in Chapter 3.
One way to improve the resolution of Nyquist rate converters (e.g., pipeline ar-
chitecture ADCs) is by employing oversampling. With oversampling, the analog input
signal is sampled at a sampling rate that is much higher than the Nyquist rate FS . To un-
derstand the benefits of oversampling, requires revisiting the quantization process. The
following sections provide an overview of quantization, oversampled A/D converters,
Vref
Ideal streight line
−Vref
−Vref 2 e
X
Vref Vref
Vref
2
4
−Vref
2 X
−Vref Vref
−Vref
−Vref
4
(a) Transfer characteristics of a uniform 2-bit (b) Quantization error for a 2-bit quantizer.
quantizer.
Figure 2.6: An example of a uniform 2-bit quantizer and quantization error e showing
the deviation of the actual 2-bit quantizer from the straight line (ideal quantizer).
2.4.1 Quantization
Figure 2.7 shows an oversampled A/D converter architecture where the quan-
tizer is modelled as an additive noise source e. The input signal x(t) is sampled at a
rate D times higher than the Nyquist-rate, FS . Once the input signal is quantized the
high-rate digital output is low-pass filtered and decimated to obtain the digital output at
the Nyquist-rate. The factor D is known as the ‘oversampling ratio’ of the converter.
By employing oversampling, the resolution of the converter is increased because the
quantization noise is reduced within the signal band.
The total amount of the quantization noise power σe2 that is added to the sampled
signal is the same regardless of whether or not the input signal is oversampled. As-
suming that the quantization noise e is uniformly distributed over ±QB /2 interval, the
quantization noise power σe2 is given by
Z QB /2
1
σe2 = e2 de = Q2B /12. (2.1)
QB −QB /2
sampler e
x(t) Digital
S/H LPF D output
quantizer
Digital decimation filter
ADC model
Even though σe2 is the same regardless of whether oversampling is used, what differs
is the frequency distribution of the quantization noise power when oversampling is em-
ployed. Because oversampling requires sampling frequencies that are much higher than
Nyquist-rate frequencies, the same amount of quantization noise power is distributed
over a wider frequency range. This reduces the noise power in the frequency band of
interest, which in turn, increases the resolution of the converter. Figure 2.8 illustrates
this fact, where the quantization noise power frequency distribution is shown for an A/D
converter with and without oversampling. The signal band of interest is the region from
−FS /2 to FS /2. For the oversampled converter architectures there is an apparent quanti-
zation noise reduction in the desired region that contributes to the increase in converter’s
resolution.
QB2
12( DFS )
Figure 2.8: Quantization noise power spectral density for A/D converters with and with-
out oversampling employed.
e
x[n] + Digital
LPF D output
−
ADC
Digital decimation filter
DAC
∆Σ modulator
x[n] z −1 y[n]
+ 1−z −1
−
In this equation, ST F (z) = z −1 represents the signal transfer function that delays the
input signal x[n], and N T F (z) = (1 − z −1 ) represents the noise transfer function that
1.8
1.4
1.2
Magnitude 1
STF(z) = z−1
0.8
0.6
0.4
0.2
0
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Normilized frequency
Figure 2.11: Frequency response of N T F (z) and ST F (z) for the first order ∆Σ mod-
F
ulator. The normalized frequency is given by f = DF S
, where FS is the Nyquist-rate
frequency for the first order ∆Σ modulator and D is the oversampling ratio.
only affects the quantization noise e[n]. Figure 2.11 shows the frequency response of
noise transfer function N T F (z) and signal transfer function ST F (z) for a first order
∆Σ modulator. Attenuation of the quantization noise in the signal band of interest by
N T F (z) is evident. The low frequency quantization noise is moved to higher frequen-
cies and outside the band of interest. In general, an Lth order ∆Σ modulator can be
modelled by
where ST F (z) = z −m is a signal transfer function that delays the input signal by m
samples, and N T F (z) = (1 − z −1 )L is a noise transfer function that contributes to
minimization of the quantization noise within the signal band [13].
From Figure 2.9, the lowpass filter that follows the ∆Σ modulator is designed to
2
j2πf 1 sin(Dπf )
G(e )= 2 (2.5)
D sin(πf )
From (2.4) it can be observed that the filter has periodically spaced zeros on the unit cir-
j2πk
cle at z = e D for k = 1, 2, 3, ...D−1. Figure 2.12 shows the frequency response of the
two stage comb filter with D = 20. The lowpass characteristic with periodically spaced
zeros at 1/D and its multiples can be observed. The lowpass filter portion preserves the
desired input signal band and periodically spaced zeros make sure that the out-of-band
quantization noise is attenuated sufficiently so that only a small portion appears back in
the signal band.
∆Σ converter architectures require primarily digital circuitry, and when com-
pared to pipeline converters, they don’t rely on high precision analog components [13,
63]. The drawback of ∆Σ converters is the need for a high oversampling ratio D to
get high linearity for relatively small input bandwidth. To maintain high linearity that
∆Σ converters offer and increase the bandwidth of the converter, ∆Σ modulators can be
placed in parallel [16,64]. Parallel architecture converters are discussed in the following
−10
−20
Magnitude in dB
−30
−40
−50
−60
−70
−80
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Normilized frequency
section.
Parallel converter architectures provide one method for trading circuit complex-
ity for increased resolution or bandwidth. Depending on the way the input signal is ap-
plied to the parallel architecture and ultimately recombined, parallel ∆Σ architectures
can be grouped into three categories: time-interleaved, frequency-band-decomposition,
and Hadamard modulation. The following sections provide an overview of these three
parallel architectures.
Time-interleaving increases the bandwidth of the overall ADC system and can be
employed on both Nyquist-rate and oversampled converter architectures [16,17,65–68].
Figure 2.13 shows an M -channel, time-interleaved ADC architecture. An analog input
signal x(t) is sequentially distributed to M S/H blocks and M ADCs with each operating
n bits
S/H ADC 1
Digital Multiplexer
x(t) n bits n bits
S/H ADC 2
n bits
S/H ADC M
Analog Demultiplexer
at 1/M of the overall system sample rate FS . Each channel operates at a different clock
phase, thereby allowing the final, high sample rate output to be formed by interleaving
the lower sample rate outputs of each channel in proper sequence (i.e. 1, 2, 3, ..., M, 1,
2, ...). This channel recombination occurs in the digital domain.
Besides having performance limitations due to the ADC architecture used, per-
formance of parallel architecture ADC systems is also limited by mismatches among
the channels. In addition to the gain and offset channel mismatch errors, the other com-
mon mismatch error for time-interleaved ADC systems is due to clock skew [69–71].
Clock skew errors cause sample time mismatches across channels [66, 71, 72]. One way
to avoid clock skew error is by implementing a front-end sample and hold (S/H) cir-
cuit [66]. Figure 2.14 shows the modified M -channel time-interleaved ADC system that
utilizes the front-end S/H circuit to minimize the clock skew errors. Here, the analog
input signal x(t) is first sampled at high sample rate and than sequentially distributed to
M ADCs with each operating at 1/M of the overall sample rate FS . This architecture
modification calls for a design of a S/H block that runs at M × FS sample rate.
n bits
ADC 1
FS
Digital Multiplexer
x(t) n bits n bits
S/H ADC 2
n bits
ADC M
Analog Demultiplexer
Figure 2.14: Modified M -channel time-interleaved ADC system that avoids clock skew
errors.
H(f)
H1 H2 H3 HM
F
0 2 FS f=
FS FS FS
M M
Figure 2.16: Frequency response of the bank of M analysis filters with each assigned to
different frequency band.
s1 [n] p1 [n]
∆Σ G(z) D
s2 [n] p2 [n]
∆Σ G(z) D
s3 [n] p3 [n]
∆Σ G(z) D
sM [n] pM [n]
chitecture is insensitive to channel mismatches [20,74]. On the other hand, each channel
of the frequency-band-decomposition architecture is unique, requiring a different filter
and bandpass A/D converter in each channel. This results in a complex design which is
more pronounced at the front end of the architecture where the analog components are
required (i.e. analysis filter bank) [14, 75].
High speed, high resolution, low power ADCs are frequently based on a pipeline
architecture because the overall speed of the pipeline converter is given by the speed of
the single low resolution stage.
Figure 3.1 shows a conventional 1-bit per stage pipeline converter architecture.
Each stage in the pipeline serves two purposes: to provide qi , the coarse resolution dig-
ital representation of the input voltage, and to provide the next stage in the pipeline
with ri , the difference between the input voltage and analog form of qi . This resid-
ual voltage, ri , is passed on to the subsequent stages for quantization in an attempt
to improve the digital representation of the input. All qi ’s are collected in the digital
encoder block where they are combined properly to achieve a higher resolution rep-
resentation of the input voltage X. A pipeline stage consists of a sample and hold
(S/H) block, 1-bit analog-to-digital converter (sub-ADC), 1-bit digital-to-analog con-
verter (sub-DAC), analog subtractor and a gain block. The quantization interval for
a single 1-bit stage is Q = 2VREF /2 or just VREF . The sub-ADC for this particular
r1 r2
X Stage 1 Stage 2 Stage N
q1 q2 qn
Digital Encoder
Digital Output
+ e1
X S/H + G1 r1
−
1
(q )VREF
sub sub 1 2
ADC DAC
q
1
Figure 3.1: Generic Pipeline ADC block diagram showing the details of a pipeline stage.
topology requires one comparator with a zero volt threshold. There are two valid digital
outputs of the sub-ADC block, a 0 or 1. The corresponding sub-DAC outputs for these
two digital values are −VREF /2 and +VREF /2. The sub-DAC outputs are subtracted
from the input and multiplied by the appropriate gain G. Ideally the gain should scale
the residual error to |ri | ≤ VREF , the input range of the subsequent stage. The input volt-
age X can be represented in terms of the error voltage, e, and sub-DAC outputs. The
representation of X in terms of the first stage error voltage, e1 , and sub-DAC output, q1 ,
is
1
X = e 1 + q1 − VREF (3.1)
2
The first stage residual voltage, r1 , can be written in terms of the corresponding values
from the next stage in the pipeline.
1
r1 = G1 e1 = e2 + q2 − VREF (3.2)
2
e2 1 1 VREF
X= + q1 − VREF + q2 − (3.3)
G1 2 2 G1
The error voltage e2 is, in turn, amplified and quantized by Stage 3, refining the repre-
sentation of X.
e3 1 1 VREF 1 VREF
X= + q1 − VREF + q2 − + q3 − (3.4)
G1 G2 2 2 G1 2 G1 G2
This process continues throughout the remaining stages of the pipeline. For the N -stage
converter, the input voltage X is represented in terms of the quantized outputs of the N
stages and the error voltage eN as
eN 1 1 VREF 1 VREF
X = + q1 − VREF + q2 − + q3 −
G1 G2 G3 . . . GN −1 2 2 G1 2 G1 G2
1 VREF 1 VREF
. . . + qN −1 − + qN − (3.5)
2 G1 G2 G3 . . . GN −2 2 G1 G2 G3 . . . GN −1
Equation 3.5 contains all required terms to form the digital output code for this N -stage
converter. The digital output is given by:
+ . . . qN −2 (GN −2 GN −1 ) + qN −1 GN −1 + qN (3.6)
Often, pipeline ADCs are designed using identical stages. If the N -stage converter was
designed using N identical stages the digital output could be re-written as:
D = q1 GN −1 + q2 GN −2 + q3 GN −3 + . . . qN −2 G2 + qN −1 G + qN (3.7)
Figure 3.2 shows the residual characteristics for 1-bit ideal pipeline stage and
pipeline stage with sub-ADC, sub-DAC and interstage gain errors. Sub-ADC error can
be fixed by modifying a pipeline stage. Sub-DAC and interstage gain errors cannot be
fixed by implementing stage modifications alone. Rather, new techniques are required
to address these errors.
Vout
+VREF +VREF
Vin Vin
q=0 q=1
−VREF −VREF
REF
+VREF
−VREF
+VREF
−V
(a) comparator offset (sub-ADC error) (b) charge injection (sub-DAC error)
Vout
+VREF
Vin
−VREF
−VREF
+VREF
Figure 3.2: Residual error plots for 1-bit per stage ideal pipeline ADC (blue) and
pipeline ADC with errors (red).
VREF
G(VF S − VDAC ) = VF S , where VDAC = .
2
G VREF
VF S = (3.8)
G−1 2
The new quantization interval is now given by Q = 2VF S /2n , where n is the number of
bits.
Reducing an interstage gain allows for variations in threshold voltages of the
sub-ADC comparators. Figure 3.3 shows the residual error characteristics for the 1-bit
per stage architecture and allowed threshold voltage change (∆VADC ) before the full
scale range of the next stage is reached. The allowed variations in a threshold voltage of
a sub-ADC comparator for a converter with the arbitrary gain is given by:
VREF 1
∆VADC =± −1 (3.9)
2 G−1
For the 14-bit, 16 stage example introduced above, the gain of 1.81 is used and VREF
is set to 1V. The full scale range of the converter is VF S = 1.12 V. This accommodates
±0.12 V variations in the threshold voltage of the sub-ADC comparator.
G VREF
2
∆VADC
V in
Figure 3.3: Residual error characteristics and allowed threshold voltage variations.
The role of the sub-DAC block is to provide an estimate of the input signal
voltage to the next stage. For a 1-bit per stage architecture, the desired sub-DAC output
is (q − 12 )VREF , where q is the digital decision level obtained by sub-ADC and VREF is
the sub-DAC reference voltage. Figure 3.2(b) shows the effect of the sub-DAC error on
the stage compared to the ideal transfer characteristics of the stage. Unlike comparator
offset errors (Figure 3.2(a)), errors in the sub-DAC output change the voltage passed to
subsequent stages, and ultimately distort the ADC output. If ∆DAC1 , ∆DAC2 and ∆DAC3
represent sub-DAC errors in the first three stages of the N -stage converter discussed in
Section 3.1, then (3.4) can be re-written as
e3 1 1 VREF 1 VREF
X = + q1 − VREF + q2 − + q3 −
G1 G2 2 2 G1 2 G1 G2
∆DAC2 ∆DAC3
+∆DAC1 + + (3.10)
G1 G1 G2
φ1
φ1
C2
Vin
C1 −
Vout
φ2 +
+VDAC q
−VDAC
Figure 3.4: Switched capacitor implementation of the MDAC for 1-bit per stage archi-
tecture.
From (3.10) it can be seen that the sub-DAC error associated with a stage scales down
by the total gain factor of all previous stages. Stages near the pipeline front end are
especially critical, and tend to dominate these error contributions.
Figure 3.2(c) shows the gain error effect compared to the ideal transfer character-
istics of the stage. The gain error changes the slope of the residual curve. Many modern
pipeline converters are implemented using switched capacitor circuits [47]. This tech-
nology is suitable for high-speed, low power and monolithic CMOS implementations of
pipeline ADCs. For CMOS implementations, the S/H block, sub-DAC and gain block
are implemented together in what is known as a multiplying digital-to-analog converter
(MDAC). Figure 3.4 shows switched capacitor implementation of the MDAC for 1-bit
per stage architecture. Non-overlapping clocks, φ1 and φ2 , control the switches of the
MDAC. During φ1 , the input voltage is sampled onto two capacitors, C1 and C2 . During
φ2 , C2 is connected to the amplifier through the feedback loop and C1 is sampling one
C1 C1
Vout = 1+ Vin − VDAC , (3.11)
C2 C2
where VDAC can be either +VDAC or −VDAC , depending on the sub-ADC output q.
From (3.11) it can be seen that the two capacitors in the MDAC block determine the
value of gain. If there is a mismatch in one of the capacitor values, C1 + ∆C1 instead of
C1 , the gain would be altered as
C1 ∆C1 C1 ∆C1
Vout = 1+ + Vin − + VDAC . (3.12)
C2 C2 C2 C2
Analog calibration schemes use the analog signal path and extra analog circuitry
to apply corrections to the stage being calibrated [21, 34–36]. The idea behind analog
calibration is to estimate dominant stage errors and then adjust required voltages and
gains back to their nominal values. These techniques adjust the threshold voltage of
Set q7 = 0 to find S1
9
Set q 7 = 1 to find S2
+V REF
S1
V in
q=0 S2 q=1
−VREF
+V REF
−VREF
(b) Residual error plot of 1-bit per stage architecture with errors.
Figure 3.5: Pipeline ADC with off-line digital calibration applied to the seventh stage.
Figure 3.5 illustrates the foreground calibration process derived in [28] for a
single stage of a pipeline ADC. The illustrated case is based on the implementation
of a 14-bit ADC with 16 identical stages, interstage gains less than two, and 1-bit per
stage topology. Gains less than two are chosen for all 16 stages so the output of each
stage does not saturate the remaining stages. Calibration begins with the least signifi-
cant stages (the end of the pipeline) and progresses toward the most significant stages.
For example, to calibrate stage 7, we must assume that stages 8-16 have already been
calibrated, or have been fabricated to sufficient accuracy that calibration is not needed.
Figure 3.5(a) shows the off-line digital calibration applied to the seventh stage of a
16-stage architecture. Figure 3.5(b) shows residual characteristics for the stage being
calibrated. Following calibration of the seventh stage, the process continues with the
sixth stage, and so on until the first stage is reached and the calibration of the converter
is complete.
Equation 3.6, derived in Section 3.1, describes the digital output of the N -stage
converter. Bit seen at the output of each stage is given a weight indicated by the gain
products given in parenthesis. Most pipeline ADCs use ‘nominal’ design gains to con-
struct the digital output. This approach is correct only if the converter is free of any
gain or sub-DAC errors. If the implemented gain is different from the design value, or
if sub-DAC errors exist, there will be error in the ADC output. Making these weights
programmable is the idea behind most of digital calibration techniques. This is the case
for the calibration algorithm derived by Karanicolas et al., where the correction terms
ωi are programmable and are updated each time a stage is calibrated. Equation 3.6 can
be re-written in terms of these weights,
N
X
D= qi ωi , (3.13)
i=1
Setting q7 =1 (Vin =0) forces Stage 7 to operate on the right segment, producing residual
voltage S2 . S2 is quantized by the remaining pipeline stages to give a digital output DS2 .
The pipeline output in this case is
For a consistent digital output, ω7 should be selected so (3.14) and (3.15) agree. Setting
(3.14) and (3.15) equal to each other gives the expression for ω7 .
The residual voltage terms S1 and S2 for a single stage are identified in Fig-
ure 3.5(b). Once the digital representations DS1 and DS2 for the residual voltages S1
φ2
Figure 3.6: Example of a two-phase, non-overlapping clock signal used in pipeline ADC
architecture.
and S2 are found, the correction term ωi can be obtained. The correction term ωi is fed
back to the digital encoder and calibration logic block. This value is a weight associ-
ated with the bit of the stage being calibrated and it carries the information about the
interstage gain and sub-DAC errors.
The off-line calibration algorithm discussed above states that the correction terms,
ωi ’s, can be found for all pipeline stages starting with the least significant stage and
progressing towards the most significant stage. In practice, calibration of the least sig-
nificant stages is not required since the converter error is dominated by the first few
stages of the pipeline. Current process technology easily accomplishes 8-bit accuracy
without calibration, suggesting that the last 7 stages (1 bit/stage topology) need not be
calibrated. Simulations have verified this, and suggest that starting calibration at the
least significant stages may actually degrade performance [57].
D = q1 GN −1 + q2 GN −2 + q3 GN −3 + . . . qN −2 G2 + qN −1 G + qN (3.17)
From (3.17) it can be seen that there is a weight associated with each bit of the stage.
When calibration occurs, Stage 3 becomes the first stage of the pipeline, and should be
given weight GN −1 . Similarly the weights associated with the other stages need to shift
to reflect the reorganization of the pipeline. The weights for Stages 1, 2, 3, ..., need to
be available at location of Stages 3, 4, 5, ..., respectively for the correct formation of the
final digital output during the calibration.
Figure 3.7 shows the proposed continuous time digital calibration architecture
48
9 0 D0 1 D1 2 D2 3 D3 C5 DC5 4 D4 5 D5 ...
10 0 D0 1 D1 2 D2 3 D3 C5 DC5 4 D4 5 D5 ...
11 -1 D−1 0 D0 1 D1 2 D2 3 D3 C5 DC5 4 D4 5 D5 ...
12 -1 D−1 0 D0 1 D1 2 D2 3 D3 C5 DC5 4 D4 5 D5 ...
13 -1 D−1 0 D0 1 D1 2 D2 3 D3 C5 DC5 4 D4 5 D5 ...
14 -1 D−1 0 D0 1 D1 2 D2 3 D3 C5 DC5 4 D4 5 D5 ...
15 -1 D−1 0 D0 1 D1 2 D2 3 D3 C5 DC5 4 D4 5 D5
16 -1 D−1 0 D0 1 D1 2 D2 3 D3 C5 DC5 4 D4 5 D5
17 -1 D−1 0 D0 1 D1 2 D2 3 D3
18 -1 D−1 0 D0 1 D1 2 D2 3 D3
Table 3.1: Sample propagation through the pipeline for the proposed real-time digital calibration technique.
Alma Delić-Ibukić, August, 2008
Vin
STAGE 1 STAGE 2 STAGE 3 STAGE 4 STAGE 5 STAGE 6 STAGE 7 STAGE 8 STAGE 9 STAGE 10
49
6 ω3 / G5 ω4 / G4
ω1 / G7 ω2 / G G3 G1
G2 G0
cal. cal. G7 G5 cal. cal. G3 cal. cal. cal. cal.
cal. G6 cal. G4 G2 G1
logic logic logic logic logic logic logic logic logic G0 logic
Finite State Machines (FSMs) have been shown to be very efficient in modelling
sequential circuits [77]. The designed state machine controls the calibration process of
each stage, the predetermined data path shift that occurs during calibration, activation of
the extra two stages at the end of the pipeline, and writing of the corrected ωi value back
to the pipeline stage being calibrated. Two passes per stage are necessary to determine
the correction term ωi for that stage. A state machine was designed for a 14-bit pipeline
ADC implemented using 16 identical stages with gains less than two and 1-bit per stage
1
(q )VREF
sub i 2
ADC
sub
DAC
0 or 1
controlled by the
finite state machine
q
i
sampling rate for the converter implemented is 51.2 MHz. At this speed, the converter
requires a total time of 3 µs to complete a calibration of 7 stages.
In addition to monitoring the calibration status of a stage, the clock counter is
responsible for setting and resetting different calibration lines for each stage. Calibration
lines have functions such as forcing the input to a sub-DAC to 0 or 1 when a stage is
being calibrated, changing the input data path, activating the extra two stages at the
end of the pipeline, monitoring the correct digital output collection sequence during
calibration period and writing the corrected term after calibration back to the calibrated
stage. Once all 7 stages have been calibrated the state machine is idle until the next
calibration signal is initiated.
Pipeline stages must be modified for the FSM to be able to make adjustments to
a stage while calibrating. All odd stages in the pipeline need to be capable of switching
a data path during the calibration process. Also, stages being calibrated must have
an option to select a ground for an input and to select forced sub-DAC inputs at the
calibration instant. The calibration instant for a given stage is controlled by the FSM.
Figure 3.8 shows the additional digital logic required by a stage being calibrated.
Most of the modifications regarding the digital calibration techniques are made
inside the digital encoder block. Digital calibration relies on measuring the error con-
tributions of the stage in digital domain and using these measured values to form the
ADC output code. The digital encoder block is where the ADC output code is formed,
therefore it plays a major role during the calibration process.
For the real-time digital calibration technique described in Section 3.4.2, the
digital encoder block must:
1. Form the ADC output code during normal operation of the converter.
2. Form the ADC output code during calibration process without interrupting the
converter’s operation.
3. During calibration process, obtain the correction terms to be used to form the
ADC output and write these terms back to a stage being calibrated for later use.
Figure 3.9 shows the digital encoder block modification for an N -stage converter
with 1-bit per stage architecture and two additional stages at the end of the pipeline
used during calibration. The digital encoder block consists of N + 2 adders (including
the extra two stages) pipelined together. The logic controlling the first seven adders is
different from the rest of the pipeline because the first seven stages can be calibrated.
During the normal converter operation each stage provides the digital encoder block with
the intermediate bit, qi , where i designates the stage number. Depending on the value
of qi , these weights will be added accordingly to form the ADC output code. The first
seven stages of a pipeline ADC have programmable weights initially set to ωi = Gi−1
and replaced as the correction term ωi is obtained during the calibration process. During
the calibration period, select lines from the FSM control the data path changes between
the stages to prevent interruption of the normal converter operation. For example, Stage
3 acts as a first stage in a pipeline when forming the coarse digital output. This select line
N−1 N−2
G G
+ + +
controlled by the
finite state machine
54
+ + +
−
Corrected weight
for a stage
Sub−DAC input
is set to 1.
q qN+1
N
qN+2
0
G FLAG FLAG OBTAINING CORRECTION TERMS
FLAG
determined by the
TWO EXTRA STAGES USED DURING CALIBRATION PROCESS finate state machine.
Figure 3.9: Modified error correction logic for a real-time digital calibration scheme implementation. Example of N -stage converter
with 1-bit per stage architecture.
is used only for one clock cycle at the start of the calibration procedure. The FSM lines
also control the use of the second set of weights which are attributed to each stage for
use during calibration process, and the FSM lines enable calibration of a stage itself. If
a particular stage is being calibrated, the coarse digital output for that stage is set to zero
(and later, to one) and the rest of the pipeline resumes the normal converter operation to
obtain the correction term ωi for the calibrated stage. The FSM select lines also control
the stages from which the ADC output will be taken. The green lines labelled FLAG in
Figure 3.9, are used during the calibration process to allow each stage to communicate
to the next stage if the second set of weights is to be used when adding the previous stage
output. All flags (except stages 1 and 2) are set to one at the start of calibration cycle.
Each stage then latches the value of FLAG from the previous stage on every clock edge.
The FLAG values propagate through the pipeline as an indicator that the corresponding
sample has been shifted in the pipeline, and the second set of weights should be used
when forming the ADC output code.
The calibration scheme was implemented using Verilog HDL and simulated us-
ing the Verilog-XL simulator. The real-time calibration technique was derived for a
14-bit ADC with 1-bit per stage architecture implemented using 18 identical stages (in-
cluding two extra stages for calibration purposes). The last two stages in the pipeline
are active only during the calibration process. To verify that the real-time calibration
technique works, it was necessary to model a pipeline stage in Verilog HDL and also to
control gain, threshold and sub-DAC reference voltages of the stages being calibrated.
To model the behavior of the pipeline ADC, fully digital odd and even stages were cre-
ated using Verilog HDL. Gain, threshold and sub-DAC reference voltages were made
control variables at the input of each simulated pipeline stage. The nominal gain for all
18 stages was set to 1.81. The input range (VF S ) for this converter was set to ±1.12
20
10
+2 LSB
0
−2 LSB
calibration starts
−10
−20
real−time calibration (Verilog HDL)
Figure 3.10: Residual error characteristics for a simulated ADC with applied real-time
calibration and errors introduced in all 18 stages of the converter.
V and the reference voltage for the converter was set to VREF = 1 V. A sampling fre-
quency of 51.2 MHz was used and the sinusoidal test signal was set to 150 kHz with the
amplitude at -1 dBFS (994 mV). Errors were introduced in all 18 stages (including two
extra stages used during calibration) of the converter and 1024 samples were collected.
Capacitor matching error between 0.1-0.5% was simulated. For threshold voltage varia-
tions, an error up to 10% of VF S was simulated. This is the maximum error allowed for
the chosen gain. Verilog-XL simulation results were collected and evaluated in MAT-
LAB. Figure 3.10 shows the residual error characteristics for a simulated 14-bit ADC
calibrated in a real-time. Before activating the calibration signal, the error contributions
from all 16 stages on the final resolution of an ADC is evident in Figure 3.10. The ADC
behaves as a 10-bit converter before calibration and as 12.7 bit converter after calibra-
tion. Once the calibration signal is activated, 154 clock cycles are needed for completion
of the calibration process.
∆Σ G(z)
∆Σ G(z)
∆Σ G(z)
uM−1[n] uM−1
* [n−d]
y[n]
∆Σ G(z)
uM [n] uM
* [n−d]
nal transfer function ST F (z) = z −m , as discussed in Section 2.4.3. The signal transfer
function introduces a fixed delay of m samples to each channel of the Π∆Σ ADC. Also,
to further simplify the analysis, the ∆Σ modulator and lowpass filter G(z) are grouped
into one system G̃(z). The delay introduced by G̃(z) contains delays introduced by both
the ∆Σ modulator and the lowpass filter G(z).
After the input signal x[n] is modulated by ur [n], the modulated input is passed
on to the system G̃(z). The output of G̃(z) is demodulated by a delayed sequence
u∗r [n − d], with ∗ indicating a complex conjugate and d indicating a delay through G̃(z),
which must be an integer value. The output of the overall system y[n] is then given by
∞
M X
X
y[n] = (g̃[k]x[n − k]ur [n − k])u∗r [n − d]
r=1 k=0
X∞ M
X
= g̃[k]x[n − k] ur [n − k]u∗r [n − d] (4.1)
k=0 r=1
Because (4.2) contains zeros that are periodically spaced, a comb sequence can be de-
fined such that
1, if k = 0, ±M, ±2M, ...
CM [k] = (4.3)
0, otherwise
∞
X
y[n] = g̃[k]x[n − k]CM [k − d] (4.4)
k=0
For the output y[n] in (4.4) to preserve the input signal x[n], g̃[n] is restricted to
1, if n = d
g̃[n] = 0, if n = d ± M, d ± 2M, ... (4.5)
arbitrary, otherwise
By restricting g̃[n], the output y[n] of the modulation based parallel ∆Σ architecture is
a delayed version of the input signal x[n], namely y[n] = x[n − d]. Constraint (4.5) puts
a restriction on the design of the lowpass filter impulse response g[n]. The delay d is
comprised of two components, ∆Σ modulator delay m and a filter delay dg , such that
dg = d − m. Therefore, for (4.5) to hold, an optimal filter g[n] is restricted to
1, if n = dg
g[n] = 0, if n = dg ± M, dg ± 2M, ... (4.6)
arbitrary, otherwise
∆Σ G(z) D
s2 [n] h 2[n]
∆Σ G(z) D
s3 [n] h 3[n]
∆Σ G(z) D
sM [n] h M [n]
∞
M X
X
y[n] = (g̃[k]x[n − k]sr [n − k])sr [n − d]
r=1 k=0
X∞ M
X
= g̃[k]x[n − k] sr [n − k]sr [n − d] (4.8)
k=0 r=1
Because the sequence sr [n] is taken from a Hadamard matrix H that has a property
HH T = M I, the second summation in (4.8) is equal to
M
X M, if k = d, d ± M, d ± 2M, ...
sr [n − k]sr [n − d] = (4.9)
r=1 0, otherwise
Equation 4.9 has periodically spaced zeros and as such can be written in terms of the
comb sequence that was defined in (4.3). Rewriting (4.8) in terms of CM [k] gives
∞
X
y[n] = M g̃[k]x[n − k]CM [k − d] (4.10)
k=0
By restricting g̃[n] the overall output of the Hadamard modulated parallel ∆Σ A/D con-
verter y[n] is a delayed version of the input signal, namely y[n] = x[n − d]. The
constraint (4.11) puts a restriction on the design of the lowpass filter g[n]. The overall
delay through G̃(z) is given by d = m + dg , where m is the delay through an Lth or-
der modulator and dg is a delay through a lowpass filter G(z). For (4.11) to hold, the
impulse response g[n] is restricted to
1/M, if n = dg
g[n] = 0, if n = dg ± M, dg ± 2M, ... (4.12)
arbitrary, otherwise
$ %!
D−1
n+d+ 2
sr [n] = hr , (4.13)
D
where D is the oversampling ratio, d is the delay through the system G̃(z), and the inner
brackets round towards minus infinity. The delay d is given by
J −1
d= +m (4.14)
2
where J is the length of a lowpass filter G(z) and m is the delay through the Lth order
∆Σ modulator. To obtain an integer result for a total system advance, J and D are either
both even or both odd integers.
Alternative filter architectures that are not restricted to (4.12), and are simpler
to implement can be used in the design of G(z). The lowpass filter G(z) must be de-
signed to minimize the quantization noise contribution in a desired signal band. In the
case of conventional ∆Σ converter architectures, the in-band quantization noise power
is reduced by using comb filters that have zeros placed at 1/D and its multiples, where
D is the oversampling ratio as was discussed in Section 2.4.3. For the parallel ∆Σ ar-
chitecture converters, the overall quantization noise power comes from the contribution
of M parallel channels [19]. Hardware efficient filters for Π∆Σ converter architectures
that minimize the overall in-band quantization noise power are derived in [19]. The
L+1 L+1
1 − z −DM
1
G(z) = (4.15)
DM 1 − z −1
L L
1 − z −DM 1 − z −(DM +1)
1 1
G(z) = . (4.16)
DM DM + 1 1 − z −1 1 − z −1
x[n] k1 z −1 k2 z −1 y[n]
+ 1−z −1 + 1−z −1
− −
Figure 4.3: Linear model for a second order ∆Σ modulator used in simulations.
The ST F (z) is the signal transfer function and N T F (z) is the noise transfer func-
tion which are described in Section 2.4.3. The 1-bit quantizer is modelled as an addi-
tive white noise source e[n] with samples uniformly distributed within ±Q1 /2 interval,
where Q1 is the quantization interval described in Section 2.4.1. For a 1-bit quantizer,
the quantization interval is given by Q1 = 2VREF /2 = VREF , where ±VREF is the
allowable input signal range of the quantizer (1-bit ADC).
A general setup for an M -channel oversampling Π∆Σ converter architecture
is shown in Figure 4.2. Equation (4.7) was used to generate Hadamard (de)modulation
sequences for 8-channel and 16-channel Π∆Σ ADCs and (4.13) is used to create a front-
end Hadamard modulation sequence that takes into account oversampling. The 8 × 8
1 1 1 1 1 1 1 1
1 −1 1 −1 1 −1 1 −1
1 1 −1 −1 1 1 −1 −1
1 −1 −1 1 1 −1 −1 1
H2 =
.
1 1 1 1 −1 −1 −1 −1
1 −1 1 −1 −1 1 −1 1
1 1 −1 −1 −1 −1 1 1
1 −1 −1 1 −1 1 1 −1
The rth row of the Hadamard matrix corresponds to modulation sequence for the rth
channel, and each column represents the time instance. Although the Hadamard modu-
lation sequences are not simply a frequency decomposition, the modulation sequences
do have distinct and recognizable spectral characteristics. For the eight-channel exam-
ple, rows three and four have the same fundamental frequency FS /4, where FS is the
Nyquist-rate clock, but differ in phase. The same is true for rows five, six, seven and
eight which share the same frequency FS /8. Figure 4.4 illustrates the frequency content
of the rows of an 8 × 8 Hadamard matrix. Numbers 1 though 8 correspond to Hadamard
matrix rows. Each channel (or multiple channels) of a Π∆Σ architecture modulates dif-
ferent frequency band of an input signal with bandwidth of FS /2. The noticeable bumps
in the noise floor mimic the noise shaping function of ∆Σ modulators.
Figures 4.5 and 4.6 show simulation results for an 8-channel and a 16-channel
Π∆Σ converter implemented using an oversampling ratio of D = 4 and a single tone
input signal. The signal amplitude was at -1 dB of full scale (dBFS). The noticeable
bumps in the noise floor are due to the noise shaping transfer function N T F (z) of a
2nd order ∆Σ modulator. In both cases, the input bandwidth FS /2 is preserved by the
oversampling Π∆Σ converter architecture. Also, the Hadamard decomposition of the
0 FS FS 3 FS FS F
8 4 8 2
−20
−40
Magnitude, dBFS
−60
−80
−100
−120
−140
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Normalized Frequency
Figure 4.5: Simulation results for an 8-channel Π∆Σ A/D converter with oversampling
ratio D = 4. Normalized frequency is given by F/FS .
ENOBΠ∆Σ=10.48 bits
−20
ENOB∆Σ=12.65 bits
−40
Magnitude, dBFS
−60
−80
−100
−120
−140
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Normalized Frequency
Figure 4.6: Simulation results for a 16-channel Π∆Σ A/D converter with oversampling
ratio D = 4. Normalized frequency is given by F/FS .
The Π∆Σ architecture described in Section 4.2 shows one way of trading circuit
complexity for increased resolution and/or bandwidth. However, the wide-bandwidth
and high-resolution results are achieved only if all M -channels in the parallel archi-
tecture are identical and Hadamard modulation sequences are in-sync. Channel mis-
matches are usually caused by variations in the manufacturing process. To preserve the
wide bandwidth and/or resolution that parallel converter architectures offer, errors such
as channel gain and offset mismatches need to be addressed. Following the discussion
of dominant errors in parallel architecture converters, an overview of current calibration
techniques suitable for Π∆Σ converter architectures is given.
Besides the nonidealities that come with conventional ∆Σ modulators, Π∆Σ ar-
chitecture converters are sensitive to channel gain mismatches, offset mismatches and
Hadamard modulation level errors [18, 19, 64, 70, 71]. To simplify the analysis of chan-
nel mismatch errors in Π∆Σ converters, a Hadamard modulated converter without over-
sampling is analyzed. Figure 4.7 shows an ideal M -channel Π∆Σ converter architecture
without oversampling. The sequence hr [n] = hr,n mod M indicates row elements of the
M × M Hadamard matrix. Each channel, as before, consists of a conventional Lth order
∆Σ modulator that is assumed to introduce a constant delay of m samples, and decimat-
ing lowpass filter G(z). The lowpass filter G(z) and ∆Σ modulators are grouped into
one system, G̃(z). The system G̃(z) introduces a delay d that consists of both, delay
through the filter and ∆Σ modulator.
Dominant errors in Π∆Σ architecture converters are channel gain and offset
mismatch errors [18, 19, 64]. These errors introduce undesirable frequency tones in the
converter output, affecting its overall linearity and degrading the spurious-free-dynamic-
range (SFDR) and signal-to-noise-ratio (SNR). Figure 4.8 shows a model used to ana-
∆Σ G(z)
h2 [n] h 2[n−d]
∆Σ G(z)
h3 [n] h3 [n−d]
∆Σ G(z)
hM−1[n] hM−1[n−d]
y[n]
∆Σ G(z)
hM [n] hM [n−d]
gain, ar
x[n] wr [n] yr [n]
1+ ε r
~
G(z)
Figure 4.8: Model for gain and offset error in rth channel of Π∆Σ converters.
∞
!
X
yr [n] = g̃[k](1 + εr )x[n − k]hr [n − k] + br hr [n − d]
k=0
∞
!
X
= g̃[k]x[n − k]hr [n − k] hr [n − d]
k=0
∞
!
X
+ g̃[k]εr x[n − k]hr [n − k] hr [n − d] + br hr [n − d] (4.18)
k=0
M
X
y[n] = yr [n]
r=1
X∞ M
X
= g̃[k]x[n − k] hr [n − k]hr [n − d]
k=0 r=1
X∞ M
X M
X
+ g̃[k]x[n − k] εr hr [n − k]hr [n − d] + br hr [n − d]
k=0 r=1 r=1
∞
X M
X
= x[n − d] + g̃[k]x[n − k] εr hr [n − k]hr [n − d]
k=0 r=1
M
X
+ br hr [n − d] (4.19)
r=1
From (4.18) and (4.19) it can be seen that offset errors br are signal independent.
At the output of each channel, the offset errors are modulated by a delayed version
of hr [n], a single row of the M × M Hadamard matrix. As shown in Section 4.2.2, an
M ×M Hadamard matrix introduces frequency tones throughout the frequency spectrum
at multiples of 1/M of the Nyquist-rate clock FS . Therefore, with the offset errors
present, the output spectrum of y[n] will contain frequency tones at FS /M and multiples
of FS /M .
−20
−40
Magnitude, dBFS
−60
−80
−100
−120
−140
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Normalized Frequency
Figure 4.9: Simulations results for a 16-channel Π∆Σ A/D converter with oversampling
ratio D = 4 and offset errors introduces in each channel. Normalized frequency is given
by F/FS .
−20
−40 F /4+F
S IN
FS/2−FIN
F /2+F
Magnitude, dBFS
S IN
−60
FS/4−FIN 3F /8−FIN
FS/8+FIN S
FS/8−FIN
−80 3FS/8+FIN
−100
5FS/16,1
7FS/16,1
FS/16,1
FS/16,−1 5FS/16,−1 7F /16,−1
3FS/16,−1 3FS/16,1 S
−120
−140
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
Frequency (MHz)
Figure 4.10: Simulations results for a 16-channel Π∆Σ A/D converter with oversam-
pling ratio D = 4 and gain errors introduces in each channel. Labelled are gain error
spectrum peak locations fε .
1/M of the Nyquist-rate clock FS before being modulated by the input frequency FIN .
However, unlike offset errors, gain errors are signal dependent and their spectrum peaks
occur at
FS
fε = i ± FIN , i = 1, 2, 3...M/2, (4.20)
M
A novel real-time digital calibration approach that removes gain mismatch errors
between channels of Π∆Σ ADCs is described below. Calibration is accomplished by
adding an additional channel that is linearly dependant on the Π∆Σ channels used.
This redundancy in the system allows for gain errors within channels to be successfully
corrected.
The model used to analyze gain and offset errors in the rth channel of a Π∆Σ
converter was introduced in Section 4.3 and is shown in Figure 4.8. The general ex-
pression for the output of rth -channel before demodulation, including channel gain and
offset errors, is given by
∞
X
wr [n] = g̃[k](1 + εr )x[n − k]hr [n − k] + br
k=0
∞
X
= g̃[k]ar x[n − k]hr [n − k] + br (4.21)
k=0
The coefficients αr must be non-zero, and should preferably have equal magnitude, so
that each Π∆Σ channel is given equal importance. The latter is a desirable but not a
necessary condition for the calibration to be successful. Depending on the number of
channels used in the Π∆Σ architecture, solutions for αr of equal magnitude may or may
not exist. A computer search algorithm can be used to determine possible αr coefficients
which lead to hc [n] = ±1. An M × 1 candidate solution vector α can be found using
1
α[i] = Hhc [i] (4.23)
M
∞
X
wc [n] = g̃[k](1 + εc )x[n − k]hc [n − k] + bc
k=0
∞
X
= g̃[k]ac x[n − k]hc [n − k] + bc (4.24)
k=0
where ac is total gain in the calibration channel including the gain error εc , and bc is the
calibration channel offset error. Substituting (4.22) into (4.24) leads to the following
∞
M X
X
wc [n] = g̃[k]ac x[n − k]αr hr [n − k] +bc . (4.25)
r=1 k=0
| {z }
The expression over the brace in (4.25) can be written in terms of Π∆Σ channel outputs
wr [n] described by (4.21),
M
X α r ac
wc [n] = (wr [n] − br ) + bc
r=1
ar
M M
!
X α r ac X αr ac
= wr [n] + bc − br (4.26)
r=1
ar r=1
ar
The first term of (4.26) contains information about gain errors of each channel
and the second term contains the sum of offsets found in each channel, including the
calibration channel. Equation (4.26) can be rewritten
M
X
wc [n] = β0 + βr wr [n] (4.27)
r=1
M
X
wc [n] = βr wr [n] (4.28)
r=0
where every sample of w0 [n] is a 1, and wr+1 [n] are rth channel outputs.
Any least-squares procedure can be used to find coefficients βˆr which best pre-
dict the known calibration channel output wc [n] from the given M channel outputs. Di-
viding coefficients βˆr for r = 1, 2, ..., M by αr provides an estimate cr = βˆr /αr ≈ ac /ar
which is proportional to the reciprocal of the unknown gain for each channel. Scaling
channel outputs of Π∆Σ converter by cr effectively removes gain mismatches.
To solve for βˆr coefficients, an adaptive recursive least squares (RLS) algorithm
is used. The RLS algorithm is independent of the input signal statistics, capable of
realizing fast convergence rate, and can be modified to work in nonstationary envi-
ronment [81]. Figure 4.11 shows the Π∆Σ converter modified to include calibration
of channel gain mismatches. To correctly formulate the least squares solution for the
unknown coefficients, the effect of quantization noise in each channel of the Π∆Σ con-
verter must be examined.
Up to now, the analysis of Π∆Σ ADCs was carried out with ∆Σ modulators
modelled by only their signal transfer function ST F (z). The ∆Σ modulators were
discussed in Section 2.4.3 and the general expression for the output of an Lth order ∆Σ
modulator was derived to be
h 1 [n] h 1 [n−d]
w2[n]
∆Σ G(z) c2
h 2 [n] h 2 [n−d]
w3[n]
∆Σ G(z) c3
h 3 [n] h 3 [n−d]
wM−1[n]
∆Σ G(z) c M−1
c
h M [n] h M [n−d]
wc [n]
∆Σ G(z) RLS
c
Algorithm
h c [n]
Z 1
2Q2B 2 2
σv2 = N T F (ej2πf )G(ej2πf ) df
12 0
Z 1
Q2B 2 2
= (2 sin πf )2L G(ej2πf ) df (4.30)
6 0
where Q2B /12 is the quantization error power that was derived in Section 2.4.2. N T F (ej2πf )
and G(ej2πf ) are the frequency responses of the noise shaping filter and the lowpass fil-
ter, respectively.
x[n] w1 [n]
∆Σ G(z) c1
v2 [n]
h 1 [n] h 1 [n−d]
w2[n]
∆Σ G(z) c2
v3 [n]
h 2 [n] h 2 [n−d]
w3[n]
∆Σ G(z) c3
h 3 [n] h 3 [n−d]
vM−1 [n]
wM−1[n]
∆Σ G(z) c M−1
vM [n]
h M−1[n] h M−1 [n−d]
wM [n] y[n]
∆Σ G(z) cM
vc [n] c
h M [n] h M [n−d]
wc [n]
∆Σ G(z) RLS
c
Algorithm
h c [n]
Figure 4.12: Parallel ∆Σ ADC modified to include gain calibration and filtered quanti-
zation noise vr [n].
M
X
w̃c [n] = βr wr [n] + vc [n]. (4.31)
r=0
An adaptive RLS algorithm can be used to find coefficients βˆr that best predict the
known calibration channel w̃c [n] from the given M channel outputs wr [n]. However,
from Figure 4.12 it can be noticed that only a corrupted version of wr [n] is available and
is given by
w̃r [n] = wr [n] + vr [n] (4.32)
Equation (4.31) can be rewritten in terms of these available channel outputs w̃r [n],
M
X
w̃c [n] = βr (w̃r [n] − vr [n]) + vc [n]
r=0
XM M
X
= βr w̃r [n] − βr vr [n] + vc [n] (4.33)
r=0 r=0
The RLS algorithm performance that is based on the corrupted set of channel outputs
w̃r [n] is expected to differ from the ‘ideal’ case described by (4.31), and these perfor-
mance deviations (e.g. the convergence rate of the RLS algorithm) are explored in the
subsequent sections.
Before looking at the convergence rate of the RLS algorithm in two distinct
environments (i.e. where filtered quantization noise vr [n] is and is not present at the
output of M channels), a summary of the RLS algorithm and definitions of parameters
used in the algorithm is given. The RLS algorithm is summarized in Table 4.1 [81, 82],
P [n − 1]w̃[n]
k[n] =
λ + w̃T [n]P [n − 1]w̃[n]
w̃[n] = [w̃0 [n], w̃1 [n], w̃2 [n], ..., w̃M [n]]T (4.34)
with each element described by (4.32). The first element w̃0 [n] is always 1, and w̃r [n]
for r = 1, 2, ..., M are outputs of M channels at time n (i.e. RLS algorithm training
samples). The vector β̂[n] is a vector of estimated coefficients at training instant n that
best fit the solution to (4.33). It is defined as
β̂[n] = [βˆ0 [n], βˆ1 [n], βˆ2 [n], ..., β̂M [n]]T . (4.35)
The initialization vector α is the vector of known coefficients that are used to find the
modulation sequence of the calibration channel hc [n]. By design, α is composed of only
±1’s as defined in (4.22).
M
!
X
Q[n] = E (β̂r [n] − βr )2
r=0
= E (β̂[n] − β)T (β̂[n] − β) (4.38)
n
X
β̂[n] − β = Φ−1 [n] w[i]vc [i] (4.39)
i=1
where vc [n] is filtered quantization noise contribution from the calibration channel w̃c [n].
For the case when w̃[n] = w[n], this is the only noise contribution to the RLS algorithm.
The RLS algorithm can be shown to converge under two common assumptions [82]:
Assumption-1: The input vectors w[n], for n = 1, 2, 3, ... are independently and identi-
cally distributed.
Assumption-2: The input vectors w[n], for n = 1, 2, 3, ... are drawn from a stochas-
tic process with a multivariate Gaussian distribution of zero mean and
1
ensemble-averaged correlation matrix R = lim Φ[n].
n→∞ n
M σv2
Q[n] = nM +1 (4.40)
n σw2
To analyze the performance of the RLS algorithm in the presence of the filtered
quantization noise, the coefficient error vector described in (4.39) needs to be examined.
If the filtered quantization noise vr [n] were not present in the rth channel of an
M channel Π∆Σ converter, the coefficient error vector would have the following form
n
X
−1
β̂[n] − β = Φ [n] w[i]vc [i] (4.41)
i=1
where
n
X
Φ[n] = w[n]wT [n] (4.42)
i=1
The expected value of the coefficient error vector E(β̂[n] − β) would be zero because
the quantization noise in the calibration channel vc [n] and the rth channel output wr [n]
are independent of each other. This implies that the RLS algorithm converges in the
mean for training samples n ≥ M to the optimum coefficients β,
E(β̂[n]) = β, n ≥ M. (4.43)
With the quantization noise taken into account, coefficients β̂ that best predict
the solution to (4.33) are sought. In this case the coefficient error vector becomes
n
X
−1
β̂[n] − β = Φ̃ [n] w̃[i](vc [i] − β T v[i]) (4.44)
i=1
n
X
Φ̃[n] = w̃[i]w̃T [i]
i=1
n
X
= (w[i] + v[i])(w[i] + v[i])T
i=1
Xn n
X n
X n
X
= w[i]wT [i] + w[i]v T [i] + v[i]wT [i] + v[i]v T [i]
i=1 i=1 i=1 i=1
∼
= Φ[n] (4.45)
n
X
β̂[n] − β = Φ−1 [n] (w[i] + v[i])(vc [i] − β T v[i]) (4.46)
i=1
n n
!
X X
= Φ−1 [n] w[i](vc [i] − β T v[i]) + v[i](vc [i] − β T v[i])
i=1 i=1
n n n
!
X X X
= Φ−1 [n] w[i](vc [i] − β T v[i]) + v[i]vc [i] − v[i]β T v[i]
i=1 i=1 i=1
The expected value of the coefficient error vector in (4.46) does not converge to a zero,
instead it converges to a bias that depends on the variance of the filtered quantization
noise σv2 , and inverse of the correlation matrix Φ−1 [n] of the input vector w[n]. The
n
!
X
E(β̂[n] − β) = −E Φ−1 [n] v[i]v[i]T β
i=1
n
!
X
= −E Φ−1 [n] σv2 Iβ
i=1
2 −1
= −nσv E(Φ [n])β (4.47)
where n is a training instant and β are the optimum coefficients that best predict the
solution to (4.33). The expected value of the first two terms in (4.46) are zero because
random variables in question are independent of each other.
In [82] it was shown that the expectation of the inverse correlation matrix Φ−1 [n]
is exactly
1
E(Φ−1 [n]) = R−1 , n>M +1 (4.48)
n−M −1
Equation (4.49) states that the RLS algorithm in the presence of the filtered quantization
noise converges in the mean for training samples n M +1 to the optimum coefficients
σ2
E(β̂[n]) = β − 2v β
σ
w 2
σ
= β 1 − 2v , nM +1 (4.50)
σw
For the RLS algorithm to converge to the optimum filter coefficients β, the biasing
constant σv2 /σw2 must be small, which implies that signal to noise ratio at the output of
the rth channel of an M channel Π∆Σ converter needs to be large. The biasing term
in (4.50) is independent of the number of training samples n, therefore the RLS algo-
rithm convergence in the mean can only improve by increasing the variance of training
samples w[n] or reducing quantization noise v[n]. Reducing quantization noise in a
given channel is not an option, because quantization noise is inherent to A/D converter
architectures and it is determined by the overall design of Π∆Σ ADC. Therefore, the
only way to improve the RLS algorithm convergence in the mean is by increasing the
variance of training samples σw2 .
The biasing term in (4.49) directly affects the performance measure Q[n] of the
RLS algorithm given in (4.38) by introducing an offset in the solution. Q[n] in the
presence of the filtered quantization noise is derived next. The derivation is based on the
analysis done in [82] and assumptions listed on page 88.
The coefficient error vector in the presence of quantization noise was given in
(4.46), and its correlation matrix is defined here as
K[n] = E (β̂[n] − β)(β̂[n] − β)T (4.51)
n X
n
!
X
−1
= E Φ [n] w̃[i](vc [i] − β T v[i])(vc [j] − β T v[j])T w̃T [j]Φ−1 [n]
i=1 j=1
n X
n
!
X
K[n] = E Φ−1 [n] w[i](vc [i] − β T v[i])(vc [j] − β T v[j])T wT [j]Φ−1 [n]
i=1 j=1
n X
n
!
X
+ E Φ−1 [n] v[i](vc [i] − β T v[i])(vc [j] − β T v[j])T v T [j]Φ−1 [n]
i=1 j=1
(4.52)
n X
X n
−1 T T T T −1
K[n] = E Φ [n] w[i]E (vc [i] − β v[i])(vc [j] − β v[j]) w [j]Φ [n]
i=1 j=1
Xn X n
−1 T T T T −1
+ E Φ [n] E v[i](vc [i] − β v[i])(vc [j] − β v[j]) v [j] Φ [n]
i=1 j=1
(4.53)
Each of the two expectation terms in (4.53) will be analyzed separately. Filtered
quantization noise v[n] and vc [n] that is encountered in each of the M channels of Π∆Σ
ADC and calibration channel, respectively, is modelled as an additive white noise pro-
cess with variance σv2 . The expectation of the filtered quantization noise of the first term
in (4.53) can be simplified to
n X
X n
E v[i](vc [i] − β T v[i])(vc [j] − β T v[j])T v T [j] =
i=1 j=1
n X n
3nσv4 ββ T , i=j
X
T T T
E v[i]β v[i]v [j]βv [j] = (4.55)
i=1 j=1 n(n − 1)σv4 ββ T , i =
6 j
For the case when i = j, the fourth order moment for a normal random variable is
used [85], otherwise random variables v[i] and v[j] are independent of each other. With
the above simplifications, (4.53) can be written in terms of (4.42), (4.54)and (4.55),
n
!
X
K[n] = 2σv2 E Φ−1 [n] w[i]wT [i]Φ−1 [n]
i=1
−1 −1
n2 σv4 + 2nσv4 ββ T
+E Φ [n]Φ [n]
2σv2 −1
R + E Φ−1 [n]Φ−1 [n] n2 σv4 + 2nσv4 ββ T
K[n] = (4.57)
n
1 −2
E(Φ−1 [n]Φ−1 [n]) = R . (4.60)
n2
The correlation matrix of a coefficient error vector given in (4.57) can be written in
terms of (4.60) as
2σv2 −1 1
R + 2 R−2 ββ T n2 σv4 + 2nσv4
K[n] =
n n
2σv2 −1 2σ 4
= R + σv4 R−2 ββ T + v R−2 ββ T . (4.61)
n n
To find the mean-squared error of the coefficient error vector Q[n] in the pres-
ence of the filtered quantization noise, a trace of the coefficient error vector correlation
matrix K[n] is taken,
For the case when input vectors w[n] for i = 1, 2, ..., n are independently and identi-
cally distributed random variables, the ensemble-averaged correlation matrix R = σw2 I.
Also, given a square matrix A and constant c the trace of cA is same as c · tr(A) and
σv2
E(β̂[n] − β) 0 − β
σw2
M σ2 2
M 2σv2 σv2
T v
Q[n] = E (β̂[n] − β) (β̂[n] − β) +
n σw2 n σw2 σw2
Table 4.2: Summary of the RLS algorithm convergence for n M +1 with and without
quantization noise present.
To verify the quality and the convergence rate of the RLS algorithm, an 8-
channel oversampling Π∆Σ converter with an additional channel for calibration was
modelled in MATLAB in which each channel contains 2nd order ∆Σ modulators with a
1-bit quantizer and decimation filter described by (4.15). The 1-bit quantizer was mod-
elled as an additive white noise source, and the oversampling ratio of D = 4 was used
in simulations.
As discussed in Section 4.4, known coefficients αr , where r = 1, 2, ..., 8, need to
be selected so the modulation sequence hc [n] for the calibration channel contains only
±1 terms. Coefficients αr should preferably have equal magnitude, so each channel in
the Π∆Σ architecture is given equal importance. For the case of an 8-channel Π∆Σ
converter, coefficients αr of equal magnitude do not exist. As identified by a computer
search algorithm, one of the valid solutions for coefficients αr that yielded only ±1
terms for a modulation sequence hc [n], was
The RLS algorithm performance analysis was based on the assumptions listed on page 88.
To effectively compare simulation results with theory, the Π∆Σ ADC input signal sam-
ples x[n] were taken from a normal distribution with zero mean and variance σx2 . For
the oversampling Π∆Σ ADC, the variance seen at the output of each channel of an
M -channel Π∆Σ converter before demodulation is given by
∞
X
σw2 = σx2 |g[n]|2 (4.64)
n=0
The RLS algorithm performance was analyzed in terms of the mean-square error
of the coefficient error vector Q[n] that is given by (4.38). Two sets of analysis were
conducted: the RLS algorithm solution to (4.31), where the algorithm’s input signal
w̃[n] = w[n], and the RLS algorithm solution to (4.33), where the algorithm’s input
signal is corrupted by noise, w̃[n] = w[n] + v[n]. The behavior of the measure Q[n] for
the RLS algorithm performance when w̃[n] = w[n] is given by (4.40) and is repeated
here in a decibel form
σw2
M
Q[n]dB = 10 log10 − 10 log10 , nM +1 (4.66)
n σv2
σw2
where is known as a signal-to-noise ratio. The metric Q[n] for the RLS algorithm
σv2
performance when w̃[n] = w[n] + v[n] is given by (4.63). Except for the factor of 2
that modifies the amount of quantization noise seen in the RLS algorithm, the algorithm
σ4
follows the convergence rate of (4.66) until the offset term 4v starts to dominate.
σw
Figure 4.13 shows the RLS algorithm performance in terms of Q[n]dB for a
simulated 8-channel Π∆Σ converter plus an additional channel for calibration and a
signal-to-noise ratio of 30 dB and 40 dB. The quantization noise power σv2 was found
according to (4.30) and a gain error mismatch of 1% was simulated and introduced to
all eight channels. The variance at the converter input σx2 was found based on the given
signal-to-noise ratio σw2 /σv2 and (4.65). Coefficients β̂[n] that contain gain correction
terms and are used in determining Q[n], are found using the RLS algorithm described
in Table 4.1. The results shown in Figure 4.13 are averaged over 10 simulation runs.
−45
−50
Q[n] in dB
−55
−60
−65
−70
−75
−80
2 3 4 5 6
10 10 10 10 10
Training samples
−40
Expected performance
−45 RLS algorithm convergence
RLS algorithm convergence with noise
−50
−55
−60
Q[n] in dB
−65
−70
−75
−80
−85
−90
2 3 4 5 6
10 10 10 10 10
Training samples
Figure 4.13: The RLS algorithm performance and convergence results for an 8-channel
Π∆Σ converter with the oversampling rate D = 4.
σv2
E(β̂[n]) = β − β, n M + 1. (4.67)
σw2
Ideally, β̂[n] should converge in the mean to true coefficients β. Figures 4.15 and 4.16
show the convergence of two coefficients (β̂2 [n]) and β̂6 [n], for a simulated 8-channel
Π∆Σ ADC with signal-to-noise ratio of 30 dB and gain mismatch errors of 1% intro-
duced in all eight channels. As before, the estimated coefficients β̂[n] are found using
−45
−50
Q[n] in dB
−55
−60
−65
−70
−75
−80
2 3 4 5 6
10 10 10 10 10
Training samples
−40
Expected performance
−45 RLS algorithm convergence
RLS algorithm convergence with noise
−50
−55
−60
Q[n] in dB
−65
−70
−75
−80
−85
−90
2 3 4 5 6
10 10 10 10 10
Training samples
Figure 4.14: The RLS algorithm performance and convergence results for an 8-channel
set up where ∆Σ modulator and decimation filter were taken out of a channel path.
0.258
Coefficient β̂2 [n]
0.256
0.254
0.252
0.25
2 3 4 5 6
10 10 10 10 10
(b)
0.255
Coefficient β̂2 [n]
0.25
0.245
0.24
2 3 4 5 6
10 10 10 10 10
Training samples
Figure 4.15: Convergence of the coefficient β̂2 [n]: (a) ideal case, quantization noise
at the output of each channel is excluded and (b) RLS algorithm performance in the
presence of the quantization noise. Solid lines designate the optimum coefficients β,
and the dashed lines designate the optimum coefficients β with the offset term included.
−0.75
−0.752
−0.754
−0.756
2 3 4 5 6
10 10 10 10 10
(b)
−0.735
Coefficient β̂6 [n]
−0.74
−0.745
−0.75
−0.755
2 3 4 5 6
10 10 10 10 10
Training samples
Figure 4.16: Convergence of the coefficient β̂6 [n]: (a) ideal case, quantization noise
at the output of each channel is excluded and (b) RLS algorithm performance in the
presence of the quantization noise. Solid lines designate the optimum coefficients β,
and the dashed lines designate the optimum coefficients β with the offset term included.
Channel gain errors and their locations in the frequency spectrum of Π∆Σ ADCs
were discussed in Section 4.3. The unwanted frequency tones degrade the overall perfor-
mance (i.e. dynamic range) of Π∆Σ converters. To quantitatively relate the accuracy of
the developed calibration algorithm to improvements in the dynamic range of the Π∆Σ
converter requires knowledge of the peak frequency tone levels that can be generated by
a given gain error.
If a full scale sinusoidal input signal is applied to an M channel time-interleaved
converter, the mean and variance of error tones due to channel gain mismatches are
given by [70]
r
σa π
µg =
2 M
σa2
σg2 = (1 − π/4) (4.68)
M
where σa2 is the variance of a total gain in a channel ar for r = 1, 2, ..., M with M being
ar = 1 + ε r , (4.69)
where εr is a channel gain error with normal distribution and variance σε2 . Therefore, the
total gain ar will also have a normal distribution with variance σa2 = σε2 . Even though
in [70] the analysis was based on a time-interleaving converter architecture, the same
result applies to Hadamard modulated converter architecture [20]. Therefore, for an 8-
channel Π∆Σ converter with a channel gain mismatch error of 1% (i.e. σa = 0.01),
the peak power of generated error tones is expected to be at 20 log10 (µg ) = −50 dB.
Figure 4.17 shows a simulated output spectrum of an 8-channel Π∆Σ converter with
channel gain mismatch errors. Channel gain errors with normal distribution and standard
deviation of σa = 0.01 were simulated. The result was obtained by averaging 16384-
point FFT’s of 100 independent simulation runs. Also plotted is the theoretical mean of
generated gain error tones. For this example, the mean is expected to be 50 dB below
the input signal.
The proposed calibration scheme uses the RLS algorithm described in Table 4.1
to find a set of coefficients β̂r for r = 1, 2, ..., M , that contain the knowledge of gain er-
rors in M parallel channels. The RLS performance analysis is based on the assumptions
listed in page 88. In Section 4.4, the optimum coefficients βr were defined as
α r ac
βr = (4.70)
ar
where αr are known coefficient values selected so the modulation sequence hc [n] con-
tains only ±1 terms. Terms labelled ac and ar are total gains (including gain error terms)
in the calibration channel and the rth channel of an M -channel Π∆Σ converter, respec-
tively. To simplify the analysis, the calibration channel is assumed to have no gain error
(i.e ac = 1). This assumption does not affect the overall result. The goal here is to
−20
−40
Magnitude, dBFS
−60
−80
−100
−120
−140
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Normalized Frequency
Figure 4.17: Averaged output spectrum for an 8-channel Π∆Σ converter with a 1%
channel gain mismatch error and oversampling ratio D = 4. The dashed line corre-
sponds to theoretical mean of spectral peaks caused by channel gain mismatches.
find channel mismatches, and if there is a gain error present in the calibration channel,
than all the channels will be calibrated with respect to gain ac of the calibration channel.
Setting ac = 1 and writing (4.70) in terms of the RLS algorithm coefficient estimates
β̂r [n] leads to the following expression
αr
β̂r [n] = + β̂ [n] (4.71)
ar
where β̂ [n] is the error describing deviation of β̂r [n] from the optimum solution βr at
training instant n.
Equation (4.71) shows that the estimated coefficients β̂r [n] are inversely propor-
tional to the total gain ar in a given channel. Dividing β̂r [n] by the known value of αr
and scaling the output of the rth channel by this new expression will correct for channel
αr 1
ȧr [n] = ar + β̂ [n]
ar αr
ar β̂ [n]
= 1+
αr
(1 + εr )β̂ [n]
= 1+
αr
β̂ [n]
∼
= 1+ (4.72)
αr
The error term β̂ [n] depends on the accuracy of estimation of β̂r [n], which in turn
depends on the RLS algorithm performance. The RLS performance was analyzed in
terms of a mean-square error of coefficient error vector Q[n] that is given in (4.38). Q[n]
can be also interpreted as a sum of variances of β̂ [n] that is contained in M channels.
Therefore, the variance of the error describing the deviation of β̂r [n] from the optimum
solution βr at the training instant n is
Q[n]
σ2β̂ = , (4.73)
M
where M is the number of channels in parallel configuration. Based on (4.73), the new
gain ȧr [n] in (4.72) has a variance
Q[n]
σȧ2 = . (4.74)
M αr2
Equation (4.74) can be written in terms of the initial gain error variance σa2 ,
Q[0] Q[n]
σȧ2 =
M αr2 Q[0]
Q[n]
= σa2 (4.75)
Q[0]
where Q[0]/M is the sum of variances of β̂ [n] that is contained in M channels at train-
αr αr αr αr
β̂ [0] = − = −
1 ar 1 1 + εr
∼
= α r εr . (4.76)
Using (4.73) and knowledge that gain errors εr have a normal distribution with variance
σa2 , Q[0] can be expressed in terms of the variance of initial gain error σa2 ,
Equation (4.75) implies that the magnitude of frequency tones due to gain mis-
match errors in a Π∆Σ converter will be changed by (Q[n]dB − Q[0]dB ) decibels. The
peak power of error tones after calibration can be found by solving (4.68) using the new
gain ȧr [n],
r
σȧ π
20 log10 (µg ) = 20 log10 (4.78)
2 M
σw2 ∼
= (0.0086)σx2 (4.79)
−20
−40
Magnitude, dBFS
Fs/4,1
−60
Fs/4,−1 Fs/2,1
Fs/2,−1
−80
Fs/8,1
3Fs/8,−1 3Fs/8,1
−100 Fs/8,−1
−120
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Normilized Frequency
(a)
−20
−40
Magnitude, dBFS
Fs/4,1
−60 Fs/8,1
Fs/8,−1
3Fs/8,−1 Fs/2,−1
Fs/2,1 3Fs/8,1
−80 Fs/4,−1
3Fs/16,−1 5Fs/16,1
−100 5Fs/16,−1 7Fs/16,1 Fs/16,−1 3Fs/16,1
7Fs/16,−1
Fs/16,1
−120
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Normilized Frequency
(b)
Figure 4.18: Output spectrum for uncalibrated (a) 8-channel and (b) 16-channel Π∆Σ
converters with gain mismatch error of 1% and oversampling ratio D = 4. The dashed
lines indicate the theoretical means of spectral peaks caused by channel gain mismatches
Up until now, the performance of the gain correction algorithm was based on the
input signal samples x[n] having normal distribution with variance σx2 . This ensured that
each channel in an M -channel Π∆Σ converter was processing part of the input signal.
The RLS algorithm cannot detect a gain error for an inactive channel(s), therefore the
input signal must excite all of the channels in the Π∆Σ architecture. If the input signal
constraint is met, the proposed calibration will simultaneously correct for all the chan-
nel gain errors. In software radio (SWR) receiver architectures an ADC is required to
capture an entire cellular band that may contain multiple wireless standards and signals
from different wireless users. This multi-tone input signal can be enough to excite all M
channels of the Π∆Σ architecture, leading to successful gain calibration. An example of
a multi-tone input signal that leads to successful channel gain error correction is given
next.
A 16-channel Π∆Σ converter with an additional channel for calibration was
modelled in MATLAB. Each channel contains a 2nd order ∆Σ modulator with the over-
sampling ratio D = 4. Calibration is demonstrated for a 5 tone input signal. This input
signal shows the wide bandwidth capabilities of Π∆Σ converters and also excites all of
the 16 channels. To have a calibration channel as a linear combination of other channels,
terms αr for r = 1, 2, ..., 16 were set to ±0.25 as identified by computer search. Gain
error mismatches of 1% were simulated and introduced to all channels (including the
calibration channel). Gain correction terms were calculated using the RLS algorithm
described in Table 4.1. Figure 4.21 shows the simulation results for an uncalibrated and
−20
−40
Magnitude, dBFS
−60
Fs/4,−1
−80 Fs/4,1
Fs/2,−1
Fs/2,1
Fs/8,1
3Fs/8,−1 3Fs/8,1
−100 Fs/8,−1
−120
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Normilized frequency
(a)
−20
−40
Magnitude, dBFS
−60
−80
Fs/4,−1 Fs/4,1
3Fs/8,−1 Fs/8,1
−100 Fs/8,−1 3Fs/8,1
Fs/2,−1
Fs/2,1
−120
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Normilized frequency
(b)
Figure 4.19: Performance of an 8-channel Π∆Σ converter after calibration. Gain cor-
rection terms were calculated using an RLS algorithm and input signal with zero mean
and variance σx2 . The RLS algorithm was trained to obtain the dynamic range improve-
ment of: (a) 20 dB and (b) 40 dB.The dashed lines correspond to theoretical means of
spectral peaks that remained after calibration.
−20
−40
Magnitude, dBFS
−60
Fs/2,−1
Fs/2,1 Fs/8,1
−80
Fs/8,−1 Fs/4,1
3Fs/8,−1 7Fs/16,1
3Fs/8,1
Fs/4,−1
−100 5Fs/16,−17Fs/16,−1 Fs/16,−1
Fs/16,1
3Fs/16,−1
5Fs/16,1 3Fs/16,1
−120
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Normilized frequency
(a)
−20
−40
Magnitude, dBFS
−60
−80
Fs/2,−1
Fs/2,1
3Fs/16,−1Fs/8,−1 5Fs/16,1
Fs/4,1 Fs/8,1
−100 5Fs/16,−1
Fs/4,−1 7Fs/16,1 3Fs/8,1
Fs/16,−1 3Fs/16,1
7Fs/16,−1
3Fs/8,−1 Fs/16,1
−120
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Normilized frequency
(b)
Figure 4.20: Performance of a 16-channel Π∆Σ converter after calibration. Gain cor-
rection terms were calculated using an RLS algorithm and input signal with zero mean
and variance σx2 . The RLS algorithm was trained to obtain the dynamic range improve-
ment of: (a) 20 dB and (b) 40 dB. The dashed lines correspond to theoretical means of
spectral peaks that remained after calibration.
M M
2σv2 X 1 4
X 1
Q[n] = 2
+ σv (4.80)
n r=1 σwr σ4
r=1 wr
2
Term σwr is the signal power at the output of the rth channel of Π∆Σ converter be-
fore demodulation. Based on (4.80), the convergence of the RLS algorithm will be
limited by the channel with the minimum signal power. The minimum signal to noise
ratio σw2 /σv2 for a 5 tone input signal was measured to be 37 dB. The RLS algorithm
will stop converging when Q[n]dB reaches -74 dB or, because the signal! power in each
M
X 1
channel is different, a more accurate result is 20 log10 σv2 2
= −75 dB. Fig-
r=1
σ wr
ure 4.22 shows the RLS algorithm convergence results for the multi-tone input signal
with frequency spectrum shown in Figure 4.21. As expected, the RLS algorithm stops
converging once Q[n]dB reaches -75 dB. Also, the RLS algorithm takes fewer iterations
to saturate because some channels have larger signal to noise ratio σw2 /σv2 and therefore
converge to the correct solution faster.
−20
−40
Magnitude, dBFS
−60
−80
−100
−120
−140
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Normilized Frequency
(a)
−20
−40
Magnitude, dBFS
−60
−80
−100
−120
−140
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Normilized Frequency
(b)
Figure 4.21: Simulation results for a 5-tone input: (a) Uncalibrated 16-channel Π∆Σ
converter with 1% gain mismatch error and oversampling ratio D = 4 and (b) Perfor-
mance of a 16-channel Π∆Σ converter after calibration. Coefficients αr are identical.
Frequencies are normalized by the decimated sample rate.
−40
−45
−50
Q[n] in dB
−55
−60
−65
−70
−75
−80
0 1 2 3 4 5 6
10 10 10 10 10 10 10
Training samples
Figure 4.22: The simulated RLS algorithm performance results for a multi-tone input
signal with frequency spectrum shown in Figure 4.21.
s 1 [n] h 1 [n]
∆Σ G(z) D c2
s 2 [n] h 2 [n]
∆Σ G(z) D c3
s 3[n] h 3 [n]
∆Σ G(z) D c M−1
c
s M [n] h M [n]
∆Σ G(z) D RLS
c
Algorithm
s c [n]
Figure 5.1: Oversampling Π∆Σ ADC with gain calibration. Also shown are the parts
of the architecture that were implemented in hardware and software.
each integrator is transferred to the capacitor labelled 2C. This is the “subtraction and
integration phase”. Because sampling and integration occur at two different clock phases
(i.e. φ1 and φ2 ), each action should be complete within half the period of the main clock.
If the main clock is running at 50 MHz, each component in ∆Σ modulator circuit must
settle to its final value in 10 ns.
During φ2 , the Hadamard modulation sequence is captured and during φ1 based
on the captured sequence switches are configured to pass the differential signal or cross
the inputs to pass the inverse of the differential signal to the stage 1 input. The logic
circuit that performs Hadamard modulation and sizing of all the switches used in Figure
5.2 can be found in the Appendix A.
The fabricated chip operates from a single 5 V supply. To maximize the output
swing, the common-mode voltage was set to 2.5 V. Each ∆Σ modulator accepts a ±1 V
fully differential input signal that is centered around the common-mode voltage. The
two reference voltages VREF + and VREF − that are required for the ∆Σ modulator op-
eration are set to 3 V and 2 V, respectively. This corresponds to a 1-bit D/A output of
±1 V. The 1-bit D/A output is controlled by a 1-bit quantizer at the output of the second
integrator. In Figure 5.2, the nodes labelled V cmi set the common mode input voltage
of the differential OTA input. In this design, V cmi was set to 1.5 V. All the required
gain-boosting OTA with common-mode feedback that was adopted for the final design.
where v + and v − are voltages seen at the positive and negative input terminals of the
OTA, respectively. Based on the timing diagram of clocks φ1 and φ2 in Figure 5.6, the
total charge stored on the integrator in Figure 5.5 at the end of φ1 is given by
1+A
q[n − 1] = vin [n − 1]Cs + vout [n − 1]Ci (5.2)
A
1 1 Cs 1 1+A
q[n − ] = vout [n − ] + vout [n − ]Ci
2 2 A 2 A
Cs 1+A
= vout [n] + vout [n]Ci (5.3)
A A
The second line of (5.3) holds since during φ1 , the voltage across Ci is constant, result-
ing in vout [n − 21 ] = vout [n]. In order to maintain charge conservation in the circuit,
q[n − 1] = q[n − 21 ]. By equating (5.2) and (5.3), the relationship between the integrator
input vin and output vout can be found.
Cs 1+A 1+A
vin [n − 1]Cs = vout [n] + Ci − vout [n]Ci (5.4)
A A A
The z-domain transfer function of the SC integrator with a finite DC gain of A is given
by
σs2
SN RdB = 10 log10
σe2
π4
= n · 6.02 + 1.76 + 50 log10 (D) − 10 log10 (5.7)
5
0.5
2
σtn = = 20 · 10−9 V2 (5.8)
107.4
By using (5.6), D = 2 and the result of (5.8), the lower limit on the required sampling
capacitor C was found to be 414-fF. The sampling capacitor C in Figure 5.2 was chosen
to be 500-fF, which in turn requires an integrating capacitor 2C of 1-pF.
I
SR = (5.9)
Ce
where I is the maximum bias current available at the OTA output node for charg-
ing/discharging of the external capacitance Ce. As mentioned in Section 5.1, sampling
and integration occur during two different clock phases, therefore each action needs to
be completed within half the period of the main clock. The design goal is to minimize
the slew rate, and therefore minimize the current required for the OTA to complete the
integration and ensure the output settles to a final value (within some allowable error
range) by the end of φ2 .
For the given converter design, a full-scale analog input range is 2 V (i.e. ±1 V
differential). Based on the ∆Σ modulator topology used and results found in [79], to
support input signals that are 1 dB below full-scale, the output of both integrators should
be at least 50 % larger than the full-scale analog input range. This means that for a full-
scale analog input range of 2 V, the output swing of the OTA should be 3 V. If the main
clock is running at 50 MHz, integration needs to complete within 10 ns. Therefore, to
avoid distortion from slewing, the minimum OTA slew rate is 300 V/µs.
In order to find the OTA current that meets the minimum slew rate requirements,
the capacitance Ce seen at the output node of the OTA to ground during φ2 must be
estimated. Figure 5.7 shows the SC integrator configuration when the clock signal φ2
is high. As mentioned before, the OTA will be slewing for most of φ2 . During the
slewing period, the operation of the OTA is nonlinear and therefore the feedback is not
effective [88,90]. The total capacitance Ce seen at the output node of the OTA to ground
during φ2 is given by
CiCs
Ce = Cl + (5.10)
Ci + Cs
In order to achieve high DC gain, the telescopic OTA architecture with gain
boosting was implemented [91–94]. Figure 5.8 shows a fully differential implementa-
tion of a telescopic OTA with gain boosting and common-mode feedback (CMFB). Also
shown are device sizings used in the final design. Circuits that generate biasing voltages
V b1 and V b2 can be found in Appendix A. The gain-boosting techniques increase the
output resistance of the telescopic OTA without the need for additional cascode stages.
Negative feedback is used to maintain a relatively constant output current by reducing
the drain voltage variations for M 1, M 2, M 7 and M 8. Minimizing current variations
(i.e. current remains more constant) translates into an increase in the output resistance
of the OTA.
Because the circuit implementation is fully differential (i.e. left and right side
are identical in implementation), it is sufficient to analyze only one side. The overall
voltage gain for a gain-boosting OTA in Figure 5.8 is given by [90]
Av ∼
= gm7 · (ro7 ro5 gm5 (1 + Agbn )) k (ro1 ro3 gm3 (1 + Agbp )) (5.11)
where gm and ro terms are small signal device transconductance and output resistance,
Figure 5.8: Fully differential telescopic OTA with gain boosting and common-mode
feedback (CMFB).
Figure 5.9: Differential gain boosting amplifiers used in the design of the OTA in Figure
5.8.
Figure 5.10: Common mode feedback circuit used in the design of a gain boosting OTA.
10
70 10
60
50
Unity gain frequency (Hz)
Phase Margin (degrees)
40
9
10
30
20
10
8
0 10
0.5 1 1.5 2 2.5 3 3.5 4
C (pF)
L
Figure 5.11: Open loop frequency response (phase margin and unity gain frequency) for
different load capacitances CL . Star symbol corresponds to unity gain frequency axis
and asterisk symbol correspond to phase margin axes.
gain frequency. For the given OTA design topology, the overall transfer function will
have a dominant pole due to a capacitive load CL located at the output node of the OTA.
However, the given topology also has a pole-zero doublet present in its transfer function
which is a side-effect of gain-boosting [92,95]. The existence of a pole-zero doublet can
have a negative affect on the phase margin and/or the settling time of the OTA. Circuit
configurations to run the open loop frequency response and slew rate tests were adapted
from [96] and are shown in Figures 5.12 and 5.13, respectively.
Figure 5.11 shows the simulated open loop frequency response behavior of the
OTA as a function of load capacitances CL . The OTA was simulated with the common-
mode input voltage V cmi set to 1.5 V and the common-mode output voltage VCM set
to 2.5 V. Figure 5.11 shows reduced phase margin due to a pole-zero doublet and low
values of CL . As CL increases, separation between the dominant pole and pole-zero
doublet increases causing a more stable frequency response with a reduced unity gain
frequency. A summary of a fully differential gain-boosting OTA with CMFB is given in
Table 5.1.
The remaining ∆Σ modulator components are the 1-bit DAC, 1-bit comparator
and the two-phase, non-overlapping clock signal generator. Full schematics and device
sizes for all of these components are provided in Appendix A.
The comparator design was motivated by a design reported in [97] and is shown
in Figure 5.14. It was sized to meet the current design requirements and its performance
at 50 MHz can be found in [86]. From Figure 5.14, transistors M 1-M 6 are the input
stage of the comparator and are always active. When Latch is high, transistors M 11
and M 12 pull the gates of M 7-M 10 low making them inactive and M 12 and M 14
make sure that the output nodes are pulled high. Therefore, during the comparator’s off-
time, the output nodes are always pulled high, which makes sure that a decision from a
previous comparison is always erased. When Latch is low, M 15 is active which in turn
deactivates M 13, M 14 and M 16. During this time the comparator makes the decision
and depending on the applied input, the positive feedback formed by M 9 and M 10 will
pull one of the output nodes low.
Both the comparator decision and its compliment are provided at the output
nodes. However, the modulator design does not directly utilize the compliment. In-
stead, the compliment is obtained by directly inverting the comparator decision. The
inverter is part of the 1-bit D/A converter design logic. This was done to avoid indeci-
sive comparator outputs [86].
The 1-bit D/A converter design and device sizes are provided in Appendix A.
The D/A converter uses two minimum sized inverters and four NMOS switches that
are controlled by the comparator output. Depending on the comparator decision, the
1-bit D/A converter will produce ±1 V differential output. This is based on VREF +
and VREF − being 3 V and 2 V, respectively. The two-phase, non-overlapping clock
generator was based on the design in [47, 86], and it was modified to meet current de-
sign requirements. The design and device sizes for the clock generator are provided in
Appendix A.
generated by an HP8642 was passed through a splitter with one signal routed to generate
the required clock signal for the chip and the other signal routed to generate the clock for
the FPGA board. Table 5.2 lists the equipment used to test the Π∆Σ ADC and collect
data.
Once the high-data rate digital outputs from the two chips are collected, digital
filtering, decimation, demodulation, channel recombination and calibration were per-
formed in MATLAB. The following sections discuss the performance of the ∆Σ test
chip with and without calibration.
The ADC test board was configured to run nine ∆Σ modulators in a parallel
configuration. This creates an 8-channel Π∆Σ converter plus an additional channel
used for calibration of channel gain mismatches.
Figure 5.16 shows the real-time data output spectrum for the uncalibrated 8-
channel Π∆Σ converter for two different input frequencies (350 kHz and 430 kHz). In
both cases, the amplitude of the input signal was set at -6 dB of full scale. Using an
Agilent logic analyzer, a sequence of 219 binary output samples per ∆Σ modulator was
collected. The collected data was filtered, downsampled and demodulated in software
to obtain 8192 samples. The output spectrum calculated from these samples is shown
in Figure 5.16. The output spectrum shows spurs due to channel gain mismatches and
harmonic distortion. The harmonic distortion terms are caused by the signal genera-
tor. Harmonics below 2.5 MHz are passed through the lowpass filter to the ADC input.
These additional tones alias back into the signal band (FS /2), and are labelled by a
single integer indicating the harmonic number. Distortion caused by channel gain mis-
FS
matches is expected to appear at frequencies of M
± Fin , as described in Section 4.3.
These terms are also labelled in the figure. The goal of gain calibration is to reduce these
undesired terms. The dashed line corresponds to a theoretical mean of spectral peaks
caused by channel gain mismatches given by (4.68). By looking at the standard devia-
tion of the estimated coefficients β̂[n] (after calibration), the channel gain mismatches
for the fabricated chip and given test setup were found to be in the order of 0.5%.
The quantization noise power at the output of each channel σv2 before demodula-
tion is determined by removing the signal component and all the distortion terms from
the output spectrum. The quantization noise power for the 8-channel Π∆Σ converter
experimental setup was found to be 8 · σv2 ∼
= 8 · 10−6 V2 . Quantization noise is expected
to be equally distributed in all 8 channels and therefore the noise seen at the output of
each channel before demodulation σv2 is 10−6 V2 .
The ADC test board was configured to run seventeen ∆Σ modulators in parallel.
This enables testing of a 16-channel Π∆Σ converter. The extra channel is used for
calibration of channel gain mismatches.
Figure 5.18 shows the real-time data output spectrum for the uncalibrated 16-
channel Π∆Σ converter. As for the 8-channel case, the two single tone test frequencies
−20
−40
Magnitude, dBFS
Fs/2,−1
Fs/2,1
2
−60
3 5
4 6
−80 3Fs/8,−2 Fs/8,2
Fs/4,−1 Fs/4,2 Fs/4,−2
3Fs/8,1 Fs/4,1
7 Fs/8,−2
3Fs/8,2 10
3Fs/8,−1
Fs/2,−2
Fs/2,2 Fs/8,−1 Fs/8,1 9
−100 8
−120
0 0.1 0.2 0.3 0.4 0.5 0.6
Frequency (MHz)
(a)
0
1
−20
−40
Magnitude, dBFS
4
Fs/2,−1
Fs/2,1 3Fs/8,−2 Fs/8,−2
Fs/4,2
6
3Fs/8,2 5
−80
10
Fs/4,−2
Fs/8,2
Fs/2,−2
Fs/2,2
3
3Fs/8,−1 7
Fs/8,−1 3Fs/8,1 Fs/8,1
9
−100
8
−120
0 0.1 0.2 0.3 0.4 0.5 0.6
Frequency (MHz)
(b)
−20
−40
Magnitude, dBFS
2
−60
3 5
Fs/2,−1
Fs/2,1
4 6
−80 Fs/4,−1 3Fs/8,−2 Fs/8,2
Fs/4,−2
Fs/4,2 3Fs/8,1 Fs/8,−2
7
3Fs/8,2 10
3Fs/8,−1 Fs/8,−1
Fs/2,−2
Fs/2,2 Fs/8,1 Fs/4,1
9
−100 8
−120
0 0.1 0.2 0.3 0.4 0.5 0.6
Frequency (MHz)
(a)
0
1
−20
−40
Magnitude, dBFS
−60 2
4 Fs/4,1
3Fs/8,−2 Fs/8,−2
Fs/4,2
6
3Fs/8,2 5
−80 Fs/4,−1 10
Fs/4,−2
Fs/8,2
Fs/2,1
Fs/2,−1
Fs/2,−2
Fs/2,2
3
3Fs/8,−1 7
Fs/8,−1 3Fs/8,1 Fs/8,1
9
−100
8
−120
0 0.1 0.2 0.3 0.4 0.5 0.6
Frequency (MHz)
(b)
−20
−40
Magnitude, dBFS
Fs/2,−1
Fs/2,1 2
−60 3
3Fs/8,1 5
Fs/4,1
6 Fs/8,1
−80 Fs/4,−1 3Fs/8,−1
4
7 Fs/8,−1
3Fs/16,−1 Fs/16,1 3Fs/16,1
7Fs/16,−1Fs/16,−1 7Fs/16,1 5Fs/16,1
−100 10 8
5Fs/16,−1 9
−120
0 0.1 0.2 0.3 0.4 0.5 0.6
Frequency (MHz)
(a)
0
1
−20
−40
Magnitude, dBFS
−60 2
Fs/2,−1
Fs/2,1 3Fs/8,1
4 Fs/4,1
Fs/4,−1 5 Fs/8,1
−80 3
3Fs/8,−1
Fs/8,−1 3Fs/16,1
Fs/16,−1 5Fs/16,1 Fs/16,1
7
6 7Fs/16,−1
9
3Fs/16,−1 10
5Fs/16,−1
−100 7Fs/16,1
8
−120
0 0.1 0.2 0.3 0.4 0.5 0.6
Frequency (MHz)
(b)
Figure 5.18: Output spectrum for uncalibrated 16-channel Π∆Σ converter with (a)
Fin = 350kHz and (b) Fin = 430 kHz. The dashed line corresponds to a theoretical
mean of spectral peaks caused by channel gain mismatches.
−20
−40
Magnitude, dBFS
2
−60 3 5
4 6 3Fs/8,1
−80
Fs/2,−1
Fs/2,1 Fs/4,1
7
Fs/4,−1 3Fs/16,−1 Fs/8,−1 Fs/16,1 3Fs/16,1
3Fs/8,−1
7Fs/16,−1Fs/16,−1 7Fs/16,1 Fs/8,1
5Fs/16,1
−100 10 8
5Fs/16,−1 9
−120
0 0.1 0.2 0.3 0.4 0.5 0.6
Frequency (MHz)
(a)
0
1
−20
−40
Magnitude, dBFS
−60 2
4
53Fs/8,1
−80 3
Fs/2,−1
Fs/2,1
3Fs/8,−1 Fs/4,−1 Fs/8,−1 Fs/16,−1 5Fs/16,1 Fs/16,1 3Fs/16,1
7 Fs/8,1
7Fs/16,−1
9 Fs/4,110
6 3Fs/16,−1
5Fs/16,−1
−100 7Fs/16,1
8
−120
0 0.1 0.2 0.3 0.4 0.5 0.6
Frequency (MHz)
(b)
−20
−40
Magnitude, dBFS
2
−60 3 5
4 Fs/2,−1
Fs/2,1 6
−80
Fs/4,1
7 3Fs/8,1
3Fs/16,−1Fs/8,−1 Fs/16,1 3Fs/16,1
Fs/4,−1 7Fs/16,−1Fs/16,−1 7Fs/16,1 Fs/8,1
5Fs/16,1
−100 3Fs/8,−1 10 8
5Fs/16,−1 9
−120
0 0.1 0.2 0.3 0.4 0.5 0.6
Frequency (MHz)
(a)
0
1
−20
−40
Magnitude, dBFS
−60 2
4
5
−80 3
Fs/2,−1 Fs/8,−1 3Fs/8,1
3Fs/8,−1 Fs/4,−1 Fs/2,1 3Fs/16,1
Fs/16,−1 5Fs/16,1 Fs/16,1
7 Fs/8,1
7Fs/16,−1
9
6 3Fs/16,−1 10
5Fs/16,−1 Fs/4,1
−100 7Fs/16,1
8
−120
0 0.1 0.2 0.3 0.4 0.5 0.6
Frequency (MHz)
(b)
Figure 5.20: Performance of a 16-channel Π∆Σ converter after calibration. The RLS
algorithm was trained to obtain the dynamic range improvement of 33 dB. The output
spectrums for: (a) Fin = 350 kHz and (b) Fin = 430 kHz are plotted. The dashed line
indicates the expected mean of spectral peaks after calibration.
FS
fε,∆t = i ± FIN , i = 1, 2, 3...M/2. (5.12)
M
In (5.12), FS is the Nyquist-rate clock, FIN is the input frequency and M is the number
of channels in a parallel configuration.
Even though the frequency locations of the clock skew and gain error spectrum
peaks are the same, the distortion terms in Figure 5.20 that are left after the gain calibra-
tion was performed are most likely due to clock skew error. The Π∆Σ ADC test setup
utilizes two separate chips to form a 16-channel Π∆Σ converter. Due to this configura-
tion there may exist a clock skew between the two chips that is more dominant than a
clock skew between the channels within a single chip. To confirm that a clock skew be-
tween the two chips is enough to cause distortion tones seen in Figure 5.20, a 16-channel
Π∆Σ converter with an additional channel for calibration was modelled in MATLAB.
Each channel contains 2nd order ∆Σ modulator, the decimation filter described by (4.15)
and a quantizer that mimics the quantization noise seen in the experiment (σv2 = 6 · 10−9
V2 ). The quantizer was modelled as an additive white noise source. The oversampling
ratio D and the Nyquist-rate frequency FS were set to 4 and 1.25 MHz, respectively.
This was the same as in the experiment. A fixed clock skew error of 0.2% at over-
1
sampled clock period (Tclk = DFS
) was introduced in eight channels. This mimics the
constant clock delay that may be seen between the two chips on the test board. Also,
a gain error mismatches of 0.5% were introduced in all 16 channels including the cali-
bration channel. Figure 5.21 shows the simulated spectrum for uncalibrated 16-channel
Π∆Σ converter with gain and clock skew errors at 350 kHz and 430 kHz. Because the
spectrum peaks due to gain errors and clock skew errors occur at the same location it
is hard to distinguish between the two. The dashed line indicates the expected mean of
spectral peaks due to 0.5% channel gain mismatches. As was the case in the experi-
−20
−40
Magnitude, dBFS
−60
Fs/2,−1
Fs/2,1
Fs/8,−1
Fs/4,−1 3Fs/8,1 Fs/8,1
−80 3Fs/8,−1
Fs/4,1
3Fs/16,1
Fs/16,1
5Fs/16,−1
3Fs/16,−1 7Fs/16,−1Fs/16,−1 7Fs/16,1
−100
5Fs/16,1
−120
0 0.1 0.2 0.3 0.4 0.5 0.6
Frequency (MHz)
(a)
−20
−40
Magnitude, dBFS
−60
Fs/4,−1 Fs/2,1 Fs/4,1
Fs/2,−1 Fs/8,−1
3Fs/8,1 Fs/8,1
−80 3Fs/8,−1
Fs/16,1
−120
0 0.1 0.2 0.3 0.4 0.5 0.6
Frequency (MHz)
(b)
Figure 5.21: Simulated output spectrum for uncalibrated 16-channel Π∆Σ converter
with (a) Fin = 350kHz and (b) Fin = 430 kHz. The clock skew of 0.2% of a high rate
sampling period is simulated between the two chips. The dashed line corresponds to a
theoretical mean of spectral peaks caused by channel gain mismatches.
−20
−40
Magnitude, dBFS
−60
−80 Fs/2,−1
Fs/2,1 3Fs/8,1 Fs/8,1
3Fs/8,−1 Fs/4,1
Fs/4,−1 Fs/8,−1 5Fs/16,1 3Fs/16,1
7Fs/16,−1
5Fs/16,−13Fs/16,−1 Fs/16,−1 7Fs/16,1 Fs/16,1
−100
−120
0 0.1 0.2 0.3 0.4 0.5 0.6
Frequency (MHz)
(a)
−20
−40
Magnitude, dBFS
−60
Fs/4,−1 Fs/4,1
−80 Fs/2,−1
Fs/2,1 3Fs/8,1 Fs/8,1
Fs/16,−1 Fs/16,1
3Fs/8,−1 Fs/8,−1 5Fs/16,1
5Fs/16,−1 3Fs/16,−17Fs/16,1
−100 7Fs/16,−1
3Fs/16,1
−120
0 0.1 0.2 0.3 0.4 0.5 0.6
Frequency (MHz)
(b)
Figure 5.22: Simulation results for a 16-channel Π∆Σ converter after calibration. The
RLS algorithm was trained to obtain the dynamic range improvement of 16 dB. The
output spectrums for: (a) Fin = 350 kHz and (b) Fin = 430 kHz are plotted. The dashed
line indicates the expected mean of spectral peaks after calibration.
−20
−40
Magnitude, dBFS
−60
−80 Fs/2,−1
Fs/2,1 3Fs/8,1
Fs/8,1 3Fs/16,1
Fs/16,1
5Fs/16,−13Fs/8,−1
Fs/16,−1 7Fs/16,1
Fs/4,−1 3Fs/16,−1 7Fs/16,−1 Fs/4,1
−100 Fs/8,−1
5Fs/16,1
−120
0 0.1 0.2 0.3 0.4 0.5 0.6
Frequency (MHz)
(a)
−20
−40
Magnitude, dBFS
−60
−80
3Fs/8,1 Fs/4,1 Fs/8,1
3Fs/8,−1 Fs/2,−1 Fs/8,−1
Fs/2,1
7Fs/16,−13Fs/16,−1 Fs/16,−1 5Fs/16,1
7Fs/16,1 3Fs/16,1
−100 5Fs/16,−1
Fs/4,−1
Fs/16,1
−120
0 0.1 0.2 0.3 0.4 0.5 0.6
Frequency (MHz)
(b)
Figure 5.23: Simulation results for a 16-channel Π∆Σ converter after calibration. The
RLS algorithm was trained to obtain the dynamic range improvement of 33 dB. The
output spectrums for: (a) Fin = 350 kHz and (b) Fin = 430 kHz are plotted. The dashed
line indicates the expected mean of spectral peaks after calibration.
Conclusion
The first accomplishment of this thesis was the development of digital back-
ground calibration technique that is suitable for implementation in a fully monolithic
pipeline A/D converters. The developed technique is discussed in Chapter 3. The new
scheme utilizes an existing digital calibration algorithm developed by Karanicolas et.
al. [28] and extends it to work in real-time by incorporating two additional stages lo-
cated at the end of the pipeline. The theory and results of this work were published
in [55, 56]. At the time of its publication, other digital background calibration tech-
niques were reported in [25,44,45]. These are correlation-based background calibration
techniques, where a random signal is introduced in a pipeline stage and stage error terms
are measured in digital domain by removing the introduced random term. Calibration
techniques in [25, 45] rely on complex digital post-processing for extraction of calibra-
tion parameters and are slow to converge. Also, in [25] the calibration technique is de-
pendant on the input signal statistics. In addition to the required digital post-processing
in [44], an additional pipeline converter identical to the one being calibrated is required.
If not perfectly matched, the two ADCs will have an additional error sources due to
channel mismatches. The work presented in this thesis frees one conversion cycle for
calibration purposes by introducing two extra stages at the end of the pipeline. Once the
conversion cycle is available, a pipeline stage can be calibrated according to [28]. To
calibrate the first seven stages of a 16-stage pipeline A/D converter implemented using
1-bit/stage topology, a total of 154 clock cycles are needed and calibration is indepen-
dent of input signal statistics. The algorithm is successful in correcting for comparator
offset, charge injection, and capacitor mismatch errors [28].
A hardware model of the continuous digital calibration logic was designed using
σv2
E(β̂[n] − β) 0 − β
σw2
M σ2 2
M 2σv2 σv2
T v
Q[n] = E (β̂[n] − β) (β̂[n] − β) +
n σw2 n σw2 σw2
Table 6.1: Summary of the RLS algorithm convergence for n M +1 with and without
quantization noise present.
for calibration was simulated where a gain error was introduced to all channels, includ-
ing a calibration channel.
For the proposed calibration to be successful, each channel of a Π∆Σ converter
needs to be processing part of the input signal, otherwise the RLS algorithm cannot
detect the gain error for an inactive channel(s). The input signal must excite all of
the channels in the Π∆Σ architectures. Because this application is targeted for wide
bandwidth applications such as software radio (SWR) receive architectures, the input
signal constraint is not hard to meet. In SWR receiver architectures an ADC is required
to capture and entire cellular band that may contain multiple wireless standards and
signals from different wireless users. This multi-tone signal can be enough to excite all
the channels in a Π∆Σ architecture. An example of a multi-tone input signal that leads
to a successful calibration of gain errors was given in Section 4.10.
Further, to demonstrate the developed calibration technique in hardware, a chip
that contains ten second order ∆Σ modulators was designed and fabricated in a 0.5-µm
CMOS process technology. A four-layer printed circuit (PC) board was also designed
and fabricated. The PC board can support two custom designed chips which allowed for
testing and calibration of a 16-channel Π∆Σ converter. The chip design and test results
with and without calibration are discussed in Chapter 5. A test board was configured to
run 8 and 16 channels in parallel with an additional channel for calibration. Once a high-
[1] Digital cellular telecommunications system (Phase 2+); Radio transmission and
reception (GSM 05.05 version 8.5.1 Release 1999), ETSI EN 300 910 V8.5.1
(2000-11) ed., European Telecommunications Standards Institute, Nov. 2000.
[4] K. C. Zangi and R. D. Koilpillai, “Software radio issues in cellular base stations,”
IEEE Journal on Selected Areas in Communications, vol. 17, pp. 561–573, Apr.
1999.
[5] J. Mitola III, “Technical challengies in the globalization of software radio,” IEEE
Communications Magazine, pp. 84–87, Feb. 1999.
[7] J. Li and U.-K. Moon, “A 1.8-V 67-mW 10-bit 100-MS/s pipelined ADC using
time-shifted CDS technique,” IEEE Journal of Solid-State Circuits, vol. 39, pp.
1468–1476, Sept. 2004.
[8] Y.-T. Wang and B. Razavi, “An 8-bit 150-MHz CMOS A/D converter,” IEEE
Journal of Solid-State Circuits, vol. 35, pp. 308–317, Mar. 2000.
[9] S.-M. Yoo, J.-B. Park, S.-H. Lee, and U.-K. Moon, “A 1.8-V 67-mW 10-bit 100-
MS/s pipelined ADC using time-shifted CDS technique,” IEEE Transactions on
Circuits and System-II, vol. 51, pp. 269–275, May 2004.
[11] W. Yang, D. Kelly, I. Mehr, M. T. Sayuk, and L. Singer, “A 3-V 340-mW 14-b
75-Msample/s CMOS ADC with 85-dB SFDR at Nyquist input,” IEEE Journal
of Solid-State Circuits, vol. 36, pp. 1931–1936, Dec. 2001.
[22] K. Dyer, D. Fu, S. Lewis, and P. Hurst, “An analog background calibration tech-
nique for time-interleaved analog-to-digital converters,” IEEE Journal of Solid-
State Circuits, vol. 33, pp. 1912–1919, Dec. 1998.
[24] H.-C. Liu, Z.-M. Lee, and J.-T. Wu, “A 15-bit 40-MS/s CMOS pipelined analog-
to-digital converter with digital background calibration,” IEEE Journal of Solid-
State Circuits, vol. 40, pp. 1047–1056, May 2005.
[25] B. Murmann and B. E. Boser, “A 12-bit 75-MS/s pipelined ADC using open-loop
residue amplification,” IEEE Journal of Solid-State Circuits, vol. 38, pp. 2040–
2050, Dec. 2003.
[27] E. G. Soenen and R. L. Geiger, “An architecture and an algorithm for fully digital
correction of monolithic pipelined ADC’s,” IEEE Transactions on Circuits and
Systems-II, vol. 42, pp. 143–153, Mar. 1995.
[29] D. Fu, K. Dyer, S. Lewis, and P. Hurst, “A digital background calibration tech-
nique for time-interleaved analog-to-digital converters,” IEEE Journal of Solid-
State Circuits, vol. 33, pp. 1904–1911, Dec. 1998.
[34] H.-S. Lee, D. A. Hodges, and P. R. Gray, “A self-calibrated 15 bit CMOS A/D
converter,” IEEE Journal of Solid-State Circuits, vol. 6, pp. 813–819, Dec. 1984.
[35] J. Ming and S. H. Lewis, “An 8-bit 80-Msample/s pipelined analog-to-digital con-
verter with background calibration,” IEEE Journal of Solid-State Circuits, vol. 36,
pp. 1489–1497, Oct. 2001.
[36] Y.-M. Lin, B. Kim, and P. R. Gray, “A 13-b 2.5-MHz self-calibrated pipelined
A/D converter in 3-micron CMOS,” IEEE Journal of Solid-State Circuits, vol. 26,
pp. 628–636, Apr. 1991.
[42] T.-H. Shu, B.-S. Song, and K. Bacrania, “A 13-b 10-Msample/s ADC digitally
calibrated with oversampling delta-sigma converter,” IEEE Journal of Solid-State
Circuits, vol. 30, pp. 443–452, Apr. 1995.
[43] U.-K. Moon and B.-S. Song, “Background digital calibration techniques for
pipelined ADC’s,” IEEE Transactions on Circuits and Systems-II, vol. 44, pp.
102–109, Feb. 1997.
[46] X. Wang, P. Hurst, and S. Lewis, “A 12-bit 20 MS/s pipelined ADC with nested
digital background calibration,” in Proceedings of IEEE Custom IC Conf., San
Jose, Sept. 2003, pp. 409–412.
[48] M. Waltari, “Circuit techniques for low-voltage and high-speed A/D converters,”
Ph.D. dissertation, Helskinki University of Technology, Helsinki, Finland, May
2002.
[50] Y. Chiu, C. W. Tsang, B. Nikolić, and P. R. Gray, “Least mean square adaptive
digital background calibration of pipelined analog-to-digital converters,” IEEE
Transactions on Circuits and Systems-I, vol. 51, pp. 38–46, Jan. 2004.
[52] ——, “Adaptive blind calibration of timing offset and gain mismatch for two-
channel time-interleaved ADCs,” IEEE Transactions on Circuits and Systems-I,
vol. 53, pp. 1278–1288, June 2006.
[53] Z.-M. Lee, C.-Y. Wang, and J.-T. Wu, “A CMOS 15-bit, 125-MS/s time-
interleaved ADC with digital background calibration,” IEEE Journal of Solid-
State Circuits, vol. 42, pp. 2149–2160, Oct. 2007.
[56] ——, “Continuous digital calibration of pipeline A/D converters,” IEEE Transac-
tions on Instrumentation and Measurement, vol. 55, pp. 1175–1185, Aug. 2006.
[67] M. Kozak and I. Kale, “Novel topologies for time-interleaved delta-sigma modu-
lators,” IEEE Transactions on Circuits and Systems-II, vol. 47, pp. 639–654, July
2000.
[69] W. C. Black Jr. and D. A. Hodges, “Time interleaved converter arrays,” IEEE
Journal of Solid-State Circuits, vol. SC-15, pp. 1022–1029, Dec. 1980.
[70] A. Petraglia and S. K. Mitra, “Analysis of mismatch effect among A/D converter
in a time-interleaved waveform digitizer,” IEEE Transactions on Instrumentation
and Measurement, vol. 40, pp. 831–835, Oct. 1991.
[76] S.-H. Lee and B.-S. Song, “Digital-domain calibration of multistep analog-to-
digital converter,” IEEE Journal of Solid-State Circuits, vol. 27, pp. 1679–1688,
Dec. 1992.
[77] D. J. Smith, HDL Chip Design. Madison, AL: Doone Publications, 1996.
[81] S. Haykin, Introduction to Adaptive Filters. New York, NY: Macmillan Pub-
lishing Company, 1984.
[82] ——, Adaptive Filter Theory. Upper Saddle River, NJ: Prantice Hall, 1996.
[83] L. R. Rabiner, R. E. Crochiere, and J. B. Allen, “FIR system modeling and identi-
fication in the presence of noise and with band-limited inputs,” IEEE Transactions
on Acoustics, Speech, and Signal Processing, vol. ASSP-26, pp. 319–333, Aug.
1978.
[84] S. L. Marple Jr. and L. R. Rabiner, “Performance of a fast algorithm for FIR sys-
tem identification using least-squares anaysis,” The Bell System Technical Jour-
nal, vol. 62, pp. 717–742, Mar. 1983.
[85] A. Papoulis and S. U. Pillai, Probability, Random Variables and Stochastic Pro-
cesses, 4th ed. New York, NY: McGraw-Hill, 2002.
[87] B. Razavi, Design of Analog CMOS Integrated Circuits. New York, NY:
McGraw-Hill, 2001.
[93] Y. Chiu, P. R. Gray, and B. Nikolic, “A 14-b 12-MS/s CMOS pipeline ADC with
over 100-dB SFDR,” IEEE Journal of Solid-State Circuits, vol. 39, pp. 2139–
2151, Dec. 2004.
[94] K. Gulati and H.-S. Lee, “A high-swing CMOS telescopic operational amplifier,”
IEEE Journal of Solid-State Circuits, vol. 33, pp. 2010–2019, Dec. 1998.
[95] M. Das, “Improved design criteria of gain-boosted CMOS OTA with high-speed
optimizations,” IEEE Transactions on Circuits and Systems-II, vol. 49, pp. 204–
207, Mar. 2002.
[96] R. J. Baker, CMOS Circuit Design, Layout and Simulation, 2nd ed. Hoboken,
NJ: John Wiley & Sons, Inc., 2005.
[99] J. Elbornsson, F. Gustafsson, and J.-E. Eklund, “Blind equalization of time er-
rors in a time-interleaved ADC system,” IEEE Transactions of Signal Processing,
vol. 53, pp. 1413–1424, Apr. 2005.
Circuit Schematics
Table A.1: Device sizing for obtaining V b1 and V b2 biasing voltages in Figure A.1.
These will bias the fully differential tranconductance amplifier and CMFB circuit in
Figures 5.8 and 5.10.
Table A.2: Device sizing for obtaining V b3 and V b4 biasing voltages in Figure A.1.
These will bias the differential gain boosting amplifiers in Figure 5.9.
Figure A.3: Buffer designed to drive 100 fF loads. It is used in Figures A.10 and A.11.
Figure A.8: Buffer designed to drive 500 fF loads. It is used in Figure A.9.