SURVEY ON ANALOG TO DIGITAL CONVERTERS

SEMINAR REPORT
submitted by

ASWANI SURESH
ASI19ECVE02

to

the APJ Abdul Kalam Technological University

in partial fulfillment of the requirements for the award of the Degree
of
Master of Technology
In
VLSI and Embedded Systems

Department of Electronics and Communication Engineering

Adi Shankara Institute of Engineering and Technology, Kalady

MARCH 2021
 DECLARATION

I undersigned hereby declare that the seminar report “ SURVEY ON ANALOG TO

DIGITAL CONVERTERS” submitted for partial fulfillment of the requirements for the
award of degree of Master of Technology of the APJ Abdul Kalam Technological Univer-
sity, Kerala is a bonafide work done by me under supervision of Prof. Jaimy James and
Prof. Anju George. This submission represents my ideas in my own words and where
ideas or words of others have been included, I have adequately and accurately cited and
referenced the original sources. I also declare that I have adhered to ethics of academic
honesty and integrity and have not misrepresented or fabricated any data or idea or fact
or source in my submission. I understand that any violation of the above will be a cause
for disciplinary action by the institute and/or the University and can also evoke penal
action from the sources which have thus not been properly cited or from whom proper
permission has not been obtained. This report has not been previously formed the basis
for the award of any degree, diploma or similar title of any other University.

Ernakulam
29-03-2021 ASWANI SURESH
 DEPARTMENT OF ELECTRONICS AND COMMUNICATION
ENGINEERING
ADI SHANKARA INSTITUTE OF ENGINEERING AND
TECHNOLOGY, KALADY

CERTIFICATE

This is to certify that the seminar entitled “ SURVEY ON ANALOG

TO DIGITAL CONVERTERS” submitted by ASWANI SURESH ( ASI19ECVE02)
to the APJ Abdul Kalam Technological University in partial fulfillment of the require-
ments for the award of the Degree of Master of Technology in VLSI and Embedded
Systems in Electronics and Communication Engineering is a bonafide record of the sem-
inar work carried out by her under our guidance and supervision.This report in any form
has not been submitted to any other University or Institute for any purpose.

Seminar Guide Head of Department

Name : Prof. Jaimy James Name : Dr. Ragesh G K
Signature : Signature :

Seminar Coordinator
Name : Prof. Jaimy James
Signature :

‘
 ACKNOWLEDGEMENT

First and foremost I remember nature, for providing a guiding mind and good health
throughout the project. I wish to record my indebtedness and thankfulness to all who
helped me to prepare this report titled “ SURVEY ON ANALOG TO DIGITAL CON-
VERTERS” and present it in a satisfactory way.
No volume of words is enough to express my gratitude towards my project guides
Prof. Jaimy James Asst.Professor Dept. of Electronics and Communication Engineer-
ing, Prof. Anju George Asst.Professor Dept. of Electronics and Communication En-
gineering and Dr. Ragesh G K Professor and Head of the Dept. of Electronics and
Communication Engineering, for their valuable advice and guidance to carry out this
work. I express my heartfelt thanks to Dr. Suresh Kumar V, Principal, Adi Shankara
Institute of Engineering and Technology, Kalady for giving me their sole co-operation
and encouragement throughout my career at Adi Shankara Institute of Engineering and
Technology.

ASWANI SURESH
(Reg. No ASI19ECVE02)
M. Tech. (VLSI and Embedded Systems)
Department of ECE
Adi Shankara Institute of Engineering and Technology, Kalady

i
 ABSTRACT
Analog to Digital Converters (ADC) are critical components in communication,
biomedical and signal processing systems. They are data converters with one way con-
version from analog to digital domain. The signals in the real world appear in analog
domain and are converted to digital form with the help of an analog to digital converter
(ADC). ADCs has found application in many areas including digital signal processing,
music recording, scientific instruments, rotary encoder and so on. The seminar presents a
survey on different types of ADCs using different CMOS technologies for different appli-
cations. As VLSI technology is approaching a different level, high speed and low power
devices are becoming more preferable. It describes different ADC designs on VLSI plat-
form to achieve low power, low delay and high speed.

ii
Contents

ACKNOWLEDGMENT i

ABSTRACT ii

List of Figures v

List of Tables vi

List of Abbreviations vii

1 INTRODUCTION 1
1.1 Relevance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Organization of the Report . . . . . . . . . . . . . . . . . . . . . . . . . 2

2 LITERATURE SURVEY 3
2.1 Analog to Digital Converters . . . . . . . . . . . . . . . . . . . . . . . . 3
2.2 Characteristics of ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.2.1 Input Signal Bandwidth . . . . . . . . . . . . . . . . . . . . . . 4
2.2.2 Resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.2.3 Sample Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.2.4 Signal to Noise Ratio . . . . . . . . . . . . . . . . . . . . . . . . 5
2.2.5 Effective Number of Bits . . . . . . . . . . . . . . . . . . . . . . 6
2.2.6 Differential Non - Linearity . . . . . . . . . . . . . . . . . . . . 6
2.2.7 Integral Non - Linearity . . . . . . . . . . . . . . . . . . . . . . 7
2.3 Types of Analog to Digital Converters . . . . . . . . . . . . . . . . . . . 8
2.3.1 Flash ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3.2 Successive Approximation Register ADC . . . . . . . . . . . . . 9
2.3.3 Dual Slope ADC . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.3.4 Delta Sigma ADC . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.3.5 Pipelined ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.4 Types of Comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.4.1 Dynamic Comparators . . . . . . . . . . . . . . . . . . . . . . . 12
2.4.2 Latch Track Comparator . . . . . . . . . . . . . . . . . . . . . . 13
2.4.3 Low Voltage Comparator . . . . . . . . . . . . . . . . . . . . . . 14
2.4.4 High Speed Comparator . . . . . . . . . . . . . . . . . . . . . . 14
2.4.5 TIQ Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.5 Performance Comparison of Different ADCs . . . . . . . . . . . . . . . 16

iii
 2.6 Performance Comparison of Different Comparators . . . . . . . . . . . . 16

3 CONCLUSION 18

iv
List of Figures

2.1 Analog to Digital Converter . . . . . . . . . . . . . . . . . . . . . . . . 4

2.2 Sampled representation of a sinusoidal signal [4] . . . . . . . . . . . . . 5
2.3 DNL Representation on an ADC Transfer Curve [4] . . . . . . . . . . . . 6
2.4 Best Fit INL [4] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.5 End Point INL [4] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.6 Flash ADC [3] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.7 SAR ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.8 Dual Slope ADC [3] . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.9 Delta Sigma ADC [3] . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.10 Pipelined ADC [3] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.11 Conventional Dynamic Comparator [20] . . . . . . . . . . . . . . . . . . 13
2.12 Latch and Track Comparator [21] . . . . . . . . . . . . . . . . . . . . . 14
2.13 TIQ Comparator [2] . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

v
List of Tables

2.1 Comparison of Different ADCs . . . . . . . . . . . . . . . . . . . . . . . 16

2.2 Comparison of Different Comparators . . . . . . . . . . . . . . . . . . . 17

vi
List of Abbreviations

ADC Analog to Digital Converter

SAR Successive Approximation Register
SNR Signal to Noise Ratio
ENOB Effective Number of Bits
DNL Differential Non - Linearity
INL Integral Non - Linearity
LSB Least Significant Bit
DC Direct Current
DAC Digital to Analog Converter
MSB Most Significant Bit
CCD Charge Coupled Device
TIQ Threshold Inverter Quantization
CMOS Complementary Metal Oxide Semiconductor
PMOS P- Channel Metal Oxide Semiconductor
NMOS N- Channel Metal Oxide

vii
Chapter 1
INTRODUCTION

The signals in the real world appear in analog domain and is converted into digital
domain to transmit digital signals. So signals are classified as analog and digital. Parti-
tioning of system into analog and digital is based on certain specification of signal such
as their frequency. For the bandwidth of above 10MHz, signal are processed in analog
domain; for the bandwidth below 100Hz, signals are processed in digital domain; and for
the signal lying in the range of 100Hz to 10MHz there is a trade-off between accuracy
and exibility of digital approach and cost, power and size of analog approach.
Analog-to-digital converters are a class of data converters with one way conversion
from Analog-to-Digital domain. The implementation of ADC is usually done either as
serial or parallel converters. Before converting a signal to digital domain, an analog signal
is first converted to discrete form using Sample and Hold circuit. Next if the sample is
simultaneously compared to different Quantization levels and converted to digital domain
in a single step, it is termed as Parallel Converter. If the system compares the sampled
output to the dierent Quantization levels in serial fashion, it is termed as Serial Converter.
Some of the common ADCs are Flash ADC, SAR ADC, Dual Slope ADC and Delta
Sigma ADC. Flash ADC is an example for parallel ADC and SAR ADC for a serial
ADC.

1.1 Relevance
ADCs are used virtually everywhere, whenever an analog signal has to be transported,
it is processed and stored in digital form. They are always used together with different
transducers to convert physical sense and measurement such as temperature, pressure,

1
humidity, speed, vibration, sound, picture etc. Analog-to-Digital Converters (ADCs) are
critical components of biomedical, communications and signal processing systems which
require low power consumption and high conversion efficiency and are used to convert
the real world signal to digital signal for the purpose of processing.

1.2 Organization of the Report

This seminar deals with different types of ADC architecture. The report can be orga-
nized in the following manner.
• Chapter 1 focuses on Introduction.
• Chapter 2 focuses on survey of different ADC architecture and comparison between
different parameters.
• Chapter 3 describes the conclusions obtained from the literature survey.

2
Chapter 2
LITERATURE SURVEY

This chapter explains about analog to digital converters, its characteristics and differ-
ent types of ADCs that are commonly used.

2.1 Analog to Digital Converters

In the real world, analog signals have continuously changing values which come from
various sources like sound, light, temperature or movement, and the digital systems mea-
sures the analog signals to give discrete signals. While analog signals are continuous
and provide an infinite number different voltage values, digital circuits are binary signal
which have only two discrete states, a logic “1” (HIGH) or a logic “0” (LOW). Basically,
it is a converter which converts the analog (continuously variable) signal to digital sig-
nal. The ADCs are usually implemented either as serial or parallel converters. Before
converting a signal to digital domain, an analog signal is first converted to discrete form
using Sample and Hold circuit. Next if the sample is simultaneously compared to differ-
ent Quantization levels and converted to digital domain in a single step, it is termed as
Parallel Converter. If the system compares the sampled output to the different Quanti-
zation levels in serial fashion, it is termed as Serial Converter. The example of Parallel
Converter is Flash Converter and that of Serial Converter is Dual Slope and Successive
Approximation Register (SAR) [2].

3
 Figure 2.1: Analog to Digital Converter

2.2 Characteristics of ADC

Analog to digital conversion includes the sampling of analog input and processing of
the sampled signal to generate digital output. The basic characteristics of an ADC are:

1. Input Signal Bandwidth

2. Resolution

3. Sample Rate

4. Signal to Noise Ratio (SNR)

5. Effective Number of Bits (ENOB)

6. Differential Non-Linearity (DNL)

7. Integral Non-Linearity (INL)

2.2.1 Input Signal Bandwidth

The frequency range of analog signal that can be passed through the analog front end
with a minimal loss in the amplitude is called as the bandwidth of the input signal.

4
2.2.2 Resolution

Resolution of the converter indicates the number of discrete values it can produce. It
is the smallest amplitude change in the input signal that can be distinguished by an ADC.
It is expressed in terms of bits. For an N-bit ADC, its resolution is also N-bits.

2.2.3 Sample Rate

The analog signal is continuous in time and it is necessary to convert this to a flow
of digital values. Sampling is the first step in the conversion of analog signal into digital
form. It is defined as the number of samples of input signal taken per second. According
to the Nyquist theorem, for any band limited signal with maximum frequency (Fmax ),
the sampling frequency must be at least equal to or greater than twice Fmax in order to
reconstruct the signal properly, ie., if the sampling frequency is less than twice Fmax , the
signal cannot be reconstructed perfectly. Therefore, higher the number of samples better
would be its reconstruction. This is shown in Figure 2.2

Figure 2.2: Sampled representation of a sinusoidal signal [4]

2.2.4 Signal to Noise Ratio

SNR is the ratio of signal power relative to that of the noise power. Higher the value
of SNR better will be the quality of the signal.
It is defined as

5
 Psignal
SNR = (2.1)
Pnoise

2.2.5 Effective Number of Bits

The resolution of an ADC is specified by the number of bits used to represent the
analog value. Ideally, a 12-bit ADC will have an ENOB of almost 12. However, real
signals have noise, and real circuits are imperfect and introduce additional noise and
distortion. Those imperfections reduce the number of bits of accuracy in the ADC. The
ENOB describes the effective resolution of the system in bits. An ADC may have 12-bit
resolution, but the effective number of bits when used in a system may be 9.5.
ENOB is given as

SNR − 1.76
ENOB = (2.2)
6.02

2.2.6 Differential Non - Linearity

DNL is commonly used to measure the performance of a converter. For an ideal

ADC, the output is divided into 2N uniform steps. Any deviation from the ideal step
width is called DNL and is measured in number of counts (LSB). ie., it is the difference
between an actual step width and the ideal value of 1 LSB [4]. Figure 2.3 below shows
representation of DNL in an ADC transfer curve.

Figure 2.3: DNL Representation on an ADC Transfer Curve [4]

6
2.2.7 Integral Non - Linearity

INL also similar to DNL is used to measure the performance of a converter. It is the
deviation between the ideal input threshold value and the measured threshold level of a
certain output code. In the other words, INL is a measure of how closely the ADC output
matches its ideal response. INL can be defined as the deviation in LSB of the actual
transfer function of the ADC from the ideal transfer curve. There are two methods to find
the INL error:

1. Best fit (best straight line) method.

2. End point method.

Best fit (best straight line) method

The best fit method of INL measurement considers offset and gain error. Here the
ideal transfer curve considered for calculating best-fit INL does not go through the ori-
gin. The ideal transfer curve here is drawn such that it depicts the nearest first-order
approximation to the actual transfer curve of the ADC. The intercept and slope of this
ideal curve can lend us the values of the offset and gain error of the ADC [4]. It is illus-
trated in Figure 2.4.

Figure 2.4: Best Fit INL [4]

End point method

The End-Point method provides the worst case INL. This measurement passes the
straight line through the origin and maximum output code of the ADC. As this method

7
provides the worst case INL, it is more useful to use this number for DC applications. It
is illustrated in Figure 2.5

Figure 2.5: End Point INL [4]

2.3 Types of Analog to Digital Converters

There are many types of Analog to Digital Converter available. They can be classified
depending on their: Structure, resolution, power consumption etc. Thus ADCs can be
divided into:

1. Flash ADC

2. Successive Approximation Register (SAR) ADC

3. Dual Slope ADC

4. Delta Sigma ADC

5. Pipelined ADC

2.3.1 Flash ADC

A Flash ADC is illustrated in Figure 2.6. Flash or Parallel Analog-to Digital Con-
verter is the simplest type of ADC and is also the fastest ADC, i.e., it requires only a
single cycle time for conversion.

8
 Figure 2.6: Flash ADC [3]

Flash ADCs are made of a series of high-speed comparators. For an N-bit converter,
the circuit employs 2N − 1 comparators and a resistive - divider with 2N resistors to pro-
vide the reference voltage. Each comparator produces a 1 when its analog input voltage
is higher than the reference voltage and a 0 if input is lower than the reference voltage.
Flash ADCs are ideal for applications requiring very large bandwidth and are generally
limited to 8-bit resolution. Some examples are satellite communication, radar processing,
sampling oscilloscopes and high-density disk drives.

2.3.2 Successive Approximation Register ADC

A SAR ADC is illustrated in Figure 2.6. SAR ADCs are the frequently used ar-
chitecture for medium-to-high-resolution applications with sample rates under 5 MSps.
Resolution for SAR ADCs most commonly ranges from 8 to 16 bits with a low power
consumption. It is used in applications like portable/battery-powered instruments, pen
digitizers, industrial controls, and data/signal acquisition.

Figure 2.7: SAR ADC

9
 At first the analog input voltage (VIN ) is held on a track/hold. To implement the
binary search algorithm, the N-bit register is first set to midscale where the MSB is set to
1. This forces the DAC output (VDAC ) to be VREF /2, where VREF is the reference voltage.
Then VIN is compared to VDAC . If VIN is greater than VDAC , the comparator output is a
logic high, or 1, and the MSB of the N-bit register remains at 1. If VIN is less than VDAC ,
the comparator output is a logic low and the MSB of the register is cleared to logic 0.
The SAR control logic then moves to the next bit down, forces that bit high, and does
another comparison. The sequence continues all the way down to the LSB. Once this is
done, the conversion is complete and the N-bit digital word is available in the register.

2.3.3 Dual Slope ADC

Dual slope integrating ADC is the most accurate, low power, high resolution Data
converter. It has least probability of error, i.e. maximum noise immunity. Its only limi-
tation is its low speed as it is the slowest Data converter with conversion time of 2 ∗ 2N
cycles. Figure 2.8 shows a Dual Slope ADC.

Figure 2.8: Dual Slope ADC [3]

Here the integrating action is performed for the fixed period of time. The value of
integration varies proportionally with input voltage sampled value. The capacitor is then
allowed to discharge and the counter runs for the discharging period thus converting
analog signal to digital word [3].

10
2.3.4 Delta Sigma ADC

Figure 2.9 shows a Delta Sigma ADC. This ADC is famous for its high resolution and
low power consumption with high stability. Due to oversampling the speed is moderate.
In addition large area is required for higher order and multi-bit system [3]. It has a wide
range of applications in biomedical fields such as Neural Recording System, biosensors,
implants etc.

Figure 2.9: Delta Sigma ADC [3]

The input signal is fed to an integrator, which senses the rate of change of voltage, and
is fed to a comparator. Based on whether the slope of integrator is positive or negative,
the output of comparator is logic “0” or “1”. This output is latched through a D Flip-Flop
and fed back to the integrator through an Op-Amp [3].

2.3.5 Pipelined ADC

An N stages Pipelined ADC is shown in Figure 2.10. The speed of the ADC is
increased by using N stages. It is the combination of parallel ADCs in series approach.
Its advantages are high speed, high resolution and low power. Its conversion time is
2N/2 − 1.

Figure 2.10: Pipelined ADC [3]

Each stage of the pipeline ADC consists of a sample-and-hold circuit, a sub-ADC,

a DAC, a subtractor and an inter-stage gain amplifier. Resolutions range from 8 bits
to 16 bits. Its applications includes CCD imaging, ultrasonic medical imaging, digital
receivers, base stations, digital video.

11
2.4 Types of Comparators
Comparators are the main building block and are widely used in the process of con-
verting analog signal into digital domain. The analog signals are applied to a combination
of comparators to determine the digital equivalent of the analog signal. Flash types ADC
is the fastest data converter which uses (2N-1) number of comparators to simultaneously
to compare the analog input voltage with the reference input voltages. In the flash ADC,
the output of the comparator is obtained in the form of thermometer code and then using
an encodes the thermometer code form of digital data converted into the binary outputs
form. Below given are some of the comparators that are commonly used:

1. Dynamic Comparators

2. Latch Track Comparator

3. Low Voltage Comparator

4. High Speed Comparator

5. TIQ Comparator

2.4.1 Dynamic Comparators

The use of a large number of comparators in the ADC usually increases the power
dissipation. Dynamic comparator reduces the power dissipation of the ADC by eliminat-
ing the static power dissipation. The use of dynamic comparator in the ADC increases the
value of offset voltage and reduce the gain of the circuit. In order to make a high speed
and low power comparator, the preamplifier-based comparator is used in the high-speed
comparator. The double tail dynamic comparator is a popular circuit used with a differ-
ent tail transistor for both pre-amplifier and latch stage to avoid the drawbacks like static
mismatches and noise. A noise in the comparator can be reduced using a cross-coupled
inverter.

12
 Figure 2.11: Conventional Dynamic Comparator [20]

2.4.2 Latch Track Comparator

The first stage of the circuit is functioning as a preamplifier which amplifies the in-
put signal to improve the sensitivity of the comparator. The second stage of the circuit
compares the reference voltage with the input voltage for analog to digital data conver-
sion. The circuit has two inputs. One input is an analog input and the second one is the
reference input from the resistive ladder of the flash ADC. A clock signal to the NMOS
transistor of the preamplifier erases the residual voltage stored in the previous sample. In
the direct result of the preamplifier i.e., the first stage of the latch track comparator, the
output may be affected with the noise of the clocked comparator due to large amounts of
charge transfer from track to hold mode. The second stage of the comparator track the
input sample and hold the output with respect to the changes of the clock signal.

13
 Figure 2.12: Latch and Track Comparator [21]

2.4.3 Low Voltage Comparator

The importance and wide applications of an ADC push the researchers to design a
comparator with low voltage, low power, low area overhead with the conversion im-
proved speed. In the differential configuration of the comparator, A reference voltage is
applied as one input and the analog input signal is applied as another input. When an
analog input voltage is greater than the reference voltage the differential amplifier am-
plifies the difference as positive. When an analog input voltage is less than the reference
voltage the differential amplifier amplifies the difference as negative or zero.

2.4.4 High Speed Comparator

It is constructed using a differential amplifier based op-amp circuit. The circuit of

a high-speed comparator is formed with the combination of a high-speed comparator
and the differential op-amp circuit. Low-frequency operation in the comparator uses to
provide high accuracy in the comparison. But in high frequency comparison, the parasitic
components and the component mismatches have to be eliminated in the circuit.

14
2.4.5 TIQ Comparator

Threshold Inversion Quantization (TIQ) comparator is a form of cascaded CMOS in-

verter which considers the threshold voltage (Vth) of an inverter as a reference voltage
in the ADC. In the cascade form of CMOS inverter, the combination of the PMOS and
NMOS forms the first stage of an inverter functions as the comparator through the com-
parison of an analogue input voltage with the threshold voltage. And the combination of
the PMOS and NMOS forms the second stage of the inverter functions as the gain com-
parator to provide the voltage swing in the output voltage equal to the supply voltage.

Figure 2.13: TIQ Comparator [2]

15
2.5 Performance Comparison of Different ADCs

Table 2.1: Comparison of Different ADCs

Topology Flash SAR ADC Dual Slope Delta Pipelined

ADC ADC Sigma ADC ADC
Sampling Rate High Medium Low Low Medium-
(Samples/sec) (1G-10G) (100K- (100-1000) (10K-1M) High
10M) (100M-1G)
Resolution Low Medium Medium High Medium
(Bits) (6-8) (12-18) (12-18) (16-24) (12-18)
Power
Consumption High Low Low Low High
Area High Low Low Medium High
Conversion
Time 1 Variable 2*2N High 2N/2 − 1
(No. of cycles)

Performance parameters of ADCs such as resolution which indicates the number of

discrete values it can produce over the range of analog values, sampling rate i.e. the
rate at which new digital values are sampled from the analog signal, power consumption
which is the rate at which electrical energy is utilized in a circuit and conversion time, the
time taken by the system to convert a discrete sample to digital value, along with latency,
accuracy, size and cost have been explored to compare the various ADC topologies and
is summarized by Table 2.1.

2.6 Performance Comparison of Different Comparators

In comparison, a TIQ comparator has low power dissipation and the and the use of
transistors are also less compared to all other comparators. Low voltage comparator used
less transistor count next to TIQ comparator but it takes large power compared to TIQ
comparators. Other types of comparators are using a relatively large number of a large
number of transistors count in the comparison.

16
 Table 2.2: Comparison of Different Comparators

Parameters Dynamic Latch- Low High Speed TIQ Com-

Com- track Voltage Comparator parator
parator Compara- Compara-
tor tor
Technology 180nm 180nm 180nm 180nm 180nm
CMOS CMOS CMOS CMOS CMOS
Supply Voltage
1.8 V 1.8 V 1.8 V 1.8 V 1.8 V
Input Freque-100 KHz 100 KHz 100 kHz 100 KHz 100 KHz
ncy
Power Consu- 309.9 nW 648.43 W 812.5 W 1.084 W 5.098 fW
mption
No. of Transis- 19 12 21 8 4
tors

17
Chapter 3
CONCLUSION

Various ADCs have been compared such as Flash ADC works with maxi- mum speed
but consumes large area and has low resolution. Similarly, SAR can be used to attain
ultra-low power at the cost of either resolution or speed, whereas Sigma Delta gets the
maximum resolution and Dual Slope consumes minimum power. Hence there is a trade-o
between various performance pa- rameters like resolution, sampling speed, power con-
sumption, area and others depending upon the application requirement. For biomedical
implants, for instance, system should work at moderate speed, low power consumption,
hence an SAR, a dual slope or a hybrid is suitable to use. For wireless sensor networks,
we require high resolution and low power, hence SAR and Sigma Delta is the better
option.
Also different comparator architectures are also compared to determine the best one.
TIQ comparator is the most efficient one as it requires only less power, delay and number
of transisters compared to others.

18
Bibliography

[1] S. Tiwari and A. Kumar, “Reconfigurable Flash ADC Using TIQ Technique,” 2018
4th International Conference on Computing Sciences (ICCS), Jalandhar, India,
2018, pp. 204-208, doi: 10.1109/ICCS.2018.00041.

[2] R. Sireesha and A. Kumar, “Design of low power 0.8V Flash ADC using TIQ in
90nm technology,” 2015 International Conference on Smart Technologies and Man-
agement for Computing, Communication, Controls, Energy and Materials (ICSTM),
Avadi, India, 2015, pp. 406-410, doi: 10.1109/ICSTM.2015.7225451.

[3] S. Bashir, S. Ali, S. Ahmed and V. Kakkar,“Analog-to-digital converters: A com-

parative study and performance analysis,” 2016 International Conference on Com-
puting, Communication and Automation (ICCCA), Greater Noida, India, 2016, pp.
999-1001, doi: 10.1109/CCAA.2016.7813861.

[4] Y. Lavania, “Low power encoder and comparator design of 5-bit flash ADC”, 2013

[5] Saurabh Pargaien, Dikendra Verma, OmPrakash, Ankur Singh Bist, Anubhav
Patrick. “Design And Simulation of Different Comparators Using Cadence Virtuoso
Analog Design- A Comparative Study”. 2020, International Journal of Advanced
Science and Technology

[6] L. Nazir, R. N. Mir and N. Hakim, “A 4 GS/s, 1.8 V multiplexer encoder based
flash ADC using TIQ technique,” 2014 International Conference on Signal Pro-
cessing and Integrated Networks (SPIN), Noida, India, 2014, pp. 458-463, doi:
10.1109/SPIN.2014.6776997.

19
 [7] J. I. Lee and J. Song, “Flash ADC architecture using multiplexers to reduce a
preamplifier and comparator count,” 2013 IEEE International Conference of IEEE
Region 10 (TENCON 2013), Xi’an, China, 2013, pp. 1-4, doi: 10.1109/TEN-
CON.2013.6718487.

[8] M. Kulkarni, V. Sridhar and G. H. Kulkarni, “4-bit Flash Analog to Digital Con-
verter design using CMOS-LTE Comparator,” 2010 IEEE Asia Pacific Confer-
ence on Circuits and Systems, Kuala Lumpur, Malaysia, 2010, pp. 772-775, doi:
10.1109/APCCAS.2010.5774817.

[9] L. Wu, F. Huang, Y. Gao, Y. Wang and J. Cheng, “A 42 mW 2 GS/s 4-

bit flash ADC in 0.18-m CMOS,” 2009 International Conference on Wire-
less Communications Signal Processing, Nanjing, China, 2009, pp. 1-5, doi:
10.1109/WCSP.2009.5371596.

[10] Khot, P. S., Dr. P. W. Wani and Dr M S Sutaone. “Design of a 45 nm TIQ Compara-
tor for High Speed and Low Power 4-Bit Flash ADC.” (2010).

[11] Goswami, M., Varma, D.M., Saloni et al. “Reduced comparator high speed low
power ADC using 90 nm CMOS technology”, Analog Integr Circ Sig Process 74,
267–278 (2013).

[12] Mohammad Rizwan, “Design and analysis of a comparator for ADC in Tanner
EDA.” International Research Journal of Engineering and Technology (IRJET),
2020.

[13] RamPrasadJ, M., B. Kariyappa and R. Holla. “Design and Implementation of Flash
ADC for Low Power Applications.” IOSR journal of VLSI and Signal Processing 4
(2014): 41-46.

[14] Abumurad, A., Choi, K. “Design Procedure and Selection of TIQ Comparators for
Flash ADCs”, Circuits Syst Signal Process 37, 500–531 (2018).

[15] Bhat P.A., Mir R.N. “Design of Low Power High Speed 4-Bit TIQ Based CMOS
Flash ADC”, Proceedings of International Conference on Advances in Comput-

20
 ing, Advances in Intelligent Systems and Computing, vol 174. Springer, New Delhi,
2013.

[16] P. E. Allen and D. R. Holberg, “CMOS Analog Circuit Design”, 2nd Edition, Oxford
University, Oxford, 2007.

[17] Razavi,Behzad. “Design of Analog CMOS Integrated Circuits”. India: Tata

McGraw-Hill, 2002.

[18] S. Hussain and M. Kumar, “Design of an efficient 8-bit flash ADC for optical com-
munication receivers,” 2016 International Conference on Electrical, Electronics,
and Optimization Techniques (ICEEOT), Chennai, India, 2016, pp. 449-453, doi:
10.1109/ICEEOT.2016.7755560.

[19] S. Sheikhaei, S. Mirabbasi and A. Ivanov, “A 0.35 /spl mu/m CMOS comparator
circuit for high-speed ADC applications,” 2005 IEEE International Symposium on
Circuits and Systems, Kobe, Japan, 2005, pp. 6134-6137 Vol. 6, doi: 10.1109/IS-
CAS.2005.1466040.

[20] Patel, Chandrahash, “Study of Comparator and their Architectures”, IJMC. (2018).

[21] Cortes, Fernando da Rocha Paixão, A. Girardi and S. Bampi. “Track-and-Latch

Comparator Design Using Associations of MOS Transistors and Characterization.”
2006 13th IEEE International Conference on Electronics, Circuits and Systems,
(2006).

[22] Arthur Lombardi Campos, Joo Navarro and Maximiliam Luppe, “De- sign of a
low power 10-bit 12MS/s asynchronous SAR ADC in 65nm CMOS”,in 2019 32nd
Symposium on Integrated Circuits and Systems De- sign (SBCCI).

[23] Z. Chen, M. Miyahara and A. Matsuzawa, “A 9.35-ENOB, 14.8 fJ/Conv.-Step

Fully-Passive Noise-Shaping SAR ADC”, IEEE Symposium on VLSI Circuits, pp.
C64-C65, 2015.

21
[24] M. V. Elzakker, E. V. Tuijl, P. Geraedts, D. Schinkel, E. Klumperink and B. Nauta
,“A 1.9W 4.4fJ/Conversion-step 10b 1MS/s Charge- Redistribution ADC”, IEEE
ISSCC Dig. Tech. Papers, pp. 244-245, 2008.

[25] C.-C. Liu, S.-J. Chang, G.-Y. Huang, Y.-Z. Lin and C.-M. Huang,“A 1V
11fJ/Conversion-Step 10bit 10MS/s Asynchronous SAR ADC in 0.18m CMOS”,
IEEE Symposium on VLSI Circuits, pp. 241-242, 2010.

[26] Javad Ahmadi-Farsani and Jose M. de la Rosa “Bulk-Input VCO-based Sigma-

Delta ADCs with Enhanced Linearity in 28-nm FD-SOI CMOS”, Instituto de Mi-
croelectronica de Sevilla, IMSE-CNM (CSIC/Universidad de Sevilla) C/Americo
Vespucio, 41092 Sevilla, SPAIN, 2019.

[27] D. S. Shylu, S. Jasmine, D. Jackuline Moni, “A Low Power Dy- namic Comparator
for a 12-bit Pipelined Successive Approximation Reg- ister (SAR) ADC”, Fourth
International Conference on Devices, Circuits and Systems (ICDCS’18), 16th and
17th Mar 2018.

22