Hardware Modeling using Verilog

Prof. Indranil Sengupta

Department of Computer Science and Engineering
Indian Institute of Technology, Kharagpur

Lecture - 02
Design Representation

In this lecture we shall be talking about Design Representation. Now, earlier I had said
that you can create a design using a hardware description language, Verilog with respect
to this course. Suppose we create a design in some hardware description language like
Verilog. Now, the question arises at what level do it typically create the design, or how do
we create? How do we visualize a design?

So, when we talk about design representation, what you mean is that, given a design, how
we can visualize the same design from different angles? Now, the way we shall be
presenting here is that there are three distinct ways or three distinct angles from where you
can visualize the same design and the implications will be a little different, let us see.

(Refer Slide Time: 01:22)

So, design representation as I said this talks about how we represent a design. A design is
nothing but you can think it as a black box that is trying to perform its intended operation.
You have designed that block to carry out certain operation and that is your design, ok.
Now, design representation, we are considering at three different levels, one you are
calling it as behavioral, structural and physical.
Now, with respect to Verilog coding these terms behavioral and structural will be coming
repeatedly and we will be understanding the exact differences and how we can code
behavioral and structural designs in Verilog in a very efficient way and of course, the third
representation is physical. Now, there is a very interesting way to just express this design
views or viewpoints, it is with respect to something called a Y-diagram.

(Refer Slide Time: 02:39)

Now, this name has come because it has a shape of a Y. So, you think of an imaginary Y
with the three design representations, in the three directions. Let us say, this is our
behavioral domain, this is our structural domain and this is our physical domain. Now, just
along each of these domains, like for example, in the axis of behavioral domain. Here we
are talking about a design in terms of its behavior, like in a very high level case, you can
think of an algorithm or a program, you can think of a specification, you can think of
Boolean expressions, you can think of truth tables, state diagram and so on, these are all
examples of behavior.

Now, when we talk about structural domain, now well we had explained in the last lecture
what is a netlist and netlist is nothing but some building blocks and their interconnections.
Now, this building blocks can define at various different levels, depending on that our
structural domain specifications can vary. So, it can be at the register transfer level, it can
be at the functional level, it can be at the gate level, transistor level and so on. And talking
about the physical domain, here you are actually talking about the implementation. Like
in the ultimate case, when the final design is complete, we would be getting our chips or a
printed circuit board.

Before that our designs will be placed on a silicon layout in terms of cells. Now, what will
those cells contain? They will contain some transistors, which will have some layout. So,
these are all implementation or physical design related things, that our chip, the cells that
are put on a chip and the transistors that make a cell. So, here we are looking from an angle
which talks about the actual implementation, ok.

So, in one side was the behavior, one side was the netlist view and the other side was the
actual physical implementation view. So, these are the three viewpoints, now there is some
interesting ways to look at these Y, let us look at it once more from this point of view.

Here we have showed it in a slightly different way, behavior, structural, geometry and you
see, we have drawn some concentric circles. The outer most circle indicates the most
abstract design, so at the behavioral level, this outside circle indicates systems, is like in
the highest level, my system may consist of two processors, one memory and one I/O
module, this is my highest level design of the system.

(Refer Slide Time: 05:55)

So, this is my behavior, so, this in the structural level will be a netlist that consisting of
interconnection of CPUs and memories as I have said the example and in the physical
level, this will consist of some chips, a collection of chips one may be processor, one may
be memory and so on, ok. So, as you go to the inner circles you are carrying out synthesis,
you are refining your design like at the next level your behavior is your algorithms. Here
you have subsystems and buses, here you have some clusters, next level you have register
transfer level blocks, you have ALU’s and registers netlist level and here you have macros
and floor plans.

Next level inside you have logic cells, gates and flip flops. So, here you have connection
of gates and flip flops, here you have cells module plans and at the lowest level you have
the transfer functions, transistors and polygons. So, as you go from the outer most circle
towards the inner most circle, from all the three viewpoints your design is getting refined,
from very high level or abstract, see from a very abstract level in the behavior, you will
say the well I want a computer system.

In the structural level, you will say that well I need two processors and one memory more
block. Now in the physical level you will say that well on the board I need four chips, these
are the different ways to look at the same thing. So, as we move towards the centre of the
circle each of these blocks will get further refined, they will get more detailed out and will
be having some kind of a top down design process.

Now, if you think of it well we normally do not do it this way that at one level, we have
all the three viewpoints, then we go to the next level, again look at all the three viewpoints.
So, we really do not work exactly in that way, rather we work in an alternate way which
is shown in the diagram on the right. So, here I am showing the behavior axis here,
structural here and geometric here or the physical here. Now you see; here I am giving an
example, we start with an algorithm at the behavioral level, so, highest level is algorithm.

So, we carry out some transformations in a systematic way which is represented you see
as a helix here, from the outside you slowly move towards the inner most point of this of
this structure. So, from the algorithm; you translate into processer which you translate into
a chip floor plan and each of the blocks in a chip floor plan you translate into finite set
machines; they will be translated into registers and ALU’s, they will be translated the
physical level into modules which will be placed module placement.

Then each of these modules; will be having a description at the behavioral level module
description now each of the modules will be designed as a netlist we call them as a leap
cell, they will be placed cell placement. Now, each of the cell will be expressed as Boolean
expressions they will be realize using transistors and finally, they will be realized using
the layout masks.

So, you see this is, this helical structure is more natural in terms of the steps that a designer
actually follows. So, although that concentric circle is a good way of representing, but the
actual process that you follow is this helix, from the outermost point we slowly move
towards the centre of the Y, ok, this is the so-called top down design process.

(Refer Slide Time: 10:07)

Ok, so let us again come back to the behavioral representation, here we shall be showing
you some examples in Verilog. So, just to repeat in the behavioral representation we
specify, how a particular design should work, that means, given a set of inputs, what should
be its output. So, here we are not telling that exactly how the design has to be implemented.
Some examples of behavioral representation are Boolean expressions, truth tables table of
input and output values.

So, you can write algorithms in some standard high level language like C that is also
behavior or algorithms written in hardware description languages like Verilog or VHDL
these are all examples of behavioral representation.
(Refer Slide Time: 11:01)

Now, let us take an example a simple example of a full adder. So, a full adder we will have
two inputs A and B and a carry input C. So, it will be generating a carry output and a sum
like this; A, B, C are the inputs and S and Cy are the outputs. Well, now I am not trying to
explain how a full adder works; you already know the basic definition of full adder; I am
just writing the logic expressions of the sum and carry. So, the sum and carry expression
in terms of A, B, C will be this: A B bar C bar OR A bar B bar C OR A bar B C bar OR A
B C; which is nothing but A exclusive OR B exclusive OR C.
S = AB′C′ + A′B′C + A′BC′ + ABC = A ⨁ B ⨁ C
Cy = AB + AC + BC
So, it is the exclusive OR of the three inputs that is sum and carry is nothing but AB OR
AC OR BC. So, this is one way of expressing the behavior of a full adder, because here
you are not specifying what kind of gates to use, how many gates to be used and so on.
We are just writing down the expressions and we are telling that well this is your sum and
this is your carry, this will be the behavior, right, this is an example.
(Refer Slide Time: 12:33)

Now, this is in terms of Boolean expression the same thing you can express in Verilog as
follows well I have not talked about the syntax of Verilog.

So, possibly this is your first look at a Verilog program, let us see what it contains. The
syntax is somewhat similar to the language C, here every statement ends with a semicolon.
This is like a function in C, this is called the module. So, Verilog program will consist of
one or more modulus. So, it starts with this keyword module, it ends with endmodule, this
is, this module is followed by the name of the module and the parameters. The parameters
are well in terms of the hardware these are nothing but the input and the output ports of
that block.

Now for a full adder, the inputs are A, B, C and the outputs are carry out and sum, right.
So, this S, Cy, A, B, C are the five parameters, we declare, A, B, C as input like this, input
A, B, C, output S, Cy. So, that the CAD tool will know that which are your input pins,
input signals which are your output signals and there is an assign statement available in
Verilog, here we are showing it using assign you can directly write down the Boolean
expression.

This hat (⋀) is the expression for Exclusive OR this indicates XOR. So, sum is A XOR B
XOR C and this ampersand (&) is AND, bar (|) is OR, carry is AB OR BC OR CA. So,
you see in Verilog you can express Boolean expression, which is behavioral specification
very concisely in this way using the assign statement, ok.
(Refer Slide Time: 14:42)

So, this is one way to specify a behavioral specification in Verilog. Now, this same design,
the full adder I am showing only one of the output the carry, well just if we recall the carry
is nothing but AB OR BC OR CA.

(Refer Slide Time: 14:55)

So, you tell me when the carry will be 1? The carry will be 1 for several conditions of A,
B and C, when either A and B is 0, but C is, A, B is 1, C is 0, A and C is 1, B is 0 or B and
C is 1, A is 0 or all these three are 1.
So, for these four cases my carry will be 1, for all other cases carry is 0. So, this I can
express or as a as a truth table. So, how do I express? Well I need not have to specify all
the rows; I can simply say that at least two must be 1; A B, A C or B C, at least two. If it
is 1; then the carry will be 1; this is what you are specify here, you see; in this truth table.

So, this is again a way to express a behavioral specification in Verilog in terms of the truth
table. So, there is a keyword called primitive. So, we use this primitive keyword here; so,
I am only showing for carry. So, there are four parameters this is the output A, B, C are
the inputs. So, I declare the input and output signals. So, I use a keyword table; so, here
this is a comment just for showing that these are the values of A, B, C and this is Cy this
is a comment line, just for convenience.

And the way you specify the input is, you specify 0 or 1 and question mark means don’t
care and colon separates inputs and outputs. The first line says; if A and B there 1, but C
is don’t care; then carry is 1; like you see here I means if A and B are 1, C is 0 then also
carry will be 1, but if A and B are 1, C is 1; then also carry is 1. So, actually C is a don’t
care; it does not depend on C. So, this we can write in a concise way using the don’t care
notation.

Similarly, if A and C are 1; B is don’t care or B and C are 1; A is don’t care; then also
carry will be 1. But on the other cases at least two of the inputs are 0; A B is 0 or A C is 0
or B C is 0; other is don’t care; then carry will be 0. So, you see; if we use don’t care then
instead of the eight rows of the truth table; here we require only six, so our specification
may be shorter, right.
(Refer Slide Time: 18:08)

Now, let us move on to structural specification; now let us structural specification as I said
that; it actually specifies how some modules are interconnected. So, when we say that I
am defining something in a structural way; which means I will have to specify the modules
and I will also have to tell how their actual interconnected, ok. Let us see an example on
this. So, earlier we mentioned that; this kind of structural representation is also called the
netlist. And netlist can be specified at various levels at a very high functional level, gate
level, transistor level and so on.

(Refer Slide Time: 18:58)

This will see later slowly. So, structural level; levels of abstraction is also we talked about
earlier I mention gate level, transistor level or can be hybrid design also.

Some of the blocks can be the gate levels, some of the blocks can be at higher level, ok.
So, as you move down; more and more details I revealed. Like a netlist; which is at a
functional level; multiplexers, decoders, adders their number of blocks will be less. So, as
you move down to the gate level netlist equivalent netlist, number of gates will be much
larger. As you move down again to a transistor level netlist; number of transistor shall be
even larger. So, as you move down; your size of the netlist will be increasing gradually.
Let us take an example to illustrate structural design.

(Refer Slide Time: 19:53)

Now, this is a circuit which you must be familiar with; this is a 4-bit ripple carry adder.
So, what we have done? Just to recall. So, 4-bit ripple carry adder consists of 4 full adders.
So, I want to add two numbers A0, A1, A2, A3 and B0, B1, B2, B3; they are all 4 bit
numbers. So, I feed the corresponding bits to the 4 full adders and C0 is my carry in. The
carry out from the first full adder will be going as carry into the next carry out from here
you will go to the carry in of the next; similarly, here and C4 will be the final carry out
and S0, S1, S2, S3; will be the final sum.

So, if you look inside the full adders; where just now sometime back we saw, the
behavioral specification of a full adder; we saw that there is a sum part, there is a carry
part, there will be one circuit which will be computing the sum; there can be another circuit
disjoint or sheared may be which will compute the carry. So, each full adder we will consist
of a sum circuit and a carry circuit.

(Refer Slide Time: 21:13)

So, conceptually speaking we show it like this. So, as if we have a 4-bit adder; we call it
as a add4, 4-bit adder. 4-bit adder consists of 4 full adders add add add, this are full adder.
Each full adder consists of a carry circuit and a sum circuit; carry circuit, sum circuit. So,
this is how we can describe a circuit in a hierarchical way and also structural way. Like
every adder will be a combination of carry and sum and this 4-bit adder will be a
combination of 4 full adders. Now, this carry and sum, we already know these are the
expressions, ok. So, let us see in Verilog how we can do this.
(Refer Slide Time: 22:03)

So, here I am showing the top level module of a 4-bit carry look ahead adder. So, here the
parameters are specified here; well here I am not going into the detail because all these
details we shall be explaining again later. I am just showing you; how this Verilog code
looks like. Just one thing you see here; here I have declared x and y are the inputs and this
x and y input; I have declared as a vector 3 colon 0 means; it is a four-bit number, but the
bits are number from the most significant side, 3, 2, 1, 0; this is the way to specify in
Verilog 3 colon 0.

Carry-in is a single carry in; similarly output sum is also 4 bit; 3 to 0. See; we here let us
show here I mean say we have an adder; we have also defined a full adder; add is a full
adder. Full adder has parameters carry-out, sum and the three inputs. So, you see here in
the 4-bit ripple carry adder; I have made four copies of this full adder, this is called
instantiation.

Well in a C program; when you call a function. So, the control goes to the function; the
function gets executed and again we come back. But in terms of hardware; if I call a full
adder four times it means I am using four copies of the full adder, this is called
instantiation. So, here four copies of the full adder will be instantiated and I am giving
different names B0, B1, B2, B3 to the four copies and these parameters the way I have
given the name; this defines the interconnection.
Like here for example, for B1 the carry-out Cy_out 0 this will be Cy_out 0. So, this will
be connected to this Cy_out 2; Cy_out 1 will means for B0, the carry-out will be connected
to the carry-in of the next, for B1 the carry-out will be connected to the carry-in of the
next, for B2 the carry-out will be connected to a carry-in of the next and so on because this
is your carry-in the last parameter, right. And here this is a hierarchy design the full adder
also we have defined in a structural way, we have put a sum and a carry. Sum is a module,
carry is a module, we have instantiated them.

(Refer Slide Time: 24:58)

And sum and carry similarly, can be described like this. So, I have defined this in a
structural way; not in a behavioral way you see, sum, this A, B, C in the inputs; sum is the
output and t is a temporary wire.
(Refer Slide Time: 25:27)

This XOR is a gate; what does it t, a, b means? t, a, b means the first one is the output
second two are the inputs; which means that I have an XOR gate for the output is t and the
inputs are A and B, the first line indicates this. Then next line indicates; there is another
XOR sum, sum is the output, inputs as t and Cy_in. So, t is there this is another XOR gate,
this is another input Cy_in and you generate sum. So, you actually specify this circuit; this
is structural because you have specified two gates, XOR gates and how they are
interconnected, right. So, this is a structural description of a sum.

Now, these gates XOR or for carry, this AND, OR these gates are already there as a part
of the Verilog language. So, this we shall be studying slowly. So, I have just shown you
example here just to show you how a Verilog module looks like. So, in the carry block in
a similar way; we need four gates g1, g2, g3, this will do a AND of AB, AND of AC and
AND of BC and the outputs are t1, t2, t3 and finally, you do a OR of t1; t2; t3 and out.

And you see the number of inputs to the gates you can vary like in the last case, the first
one will be the output and the remaining three will be the inputs. So, this will be
automatically taken like this, right.
(Refer Slide Time: 27:03)

Now talking about the physical representation which is the lowest level; here as I said that
when you finally, fabricate the chips; you define a large number of various polygonal
shapes; for the different layers of fabrication, ok.

So, these are this specification of so-called photo masks that are required in the fabrication
process. Now this 4-bit adder is the way we look at it; from the function or the structural
point of view, but from the physical point of view there will be a large number of rectangles
or polygons.

(Refer Slide Time: 27:48)

So, this also can be specified in Verilog; I am just showing you an example this is not the
complete description, just a partial description for the adder. Like you can actually define
some coordinates 0, 35 is a coordinate; this is an aluminum wire of width one unit, this is
the poly silicon wire of width 2 units and so on. So, in this way you can define various
wires of different metals or materials, you can specify the widths basically their rectangular
shapes, right.

Rectangles, there will be a large number of such rectangles will define you such
specification. So, I am just showing you these primitives are also means available in
Verilog. So, when you go down to the layout level; the same Verilog language can be used
to specify your layout, ok. This is what I meant by saying is that you have a hardware
description language and as the process of synthesis continues you transform one version
of Verilog to another version of Verilog, that another version of Verilog to another define
version of Verilog in that way you proceed and at the final step you get a description which
is your final layout description, ok.

(Refer Slide Time: 29:09)

So, just a quick look at the digital IC design flow once more; starting from the
specification, you design entry or this may be your specification in your Verilog or VHDL;
logic synthesis and there are some steps where you are actually going for the physical
design; this is called physical design. You go for partitioning, floor planning, placement
routing steps like this.
And in the first steps; you go for design entry, logic synthesis, partitioning. This steps are
typically called frontend design or logical design and these are called physical design or
backend design. And there is some feedback connection also because at some step; you
may find that it is not working properly to do simulation, you may have to go back and
make some changes.

Like here also you can do some circuit extraction and simulation; you say that your delay
is not coming proper, you may have to go back and make some changes. So, just a very
rough view of the whole process of design; frontend design and backend design; this entire
process has to be traversed by a designer to actually design a circuit in terms of the final
layout description, starting from the behavior.

So, with this we come to the end of the second lecture. Well, in this lecture we have
basically talked about design representations; the three ways you can visualize a design
and we have seen some examples in Verilog; how Verilog can be used to capture the design
at the different levels of abstraction; different views, behavioral structural and physical.

Thank you.