TLC1542C, TLC1542I, TLC1542M, TLC1542Q, TLC1543C, TLC1543I, TLC1543Q 10-Bit Analog-To-Digital Converters With Serial Control and 11 Analog Inputs

TLC1542C, TLC1542I, TLC1542M, TLC1542Q, TLC1543C, TLC1543I, TLC1543Q
10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH

SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS052E – MARCH 1992 – OCTOBER 1998
D 10-Bit Resolution A/D Converter DB, DW, J, OR N PACKAGE

D 11 Analog Input Channels (TOP VIEW)
D Three Built-In Self-Test Modes

D Inherent Sample-and-Hold Function
A0
A1
1
2
20
19
VCC
EOC
D Total Unadjusted Error . . . ± 1 LSB Max A2 3 18 I/O CLOCK
D On-Chip System Clock A3 4 17 ADDRESS
D End-of-Conversion (EOC) Output A4 5 16 DATA OUT
D Terminal Compatible With TLC542 A5 6 15 CS
A6 REF +
D
7 14
CMOS Technology
A7 8 13 REF –
A8 9 12 A10
description
GND 10 11 A9
The TLC1542C, TLC1542I, TLC1542M, TLC1542Q,
TLC1543C, TLC1543I, and TLC1543Q are CMOS FK OR FN PACKAGE
10-bit switched-capacitor successive-approximation (TOP VIEW)
analog-to-digital converters. These devices have three
EOC
VCC
A2
A1
A0
inputs and a 3-state output [chip select (CS),
input-output clock (I/O CLOCK), address input
(ADDRESS), and data output (DATA OUT)] that 3 2 1 20 19
A3 4 18 I/O CLOCK
provide a direct 4-wire interface to the serial port of a A4 5 17 ADDRESS
host processor. These devices allow high-speed data A5 6 16 DATA OUT
transfers from the host. A6 7 15 CS
In addition to a high-speed A /D converter and versatile A7 8 14 REF +
9 10 11 12 13
control capability, these devices have an on-chip
14-channel multiplexer that can select any one of 11
A10
A8
A9
REF –
GND
analog inputs or any one of three internal self-test
voltages. The sample-and-hold function is automatic.
At the end of A /D conversion, the end-of-conversion
(EOC) output goes high to indicate that conversion is
complete. The converter incorporated in the devices
features differential high-impedance reference inputs
that facilitate ratiometric conversion, scaling, and
isolation of analog circuitry from logic and supply noise.
A switched-capacitor design allows low-error conver-
sion over the full operating free-air temperature range.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Copyright  1998, Texas Instruments Incorporated
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

AVAILABLE OPTIONS
PACKAGE
TA SMALL
SMALL OUTLINE CHIP CARRIER PLASTIC DIP CHIP CARRIER CERAMIC DIP
OUTLINE
(DW) (FN) (N) (FK) (J)
(DB)
TLC1542CDW TLC1542CFN TLC1542CN
0°C to 70°C
TLC1543CDB TLC1543CDW TLC1543CFN TLC1543CN
TLC1542IDW TLC1542IFN TLC1542IN
– 40°C to 85°C
TLC1543IDB TLC1543IDW TLC1543IFN TLC1543IN
TLC1542QDB TLC1542QDW TLC1542QFN TLC1542QN
– 40°C to 125°C
TLC1543QDB TLC1543QDW TLC1543QFN TLC1543QN
– 55°C to 125°C TLC1542MFK TLC1542MJ
functional block diagram

REF+ REF –
14 13
1
A0 10-Bit
2 Sample and
A1 Analog-to-Digital
3 Hold Converter
A2
4 (switched capacitors)
A3
5
A4
6 14-Channel 10
A5
7 Analog
A6
8 Multiplexer
A7 Output 10 10-to-1 Data
9 16 DATA
A8 Data Selector and
11 Register Driver OUT
A9 4 Input Address
12 Register
A10
4
3
System
Clock,
Self-Test Control Logic,
Reference 19
and I/O EOC
Counters
17
ADDRESS
18
I/O CLOCK
15
CS
typical equivalent inputs
INPUT CIRCUIT IMPEDANCE DURING SAMPLING MODE INPUT CIRCUIT IMPEDANCE DURING HOLD MODE
1 kΩ TYP
A0 – A10 A0 – A10
Ci = 60 pF TYP
(equivalent input 5 MΩ TYP
capacitance)
2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Terminal Functions
TERMINAL
I/O DESCRIPTION
NAME NO.
ADDRESS 17 I Serial address input. A 4-bit serial address selects the desired analog input or test voltage that is to
be converted next. The address data is presented with the MSB first and shifts in on the first four rising
edges of I/O CLOCK. After the four address bits have been read into the address register, this input
is ignored for the remainder of the current conversion period.
A0 – A10 1 – 9, 11, 12 I Analog signal inputs. The 11 analog inputs are applied to these terminals and are internally multiplexed.
The driving source impedance should be less than or equal to 1 kΩ.
CS 15 I Chip select. A high-to-low transition on this input resets the internal counters and controls and enables
DATA OUT, ADDRESS, and I/O CLOCK within a maximum of a setup time plus two falling edges of
the internal system clock. A low-to-high transition disables ADDRESS and I/O CLOCK within a setup
time plus two falling edges of the internal system clock.
DATA OUT 16 O The 3-state serial output for the A/D conversion result. This output is in the high-impedance state when
CS is high and active when CS is low. With a valid chip select, DATA OUT is removed from the
high-impedance state and is driven to the logic level corresponding to the MSB value of the previous
conversion result. The next falling edge of I/O CLOCK drives this output to the logic level corresponding
to the next most significant bit, and the remaining bits shift out in order with the LSB appearing on the
ninth falling edge of I/O CLOCK. On the tenth falling edge of I/O CLOCK, DATA OUT is driven to a low
logic level so that serial interface data transfers of more than ten clocks produce zeroes as the unused
LSBs.
EOC 19 O End of conversion. This output goes from a high to a low logic level on the trailing edge of the tenth I/O
CLOCK and remains low until the conversion is complete and data are ready for transfer.
GND 10 I The ground return terminal for the internal circuitry. Unless otherwise noted, all voltage measurements
are with respect to this terminal.
I/O CLOCK 18 I Input/output clock. This terminal receives the serial I/O CLOCK input and performs the following four
functions:
1) It clocks the four input address bits into the address register on the first four rising edges of the I/O
CLOCK with the multiplex address available after the fourth rising edge.
2) On the fourth falling edge of I/O CLOCK, the analog input voltage on the selected multiplex input
begins charging the capacitor array and continues to do so until the tenth falling edge of
I/O CLOCK.
3) It shifts the nine remaining bits of the previous conversion data out on DATA OUT.
4) It transfers control of the conversion to the internal state controller on the falling edge of the tenth
clock.
REF + 14 I The upper reference voltage value (nominally VCC) is applied to this terminal. The maximum input
voltage range is determined by the difference between the voltage applied to this terminal and the
voltage applied to the REF – terminal.
REF – 13 I The lower reference voltage value (nominally ground) is applied to this terminal.
VCC 20 I Positive supply voltage
detailed description
With chip select (CS) inactive (high), the ADDRESS and I/O CLOCK inputs are initially disabled and DATA OUT
is in the high-impedance state. When the serial interface takes CS active (low), the conversion sequence begins
with the enabling of I/O CLOCK and ADDRESS and the removal of DATA OUT from the high-impedance state.
The serial interface then provides the 4-bit channel address to ADDRESS and the I/O CLOCK sequence to I/O
CLOCK. During this transfer, the serial interface also receives the previous conversion result from DATA OUT.
I/O CLOCK receives an input sequence that is between 10 and 16 clocks long from the host serial interface.
The first four I/O clocks load the address register with the 4-bit address on ADDRESS, selecting the desired
analog channel, and the next six clocks providing the control timing for sampling the analog input.

detailed description (continued)

There are six basic serial-interface timing modes that can be used with the device. These modes are determined
by the speed of I/O CLOCK and the operation of CS as shown in Table 1. These modes are (1) a fast mode with
a 10-clock transfer and CS inactive (high) between conversion cycles, (2) a fast mode with a 10-clock transfer
and CS active (low) continuously, (3) a fast mode with an 11- to 16-clock transfer and CS inactive (high) between
conversion cycles, (4) a fast mode with a 16-clock transfer and CS active (low) continuously, (5) a slow mode
with an 11- to 16-clock transfer and CS inactive (high) between conversion cycles, and (6) a slow mode with
a 16-clock transfer and CS active (low) continuously.
The MSB of the previous conversion appears at DATA OUT on the falling edge of CS in mode 1, mode 3, and
mode 5, on the rising edge of EOC in mode 2 and mode 4, and following the sixteenth clock falling edge in
mode 6. The remaining nine bits are shifted out on the next nine falling edges of I/O CLOCK. Ten bits of data
are transmitted to the host-serial interface through DATA OUT. The number of serial clock pulses used also
depends on the mode of operation, but a minimum of ten clock pulses is required for conversion to begin. On
the tenth clock falling edge, the EOC output goes low and returns to the high logic level when conversion is
complete and the result can be read by the host. Also, on the tenth clock falling edge, the internal logic takes
DATA OUT low to ensure that the remaining bit values are zero when the I/O CLOCK transfer is more than ten
clocks long.
Table 1 lists the operational modes with respect to the state of CS, the number of I/O serial transfer clocks that
can be used, and the timing edge on which the MSB of the previous conversion appears at the output.
Table 1. Mode Operation

NO. OF TIMING
MODES CS MSB AT DATA OUT †
I/O CLOCKS DIAGRAM
Mode 1 High between conversion cycles 10 CS falling edge Figure 9
Mode 2 Low continuously 10 EOC rising edge Figure 10
Fast Modes
Mode 3 High between conversion cycles 11 to 16‡ CS falling edge Figure 11
Mode 4 Low continuously 16‡ EOC rising edge Figure 12
Mode 5 High between conversion cycles 11 to 16‡ CS falling edge Figure 13
Slow Modes
Mode 6 Low continuously 16‡ 16th clock falling edge Figure 14
† These edges also initiate serial-interface communication.
‡ No more than 16 clocks should be used.
fast modes
The device is in a fast mode when the serial I/O CLOCK data transfer is completed before the conversion is
completed. With a 10-clock serial transfer, the device can only run in a fast mode since a conversion does not
begin until the falling edge of the tenth I/O CLOCK.
mode 1: fast mode, CS inactive (high) between conversion cycles, 10-clock transfer
In this mode, CS is inactive (high) between serial I/O CLOCK transfers and each transfer is ten clocks long. The
falling edge of CS begins the sequence by removing DATA OUT from the high-impedance state. The rising edge
of CS ends the sequence by returning DATA OUT to the high-impedance state within the specified delay time.
Also, the rising edge of CS disables the I/O CLOCK and ADDRESS terminals within a setup time plus two falling
edges of the internal system clock.
mode 2: fast mode, CS active (low) continuously, 10-clock transfer
In this mode, CS is active (low) between serial I/O CLOCK transfers and each transfer is ten clocks long. After
the initial conversion cycle, CS is held active (low) for subsequent conversions; the rising edge of EOC then
begins each sequence by removing DATA OUT from the low logic level, allowing the MSB of the previous
conversion to appear immediately on this output.

mode 3: fast mode, CS inactive (high) between conversion cycles, 11- to 16-clock transfer
In this mode, CS is inactive (high) between serial I/O CLOCK transfers, and each transfer can be 11 to 16 clocks
long. The falling edge of CS begins the sequence by removing DATA OUT from the high-impedance state. The
rising edge of CS ends the sequence by returning DATA OUT to the high-impedance state within the specified
delay time. Also, the rising edge of CS disables the I/O CLOCK and ADDRESS terminals within a setup time
plus two falling edges of the internal system clock.
mode 4: fast mode, CS active (low) continuously, 16-clock transfer
In this mode, CS is active (low) between serial I/O CLOCK transfers and each transfer must be exactly 16 clocks
long. After the initial conversion cycle, CS is held active (low) for subsequent conversions; the rising edge of
EOC then begins each sequence by removing DATA OUT from the low logic level, allowing the MSB of the
previous conversion to appear immediately on this output.
slow modes
In a slow mode, the conversion is completed before the serial I/O CLOCK data transfer is completed. A slow
mode requires a minimum 11-clock transfer into I/O CLOCK, and the rising edge of the eleventh clock must
occur before the conversion period is complete; otherwise, the device loses synchronization with the host-serial
interface and CS has to be toggled to initialize the system. The eleventh rising edge of the I/O CLOCK must
occur within 9.5 µs after the tenth I/O clock falling edge.
mode 5: slow mode, CS inactive (high) between conversion cycles, 11- to 16-clock transfer
In this mode, CS is inactive (high) between serial I/O CLOCK transfers and each transfer can be 11 to 16 clocks
long. The falling edge of CS begins the sequence by removing DATA OUT from the high-impedance state. The
rising edge of CS ends the sequence by returning DATA OUT to the high-impedance state within the specified
delay time. Also, the rising edge of CS disables the I/O CLOCK and ADDRESS terminals within a setup time
plus two falling edges of the internal system clock.
mode 6: slow mode, CS active (low) continuously, 16-clock transfer
In this mode, CS is active (low) between serial I/O CLOCK transfers and each transfer must be exactly 16 clocks
long. After the initial conversion cycle, CS is held active (low) for subsequent conversions. The falling edge of
the sixteenth I/O CLOCK then begins each sequence by removing DATA OUT from the low state, allowing the
MSB of the previous conversion to appear immediately at DATA OUT. The device is then ready for the next
16-clock transfer initiated by the serial interface.
address bits
The 4-bit analog channel-select address for the next conversion cycle is presented to the ADDRESS terminal
(MSB first) and is clocked into the address register on the first four leading edges of I/O CLOCK. This address
selects one of 14 inputs (11 analog inputs or three internal test inputs).
analog inputs and test modes
The 11 analog inputs and the three internal test inputs are selected by the 14-channel multiplexer according
to the input address as shown in Tables 2 and 3. The input multiplexer is a break-before-make type to reduce
input-to-input noise injection resulting from channel switching.
Sampling of the analog input starts on the falling edge of the fourth I/O CLOCK, and sampling continues for six
I/O CLOCK periods. The sample is held on the falling edge of the tenth I/O CLOCK. The three test inputs are
applied to the multiplexer, sampled, and converted in the same manner as the external analog inputs.

analog inputs and test modes (continued)
Table 2. Analog-Channel-Select Address

VALUE SHIFTED INTO
ANALOG INPUT ADDRESS INPUT
SELECTED
BINARY HEX
A0 0000 0
A1 0001 1
A2 0010 2
A3 0011 3
A4 0100 4
A5 0101 5
A6 0110 6
A7 0111 7
A8 1000 8
A9 1001 9
A10 1010 A
Table 3. Test-Mode-Select Address

INTERNAL VALUE SHIFTED INTO
SELF-TEST ADDRESS INPUT
VOLTAGE OUTPUT RESULT (HEX)‡
SELECTED† BINARY HEX
Vref+ – Vref–
1011 B 200
2
Vref– 1100 C 000
Vref+ 1101 D 3FF
† Vref+ is the voltage applied to the REF+ input, and Vref– is the voltage applied to the REF–
input.
‡ The output results shown are the ideal values and vary with the reference stability and
with internal offsets.
converter and analog input

The CMOS threshold detector in the successive-approximation conversion system determines each bit by
examining the charge on a series of binary-weighted capacitors (see Figure 1). In the first phase of the
conversion process, the analog input is sampled by closing the SC switch and all ST switches simultaneously.
This action charges all the capacitors to the input voltage.
In the next phase of the conversion process, all ST and SC switches are opened and the threshold detector
begins identifying bits by identifying the charge (voltage) on each capacitor relative to the reference (REF –)
voltage. In the switching sequence, ten capacitors are examined separately until all ten bits are identified and
then the charge-convert sequence is repeated. In the first step of the conversion phase, the threshold detector
looks at the first capacitor (weight = 512). Node 512 of this capacitor is switched to the REF+ voltage, and the
equivalent nodes of all the other capacitors on the ladder are switched to REF –. If the voltage at the summing
node is greater than the trip point of the threshold detector (approximately one-half VCC ), a 0 bit is placed in
the output register and the 512-weight capacitor is switched to REF –. If the voltage at the summing node is less
than the trip point of the threshold detector, a 1 bit is placed in the register and the 512-weight capacitor remains
connected to REF + through the remainder of the successive-approximation process. The process is repeated
for the 256-weight capacitor, the 128-weight capacitor, and so forth down the line until all bits are counted.

converter and analog input (continued)

With each step of the successive-approximation process, the initial charge is redistributed among the
capacitors. The conversion process relies on charge redistribution to count and weigh the bits from MSB to LSB.
SC
Threshold
Detector
To Output
512 256 128 16 8 4 2 1 1 Latches
Node 512 REF+ REF+ REF+ REF+ REF+ REF+ REF+
REF – REF – REF – REF – REF – REF – REF – REF – REF –

ST ST ST ST ST ST ST ST ST
VI
Figure 1. Simplified Model of the Successive-Approximation System

chip-select operation
The trailing edge of CS starts all modes of operation, and CS can abort a conversion sequence in any mode.
A high-to-low transition on CS within the specified time during an ongoing cycle aborts the cycle, and the device
returns to the initial state (the contents of the output data register remain at the previous conversion result).
Exercise care to prevent CS from being taken low close to completion of conversion because the output data
can be corrupted.
reference voltage inputs
There are two reference inputs used with the device: REF + and REF –. These voltage values establish the upper
and lower limits of the analog input to produce a full-scale and zero reading respectively. The values of REF +,
REF–, and the analog input should not exceed the positive supply or be lower than GND consistent with the
specified absolute maximum ratings. The digital output is at full scale when the input signal is equal to or higher
than REF + and at zero when the input signal is equal to or lower than REF –.

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 6.5 V
Input voltage range, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to VCC + 0.3 V
Output voltage range, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to VCC + 0.3 V
Positive reference voltage, Vref+ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VCC + 0.1 V
Negative reference voltage, Vref– . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.1 V
Peak input current (any input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 mA
Peak total input current (all inputs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 30 mA
Operating free-air temperature range, TA: TLC1542C, TLC1543C . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
TLC1542I, TLC1543I . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 85°C
TLC1542Q, TLC1543Q . . . . . . . . . . . . . . . . . . . . . – 40°C to 125°C
TLC1542M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 125°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from the case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to digital ground with REF – and GND wired together (unless otherwise noted).
recommended operating conditions

MIN NOM MAX UNIT
Supply voltage, VCC 4.5 5 5.5 V
Positive reference voltage, Vref + (see Note 2) VCC V
Negative reference voltage, Vref – (see Note 2) 0 V
Differential reference voltage, Vref + – Vref – (see Note 2) 2.5 VCC VCC + 0.2 V
Analog input voltage (see Note 2) 0 VCC V
High-level control input voltage, VIH VCC = 4.5 V to 5.5 V 2 V
Low-level control input voltage, VIL VCC = 4.5 V to 5.5 V 0.8 V
Setup time, address bits at data input before I/O CLOCK↑, tsu(A) (see Figure 4) 100 ns
Hold time, address bits after I/O CLOCK↑, th(A) (see Figure 4) 0 ns
Hold time, CS low after last I/O CLOCK↓, th(CS) (see Figure 5) 0 ns
Setup time, CS low before clocking in first address bit, tsu(CS) (see Note 3 and Figure 5) 1.425 µs
Clock frequency at I/O CLOCK (see Note 4) 0 2.1 MHz
Pulse duration, I/O CLOCK high, twH(I/O) 190 ns
Pulse duration, I/O CLOCK low, twL(I/O) 190 ns
Transition time, I/O CLOCK, tt(I/O) (see Note 5 and Figure 6) 1 µs
Transition time, ADDRESS and CS, tt(CS) 10 µs
TLC1542C, TLC1543C 0 70
TLC1542I, TLC1543I – 40 85
Operating free-air
free air temperature,
temperature TA °C
TLC1542Q, TLC1543Q – 40 125
TLC1542M – 55 125
NOTES: 2. Analog input voltages greater than that applied to REF+ convert as all ones (1111111111), while input voltages less than that applied
to REF– convert as all zeros (0000000000). The device is functional with reference voltages down to 1 V (Vref + – Vref – ); however,
the electrical specifications are no longer applicable.
3. To minimize errors caused by noise at CS, the internal circuitry waits for a setup time plus two falling edges of the internal system
clock after CS↓ before responding to control input signals. Therefore, no attempt should be made to clock in an address until the
minimum CS setup time has elapsed.
4. For 11- to 16-bit transfers, after the tenth I/O CLOCK falling edge (≤ 2 V) at least 1 I/O CLOCK rising edge (≥ 2 V) must occur within
9.5 µs.
5. This is the time required for the clock input signal to fall from VIHmin to VILmax or to rise from VILmax to VIHmin. In the vicinity of
normal room temperature, the devices function with input clock transition time as slow as 1 µs for remote data-acquisition
applications where the sensor and the A/D converter are placed several feet away from the controlling microprocessor.

electrical characteristics over recommended operating free-air temperature range,

VCC = Vref+ = 4.5 V to 5.5 V, I/O CLOCK frequency = 2.1 MHz (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP† MAX UNIT
VCC = 4.5 V, IOH = –1.6 mA 2.4
VOH High level output voltage
High-level V
VCC = 4.5 V to 5.5 V, IOH = – 20 µA VCC – 0.1
VCC = 4.5 V, IOL = 1.6 mA 0.4
VOL Low level output voltage
Low-level V
VCC = 4.5 V to 5.5 V, IOL = 20 µA 0.1
Off-state VO = VCC, CS at VCC 10
IOZ (high impedance state)
(high-impedance-state) µA
output current VO = 0, CS at VCC – 10
IIH High-level input current VI = VCC 0.005 2.5 µA
IIL Low-level input current VI = 0 – 0.005 – 2.5 µA
ICC Operating supply current CS at 0 V 0.8 2.5 mA
Selected channel leakage Selected channel at VCC, Unselected channel at 0 V 1
current TLC1542/TLC1543 µA
C, I, or Q Selected channel at 0 V, Unselected channel at VCC –1
Selected channel at VCC, Unselected channel at 0 V,
1
TA = 25°C
Selected channel leakage Selected channel at 0 V, Unselected channel at VCC,
TA = 25°C
–1 µA
current TLC1542M
Selected channel at VCC, Unselected channel at 0 V 2.5
Selected channel at 0 V, Unselected channel at VCC – 2.5
Maximum static analog
Vref + = VCC, Vref – = GND 10 µA
reference current into REF +
Input Analog inputs 7
Ci pF
capacitance Control inputs 5
† All typical values are at VCC = 5 V, TA = 25°C.

operating characteristics over recommended operating free-air temperature range,

VCC = Vref+ = 4.5 V to 5.5 V, I/O CLOCK frequency = 2.1 MHz (unless otherwise noted)
TEST CONDITIONS MIN TYP† MAX UNIT
TLC1542C, I, or Q ± 0.5 LSB
EL Linearity error (see Note 6) TLC1543C, I, or Q ±1 LSB
TLC1542M ±1 LSB
TLC1542C, I, or Q See Note 2 ±1 LSB
EZS Zero-scale error (see Note 7) TLC1543C, I, or Q See Note 2 ±1 LSB
TLC1542M See Note 2 ±1 LSB
TLC1542C, I, or Q See Note 2 ±1 LSB
EFS Full-scale error (see Note 7) TLC1543C, I, or Q See Note 2 ±1 LSB
TLC1542M See Note 2 ±1 LSB
TLC1542C, I, or Q ±1 LSB
Total unadjusted error (see Note 8) TLC1543C, I, or Q ±1 LSB
TLC1542M ±1 LSB
ADDRESS = 1011 512
Self-test output code (see Table 3 and Note 9) ADDRESS = 1100 0
ADDRESS = 1101 1023
tconv Conversion time See timing diagrams 21 µs
21
See timing diagrams +10 I/O
tc Total cycle time (access, sample, and conversion) CLOCK µs
and Note 10
periods
See timing diagrams I/O

tacq Channel acquisition time (sample) 6 CLOCK
and Note 10 periods
tv Valid time, DATA OUT remains valid after I/O CLOCK↓ See Figure 6 10 ns
td(I/O-DATA) Delay time, I/O CLOCK↓ to DATA OUT valid See Figure 6 240 ns
td(I/O-EOC) Delay time, tenth I/O CLOCK↓ to EOC↓ See Figure 7 70 240 ns
td(EOC-DATA) Delay time, EOC↑ to DATA OUT (MSB) See Figure 8 100 ns
† All typical values are at TA = 25°C.
NOTES: 2. Analog input voltages greater than that applied to REF + convert as all ones (1111111111), while input voltages less than that applied
to REF – convert as all zeros (0000000000). The device is functional with reference voltages down to 1 V (Vref + – Vref – ); however,
the electrical specifications are no longer applicable.
6. Linearity error is the maximum deviation from the best straight line through the A/D transfer characteristics.
7. Zero-scale error is the difference between 0000000000 and the converted output for zero input voltage; full-scale error is the
difference between 1111111111 and the converted output for full-scale input voltage.
8. Total unadjusted error comprises linearity, zero-scale, and full-scale errors.
9. Both the input address and the output codes are expressed in positive logic.
10. I/O CLOCK period = 1/(I/O CLOCK frequency) (see Figure 6)

operating characteristics over recommended operating free-air temperature range,

VCC = Vref+ = 4.5 V to 5.5 V, I/O CLOCK frequency = 2.1 MHz (unless otherwise noted) (continued)
TEST CONDITIONS MIN TYP† MAX UNIT
tPZH, tPZL Enable time, CS↓ to DATA OUT (MSB driven) See Figure 3 1.3 µs
tPHZ, tPLZ Disable time, CS↑ to DATA OUT (high impedance) See Figure 3 150 ns
tr(EOC) Rise time, EOC See Figure 8 300 ns
tf(EOC) Fall time, EOC See Figure 7 300 ns
tr(DATA) Rise time, data bus See Figure 6 300 ns
tf(DATA) Fall time, data bus See Figure 6 300 ns
Delay time, tenth I/O CLOCK↓ to CS↓ to abort conversion
td(I/O-CS) 9 µs
(see Note 11)
† All typical values are at TA = 25°C.
NOTE 11. Any transitions of CS are recognized as valid only if the level is maintained for a setup time plus two falling edges of the internal clock
(1.425 µs) after the transition.
PARAMETER MEASUREMENT INFORMATION

Test Point VCC Test Point VCC
RL = 2.18 kΩ RL = 2.18 kΩ
EOC DATA OUT
CL = 50 pF 12 kΩ CL = 100 pF 12 kΩ
Figure 2. Load Circuits
Address
Valid
2V 2V
CS ADDRESS
0.8 V 0.8 V
tPZH, tPZL th(A)

tPHZ, tPLZ tsu(A)
2.4 V 90%
DATA I/O CLOCK
OUT 0.4 V 10% 0.8 V
Figure 3. DATA OUT Enable and Disable Figure 4. ADDRESS Setup and Hold TIme
Voltage Waveforms Voltage Waveforms

2V
CS
0.8 V
tsu(CS)
th(CS)
I/O CLOCK
First Last
0.8 V 0.8 V
Clock Clock
Figure 5. I/O CLOCK Setup and Hold Time Voltage Waveforms
tt(I/O) tt(I/O)
2V 2V
I/O CLOCK
0.8 V
0.8 V 0.8 V
I/O CLOCK Period
td(I/O-DATA)
tv
2.4 V 2.4 V
DATA OUT
0.4 V 0.4 V
tr(DATA), tf(DATA)
Figure 6. I/O CLOCK and DATA OUT Voltage Waveforms
I/O CLOCK 10th 0.8 V

Clock
td(I/O-EOC)
2.4 V
EOC 0.4 V
tf(EOC)
Figure 7. I/O CLOCK and EOC Voltage Waveforms
tr(EOC)
EOC 2.4 V
0.4 V
td(EOC-DATA)
2.4 V
DATA OUT
0.4 V
Valid MSB
Figure 8. EOC and DATA OUT Voltage Waveforms

timing diagrams
CS
(see Note A)
I/O
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
1 2 3 4 5 6 7 8 9 10 1
CLOCK
Access Cycle B Sample Cycle B
Hi-Z State
DATA
A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 B9
OUT
Previous Conversion Data
ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
MSB LSB
ADDRESS
B3 B2 B1 B0 C3
MSB LSB
EOC
Shift in New Multiplexer Address;

Simultaneously Shift Out Previous
Conversion Value A/D Conversion
Initialize Interval Initialize
NOTE A: To minimize errors caused by noise at CS, the internal circuitry waits for a setup time plus two falling edges of the internal system clock
after CS↓ before responding to control input signals. Therefore, no attempt should be made to clock in an address until the minimum
CS setup time has elapsed.
Figure 9. Timing for 10-Clock Transfer Using CS

timing diagrams (continued)
Must be High on Power Up

CS
(see Note A)
I/O 1 2 3 4 5 6 7 8 9 10 1
CLOCK
DATA
A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Low Level B9
OUT
MSB LSB
ADDRESS
B3 B2 B1 B0 C3
MSB LSB
EOC

NOTE A: To minimize errors caused by noise at CS, the internal circuitry waits for a setup time plus two falling edges of the internal system clock
after CS↓ before responding to control input signals. Therefore, no attempt should be made to clock in an address until the minimum
CS setup time has elapsed.
Figure 10. Timing for 10-Clock Transfer Not Using CS

ÏÏÏ
ÏÏÏ
See Note B
ÏÏÏ
CS
(see Note A)
I/O
ÎÎ
ÎÎ
1 2 3 4 5 6 7 8 9 10 11 16 1
CLOCK
ÎÎÎ
Low
DATA Hi-Z
A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Level B9
OUT
ÎÎÎÎÎ
ÎÎÎ ÎÎÎ ÎÎÎ
ÎÎÎ
MSB LSB
ÎÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ADDRESS
B3 B2 B1 B0 C3
MSB LSB
EOC

Interval
Initialize Initialize
NOTES: A. To minimize errors caused by noise at CS, the internal circuitry waits for a setup time plus two falling edges of the internal system
B. A low-to-high transition of CS disables ADDRESS and the I/O CLOCK within a maximum of a setup time plus two falling edges of
the internal system clock.
Figure 11. Timing for 11- to 16-Clock Transfer Using CS (Serial Transfer Interval Shorter Than Conversion)


Must Be High on Power Up
CS
(see Note A)
I/O 1 2 3 4 5 6 7 8 9 10 14 15 16 1
CLOCK
Access Cycle B Sample Cycle B See Note B
DATA A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Low Level B9

OUT
ÎÎÎÎÎÎÎÎÎ
ÎÎÎ ÎÎÎÎ
MSB LSB
ADDRESS
ÎÎÎÎÎÎÎÎÎ
ÎÎÎ
B3
MSB
B2 B1 B0
LSB
ÎÎÎÎ C3
EOC
A/D Conversion
Interval
Conversion Value
Initialize Initialize
B. The first I/O CLOCK must occur after the rising edge of EOC.
Figure 12. Timing for 16-Clock Transfer Not Using CS (Serial Transfer Interval Shorter Than Conversion)

ÏÏÏ
CS
(see Note A) ÏÏÏ
ÎÎ
I/O
CLOCK
1 2 3
Access Cycle B
4 5 6 7
Sample Cycle B
8 9 10 11
ÎÎ 16
See Note B
1
ÎÎÎ Hi-Z State
ÎÎÎ
DATA Low
A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Level B9
OUT
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
MSB LSB
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ADDRESS
B3 B2 B1 B0 C3
ÏÏÏ
MSB LSB
EOC

ÏÏÏ
B. The 11th rising edge of the I/O CLOCK sequence must occur before the conversion is complete to prevent losing serial interface
synchronization.
Figure 13. Timing for 11- to 16-Clock Transfer Using CS (Serial Transfer Interval Longer Than Conversion)


Must be High on Power Up
CS
(see Note A)
I/O 1 2 3 4 5 6 7 8 9 10 14 15 16 1
CLOCK
Access Cycle B Sample Cycle B See Note B See Note C
DATA A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Low Level B9

OUT
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
MSB LSB
ADDRESS
ÎÎÎÎÎÎÎÎÎÎ
B3
MSB
B2 B1 B0
LSB
ÎÎÎÎ C3
EOC

Initialize Interval
B. The 11th rising edge of the I/O CLOCK sequence must occur before the conversion is complete to prevent losing serial interface
synchronization.
C. The I/O CLOCK sequence is exactly 16 clock pulses long.
Figure 14. Timing for 16-Clock Transfer Not Using CS (Serial Transfer Interval Longer Than Conversion)

APPLICATION INFORMATION
1111111111 1023
See Notes A and B
1111111110 1022
1111111101 1021
VFS
VFT = VFS – 1/2 LSB

Digital Output Code
1000000001 513
Step
1000000000 512
VZT =VZS + 1/2 LSB
0111111111 511
VZS
0000000010 2
0000000001 1
0000000000 0
0.0024
4.9080
0 0.0048 0.0096 2.4528 2.4576 2.4624 4.9056 4.9104 4.9152
VI – Analog Input Voltage – V

NOTES: A. This curve is based on the assumption that Vref + and Vref – have been adjusted so that the voltage at the transition from digital 0
to 1 (VZT) is 0.0024 V and the transition to full scale (VFT) is 4.908 V. 1 LSB = 4.8 mV.
B. The full-scale value (VFS) is the step whose nominal midstep value has the highest absolute value. The zero-scale value (VZS) is
the step whose nominal midstep value equals zero.
Figure 15. Ideal Conversion Characteristics
TLC1542/43
1 15
A0 CS
2 18
A1 I/O CLOCK
3 17
A2 ADDRESS Control
4 Processor
A3 Circuit
5 16
A4 DATA OUT
Analog 6 19
A5 EOC
Inputs 7
A6
8
A7
9 14
A8 5-V DC Regulator
11 REF+
A9 13
12 REF–
A10
GND
10
To Source
Ground
Figure 16. Serial Interface

APPLICATION INFORMATION
simplified analog input analysis

Using the equivalent circuit in Figure 17, the time required to charge the analog input capacitance from 0 to VS
within 1/2 LSB can be derived as follows:
The capacitance charging voltage is given by
– t c /RtCi
(
VC = VS 1– e ) (1)
where
Rt = Rs + ri
The final voltage to 1/2 LSB is given by

VC (1/2 LSB) = VS – (VS /2048) (2)
Equating equation 1 to equation 2 and solving for time tc gives

– t c /RtCi
VS – (VS/2048) = VS 1– e( ) (3)
and
tc (1/2 LSB) = Rt × Ci × ln(2048) (4)
Therefore, with the values given the time for the analog input signal to settle is
tc (1/2 LSB) = (Rs + 1 kΩ) × 60 pF × ln(2048) (5)
This time must be less than the converter sample time shown in the timing diagrams.
Driving Source† TLC1542/3
Rs VI ri
VS VC
1 kΩ MAX
Ci
50 pF MAX
VI = Input Voltage at A0 – A10

VS = External Driving Source Voltage
Rs = Source Resistance
ri = Input Resistance
Ci = Equivalent Input Capacitance
† Driving source requirements:

• Noise and distortion for the source must be equivalent to the
resolution of the converter.
• Rs must be real at the input frequency.
Figure 17. Equivalent Input Circuit Including the Driving Source

MECHANICAL DATA
DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
28 PIN SHOWN
0,38
0,65 0,15 M
0,22
28 15
0,15 NOM
5,60 8,20
5,00 7,40
Gage Plane
1 14 0,25
A 0°– 8° 1,03
0,63
Seating Plane
2,00 MAX 0,05 MIN 0,10
PINS **
14 16 20 24 28 30 38
DIM
A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90
A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30
4040065 / D 02/98
NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150

MECHANICAL DATA
DW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
16 PIN SHOWN
0.050 (1,27) 0.020 (0,51)

0.010 (0,25) M
0.014 (0,35)
16 9
0.419 (10,65)
0.400 (10,15)
0.299 (7,59) 0.010 (0,25) NOM
0.293 (7,45)
Gage Plane
0.010 (0,25)
1 8
0°– 8° 0.050 (1,27)
A 0.016 (0,40)
Seating Plane
0.012 (0,30) 0.004 (0,10)

0.104 (2,65) MAX
0.004 (0,10)
PINS **
16 20 24
DIM
0.410 0.510 0.610

A MAX
(10,41) (12,95) (15,49)
0.400 0.500 0.600

A MIN
(10,16) (12,70) (15,24)
4040000 / D 02/98
NOTES: A. All linear dimensions are in inches (millimeters).

C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
D. Falls within JEDEC MS-013

MECHANICAL DATA
FK (S-CQCC-N**) LEADLESS CERAMIC CHIP CARRIER
28 TERMINAL SHOWN
NO. OF A B
18 17 16 15 14 13 12
TERMINALS
** MIN MAX MIN MAX
0.342 0.358 0.307 0.358

19 11 20
(8,69) (9,09) (7,80) (9,09)
20 10 0.442 0.458 0.406 0.458
28
(11,23) (11,63) (10,31) (11,63)
21 9
B SQ 0.640 0.660 0.495 0.560
22 8 44
(16,26) (16,76) (12,58) (14,22)
A SQ
23 7 0.739 0.761 0.495 0.560
52
(18,78) (19,32) (12,58) (14,22)
24 6
0.938 0.962 0.850 0.858
68
(23,83) (24,43) (21,6) (21,8)
25 5
1.141 1.165 1.047 1.063
84
(28,99) (29,59) (26,6) (27,0)
26 27 28 1 2 3 4
0.020 (0,51) 0.080 (2,03)

0.010 (0,25) 0.064 (1,63)
0.020 (0,51)
0.010 (0,25)
0.055 (1,40)
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.028 (0,71) 0.045 (1,14)

0.022 (0,54) 0.035 (0,89)
0.050 (1,27)
4040140 / D 10/96

C. This package can be hermetically sealed with a metal lid.
D. The terminals are gold plated.
E. Falls within JEDEC MS-004

MECHANICAL DATA
FN (S-PQCC-J**) PLASTIC J-LEADED CHIP CARRIER
20 PIN SHOWN
Seating Plane
0.004 (0,10)
0.180 (4,57) MAX

D
0.120 (3,05)
D1 0.090 (2,29)
0.020 (0,51) MIN
3 1 19
0.032 (0,81)
0.026 (0,66)
4 18
D2 / E2
E E1
D2 / E2
8 14
0.050 (1,27) 0.021 (0,53)

9 13 0.013 (0,33)
0.008 (0,20) NOM 0.007 (0,18) M
NO. OF D/E D1 / E1 D2 / E2
PINS
** MIN MAX MIN MAX MIN MAX
20 0.385 (9,78) 0.395 (10,03) 0.350 (8,89) 0.356 (9,04) 0.141 (3,58) 0.169 (4,29)
28 0.485 (12,32) 0.495 (12,57) 0.450 (11,43) 0.456 (11,58) 0.191 (4,85) 0.219 (5,56)
44 0.685 (17,40) 0.695 (17,65) 0.650 (16,51) 0.656 (16,66) 0.291 (7,39) 0.319 (8,10)
52 0.785 (19,94) 0.795 (20,19) 0.750 (19,05) 0.756 (19,20) 0.341 (8,66) 0.369 (9,37)
68 0.985 (25,02) 0.995 (25,27) 0.950 (24,13) 0.958 (24,33) 0.441 (11,20) 0.469 (11,91)
84 1.185 (30,10) 1.195 (30,35) 1.150 (29,21) 1.158 (29,41) 0.541 (13,74) 0.569 (14,45)
4040005 / B 03/95

C. Falls within JEDEC MS-018

MECHANICAL DATA
J (R-GDIP-T**) CERAMIC DUAL-IN-LINE PACKAGE
14 PIN SHOWN
PINS **
14 16 18 20
DIM
0.310 0.310 0.310 0.310

A MAX
(7,87) (7,87) (7,87) (7,87)
B
0.290 0.290 0.290 0.290
14 8 A MIN
(7,37) (7,37) (7,37) (7,37)
0.785 0.785 0.910 0.975

B MAX
(19,94) (19,94) (23,10) (24,77)
C
0.755 0.755 0.930
B MIN
(19,18) (19,18) (23,62)
0.300 0.300 0.300 0.300

C MAX
1 7 (7,62) (7,62) (7,62) (7,62)
0.065 (1,65)
0.245 0.245 0.245 0.245
0.045 (1,14) C MIN
(6,22) (6,22) (6,22) (6,22)
0.100 (2,54)
0.020 (0,51) MIN A
0.070 (1,78)
0.200 (5,08) MAX

Seating Plane
0.130 (3,30) MIN
0.100 (2,54)
0°–15°
0.023 (0,58)
0.015 (0,38) 0.014 (0,36)
0.008 (0,20)
4040083/D 08/98

C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Index point is provided on cap for terminal identification only on press ceramic glass frit seal only.
E. Falls within MIL STD 1835 GDIP1-T14, GDIP1-T16, GDIP1-T18, GDIP1-T20, and GDIP1-T22.

MECHANICAL DATA
N (R-PDIP-T**) PLASTIC DUAL-IN-LINE PACKAGE
16 PIN SHOWN
PINS **
14 16 18 20
DIM
0.775 0.775 0.920 0.975

A A MAX
(19,69) (19,69) (23.37) (24,77)
16 9 0.745 0.745 0.850 0.940

A MIN
(18,92) (18,92) (21.59) (23,88)
0.260 (6,60)
0.240 (6,10)
1 8
0.070 (1,78) MAX
0.310 (7,87)
0.035 (0,89) MAX 0.020 (0,51) MIN
0.290 (7,37)
0.200 (5,08) MAX
Seating Plane
0.125 (3,18) MIN
0.100 (2,54)
0°– 15°
0.021 (0,53)
0.010 (0,25) M 0.010 (0,25) NOM
0.015 (0,38)
14/18 PIN ONLY
4040049/C 08/95

C. Falls within JEDEC MS-001 (20 pin package is shorter then MS-001.)

IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF

DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright  1998, Texas Instruments Incorporated

TLC1542C, TLC1542I, TLC1542M, TLC1542Q, TLC1543C, TLC1543I, TLC1543Q 10-Bit Analog-To-Digital Converters With Serial Control and 11 Analog Inputs

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TLC1542C, TLC1542I, TLC1542M, TLC1542Q, TLC1543C, TLC1543I, TLC1543Q

10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH

D 10-Bit Resolution A/D Converter DB, DW, J, OR N PACKAGE

D Three Built-In Self-Test Modes

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

functional block diagram

typical equivalent inputs

2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3

detailed description (continued)

Table 1. Mode Operation

4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5

analog inputs and test modes (continued)

Table 2. Analog-Channel-Select Address

Table 3. Test-Mode-Select Address

converter and analog input

6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

converter and analog input (continued)

Node 512 REF+ REF+ REF+ REF+ REF+ REF+ REF+

REF – REF – REF – REF – REF – REF – REF – REF – REF –

Figure 1. Simplified Model of the Successive-Approximation System

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7

recommended operating conditions

8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics over recommended operating free-air temperature range,

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9

operating characteristics over recommended operating free-air temperature range,

See timing diagrams I/O

10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

operating characteristics over recommended operating free-air temperature range,

PARAMETER MEASUREMENT INFORMATION

EOC DATA OUT

Figure 2. Load Circuits

tPZH, tPZL th(A)

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11

PARAMETER MEASUREMENT INFORMATION

Figure 5. I/O CLOCK Setup and Hold Time Voltage Waveforms

Figure 6. I/O CLOCK and DATA OUT Voltage Waveforms

I/O CLOCK 10th 0.8 V

Figure 7. I/O CLOCK and EOC Voltage Waveforms

Figure 8. EOC and DATA OUT Voltage Waveforms

12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

Shift in New Multiplexer Address;

Figure 9. Timing for 10-Clock Transfer Using CS

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13

PARAMETER MEASUREMENT INFORMATION

timing diagrams (continued)

Must be High on Power Up

Shift in New Multiplexer Address;

Figure 10. Timing for 10-Clock Transfer Not Using CS

14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

timing diagrams (continued)

Shift in New Multiplexer Address;

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 15