ARM Lab Manual1 PDF

Geetha Shishu Shikshana Sangha(R)
GSSS INSTITUTE OF ENGINEERING AND TECHNOLOGY

FOR WOMEN
(Affiliated to Visvesvaraya Technological University and Approved
by AICTE, New Delhi and Govt. of Karnataka)
K.R.S Road, Metagalli, Mysuru – 570016
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

Accredited by NBA, New Delhi (Validity: 01.07.2017 - 30.06.2020)
EMBEDDED CONTROLLER LAB (15ECL67)

6TH SEMESTER, 2018
Prepared by
Smt Thilagavathy R , Assistant Professor, Dept of ECE, GSSSIETW,Mysuru

Sri Aravind R, Assistant Professor, Dept of ECE, GSSSIETW,Mysuru
VISION
To foster professional level competence in all areas of Electronics and Communication Engineering
and to benchmark the Department as a centre in the Country, for nurturing Women Engineers in the
Country.
Mission of the Department:
M1: To impart value based Technical education and training.
M2: To impart Theoretical Knowledge, Practical Knowledge and Entrepreneurship Skills.
M3: To develop Innovation and Creativity in Students.
M4: To conduct Application oriented research.
M5: To sensitize the Students regarding Social, Moral and Professional ethics.
M6: To provide sufficient Industry exposure to the Students.
M7: To provide special skills training to the Students to make them eligible for Placement.
PROGRAM EDUCATIONAL OBJECTIVES
PEO1: To inculcate students to excel in professional career and/or higher education by acquiring
knowledge in the field of Electronics and Communication.
PEO2: To make the students capable of managing their profession based on existing as well as
new emerging technologies in the area of Electronics and Communication Engineering.
PEO3: To Produce Technically competent graduates with ability to analyze, design, develop,
optimize and implement Electronics and Communication systems.
PEO4: To prepare the students to be able to exhibit professionalism, ethical attitude,

communication skills, team work in their profession and to adapt to current trends by
engaging in life-long learning.
Program Outcomes
Engineering Graduates will be able to:
1. Engineering knowledge: Apply the knowledge of mathematics, science, engineering

fundamentals, and an engineering specialization to the solution of complex engineering
problems.
2. Problem analysis: Identify, formulate, review research literature, and analyze complex
engineering problems reaching substantiated conclusions using first principles of mathematics,
natural sciences, and engineering sciences.
3. Design/development of solutions: Design solutions for complex engineering problems and
design system components or processes that meet the specified needs with appropriate
consideration for the public health and safety, and the cultural, societal, and environmental
considerations.
4. Conduct investigations of complex problems: Use research-based knowledge and research
methods including design of experiments, analysis and interpretation of data, and synthesis of the
information to provide valid conclusions.
5. Modern tool usage: Create, select, and apply appropriate techniques, resources, and modern
engineering and IT tools including prediction and modeling to complex engineering activities
with an understanding of the limitations.
6. The engineer and society: Apply reasoning informed by the contextual knowledge to assess
societal, health, safety, legal and cultural issues and the consequent responsibilities relevant to
the professional engineering practice.
7. Environment and sustainability: Understand the impact of the professional engineering
solutions in societal and environmental contexts, and demonstrate the knowledge of, and need for
sustainable development.
8. Ethics: Apply ethical principles and commit to professional ethics and responsibilities and norms
of the engineering practice.
9. Individual and team work: Function effectively as an individual, and as a member or leader in
diverse teams, and in multidisciplinary settings.
10. Communication: Communicate effectively on complex engineering activities with the
engineering community and with society at large, such as, being able to comprehend and write
effective reports and design documentation, make effective presentations, and give and receive
clear instructions.
11. Project management and finance: Demonstrate knowledge and understanding of the
engineering and management principles and apply these to one’s own work, as a member and
leader in a team, to manage projects and in multidisciplinary environments.
12. Life-long learning: Recognize the need for, and have the preparation and ability to engage in
independent and life-long learning in the broadest context of technological change.
Program Specific Outcomes
PSO1. Graduates will have the ability to mould the technology in the areas of Analog and
Digital Scenario.
PSO2. Implementation of functional Blocks of hardware software co-design for signal

processing and communication application
Embedded Controller Laboratory Syllabus
Subject Code: 15ECL67 I.A. Marks: 20

Hours/Week: 03 Exam Hours: 03
Total Hours: 42 Exam Marks: 80
PART-A: Conduct the following Study experiments to learn ALP using ARM Cortex M3 Registers
using an Evaluation board and the required software tool.
1. ALP to multiply two 16 bit binary numbers.
2. ALP to find the sum of first 10 integer numbers.
PART-B: Conduct the following experiments on an ARM CORTEX M3 evaluation board using
evaluation version of Embedded 'C' & Keil Uvision-4 tool/compiler.
1. Display “Hello World” message using Internal UART.
2. Interface and Control a DC Motor.
3. Interface a Stepper motor and rotate it in clockwise and anti-clockwise direction.
4. Determine Digital output for a given Analog input using Internal ADC of ARM controller.
5. Interface a DAC and generate Triangular and Square waveforms.
6. Interface a 4x4 keyboard and display the key code on an LCD.
7. Using the Internal PWM module of ARM controller generate PWM and vary its duty cycle.
8. Demonstrate the use of an external interrupt to toggle an LED On/Off.
9. Display the Hex digits 0 to F on a 7-segment LED interface, with an appropriate delay in between.
10. Interface a simple Switch and display its status through Relay, Buzzer and LED.
11. Measure Ambient temperature using a sensor and SPI ADC IC. 
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Dos & don’ts
1. Check the components before you start the experiment.

2. Handle the equipments & components carefully
3. Know emergency procedures
4. Never work in the laboratory without the supervision of an instructor
5. Always perform the experiments or work precisely as directed by your instructor.
6. Store coats, bags, and other personal items in designated areas
7. Keep the work benches clear of all objects
8. Do not handle any equipment before reading the instructions/Instruction manuals.
9. Observe type of sockets of equipment power to avoid mechanical damage.
Embedded Controller Lab(15ECL67)
1. INTRODUCTION TO ARM CORTEX M3 PROCESSOR
1.1 Introduction
The ARM Cortex-M3 is a general purpose 32-bit microprocessor, which offers high performance
and very low power consumption. The Cortex-M3 offers many new features, including a Thumb-
2 instruction set, low interrupt latency, hardware divide, interruptible/continuable multiple load
and store instructions, automatic state save and restore for interrupts, tightly integrated interrupt
controller with Wake-up Interrupt Controller and multiple core buses capable of simultaneous
accesses. Pipeline techniques are employed so that all parts of the processing and memory
systems can operate continuously. Typically, while one instruction is being executed, its
successor is being decoded, and a third instruction is being fetched from memory.
The processor has a Harvard architecture, which means that it has a separate instruction bus and
data bus. This allows instructions and data accesses to take place at the same time, and as a result
of this, the performance of the processor increases because data accesses do not affect the
instruction pipeline. This feature results in multiple bus interfaces on Cortex-M3, each with
optimized usage and the ability to be used simultaneously. However, the instruction and data
buses share the same memory space (a unified memory system). In other words, you cannot get 8
GB of memory space just because you have separate bus interfaces.
A simplified block diagram of the Cortex-m3 architecture is shown below
Dept. of ECE, GSSSIETW, Mysuru Page 1

It is worthwhile highlighting that the Cortex-M3 processor is not the first ARM processor to be
used to create generic micro controllers. The venerable ARM7 processor has been very
successful in this market, The Cortex-M3 processor builds on the success of the ARM7
processor to deliver devices that are significantly easier to program and debug and yet deliver a
higher processing capability.
1.2 Background of ARM architecture

ARM was formed in 1990 as Advanced RISC Machines Ltd., a joint venture of Apple Computer,
Acorn Computer Group, and VLSI Technology. In 1991, ARM introduced the ARM6 processor
family, and VLSI became the initial licensee. Subsequently, additional companies, including
Texas Instruments, NEC, Sharp, and ST Microelectronics, licensed the ARM processor designs,
extending the applications of ARM processors into mobile phones, computer hard disks, personal
digital assistants (PDAs), home entertainment systems, and many other consumer products.
Nowadays, ARM partners ship in excess of 2 billion ARM processors each year. Unlike many
semiconductor companies, ARM does not manufacture processors or sell the chips directly.
Instead, ARM licenses the processor designs to business partners, including a majority of the
world‟s leading semiconductor companies. Based on the ARM low-cost and power-efficient
processor designs, these partners create their processors, micro controllers, and system-onchip
solutions. This business model is commonly called intellectual property (IP) licensing.
1.3 Architecture versions

Over the years, ARM has continued to develop new processors and system blocks. These include
the popular ARM7TDMI processor and, more recently, the ARM1176TZ (F)-S processor, which
is used in high-end applications such as smart phones. The evolution of features and
enhancements to the processors over time has led to successive versions of the ARM
architecture. Note that architecture version numbers are independent from processor names. For
example, the ARM7TDMI processor is based on the ARMv4T architecture (the T is for Thumb
instruction mode support).

The ARMv5E architecture was introduced with the ARM9E processor families, including the
ARM926E-S and ARM946E-S processors. This architecture added “Enhanced” Digital Signal
Processing (DSP) instructions for multimedia applications. With the arrival of the ARM11
processor family, the architecture was extended to the ARMv6. New features in this architecture
included memory system features and Single Instruction–Multiple Data (SIMD) instructions.
Processors based on the ARMv6 architecture include the ARM1136J (F)-S, the ARM1156T2
(F)-S, and the ARM1176JZ (F)-S. Over the past several years, ARM extended its product
portfolio by diversifying its CPU development, which resulted in the architecture version 7 or v7.
In this version, the architecture design is divided into three profiles:

 The A profile is designed for high-performance open application platforms.
 The R profile is designed for high-end embedded systems in which real-time
performance is needed.
 The M profile is designed for deeply embedded micro controller-type systems.
Bit more details on these profiles

A Profile (ARMv7-A): Application processors which are designed to handle complex
applications such as high-end embedded operating systems (OSs) (e.g., Symbian, Linux, and
Windows Embedded). These processors requiring the highest processing power, virtual memory
system support with memory management units (MMUs), and, optionally, enhanced Java
support and a secure program execution environment. Example products include high-end
mobile phones and electronic wallets for financial transactions.
R Profile (ARMv7-R): Real-time, high-performance processors targeted primarily at the higher
end of the real-time market, those applications, such as high-end breaking systems and hard drive
controllers, in which high processing power and high reliability are essential and for which low
latency is important.
M Profile (ARMv7-M): Processors targeting low-cost applications in which processing
efficiency is important and cost, power consumption, low interrupt latency, and ease of use are
critical, as well as industrial control applications, including real-time control systems. The
Cortex processor families are the first products developed on architecture v7, and the Cortex- M3

processor is based on one profile of the v7 architecture, called ARM v7-M, an architecture
specification for micro controller products.
Below figure shows the development stages of ARM versions
1.4 Instruction Set Development

Enhancement and extension of instruction sets used by the ARM processors has been one of the
key driving forces of the architecture‟s evolution. Historically (since ARM7TDMI), two
different instruction sets are supported on the ARM processor: the ARM instructions that are 32
bits and Thumb instructions that are 16 bits. During program execution, the processor can be
dynamically switched between the ARM state and the Thumb state to use either one of the
instruction sets. The Thumb instruction set provides only a subset of the ARM instructions, but it
can provide higher code density. It is useful for products with tight memory requirements.
1.4.1 The Thumb-2 Technology and Instruction Set Architecture

The Thumb-2 technology extended the Thumb Instruction Set Architecture (ISA) into a highly
efficient and powerful instruction set that delivers significant benefits in terms of ease of use,
code size, and performance. The extended instruction set in Thumb-2 is a super set of the
previous 16-bit Thumb instruction set, with additional 16-bit instructions alongside 32-bit
instructions. It allows more complex operations to be carried out in the Thumb state, thus
allowing higher efficiency by reducing the number of states switching between ARM state and
Thumb state. Focused on small memory system devices such as micro controllers and reducing
the size of the processor, the Cortex-M3 supports only the Thumb-2 (and traditional Thumb)
instruction set.
Instead of using ARM instructions for some operations, as in traditional ARM processors, it uses
the Thumb-2 instruction set for all operations. As a result, the Cortex-M3 processor is not
backward compatible with traditional ARM processors. Nevertheless, the Cortex-M3 processor
can execute almost all the 16-bit Thumb instructions, including all 16-bit Thumb instructions
supported on ARM7 family processors, making application porting easy. With support for both
16-bit and 32-bit instructions in the Thumb-2 instruction set, there is no need to switch the
processor between Thumb state (16-bit instructions) and ARM state (32-bit instructions). For
example, in ARM7 or ARM9 family processors, you might need to switch to ARM state if you
want to carry out complex calculations or a large number of conditional operations and good
performance is needed, whereas in the Cortex-M3 processor, you can mix 32-bit instructions
with 16-bit instructions without switching state, getting high code density and high performance
with no extra complexity.
The Thumb-2 instruction set is a very important feature of the ARMv7 architecture. Compared
with the instructions supported on ARM7 family processors (ARMv4T architecture), the Cortex-
M3 processor instruction set has a large number of new features. For the first time, hardware
divide instruction is available on an ARM processor, and a number of multiply instructions are
also available on the Cortex-M3 processor to improve data-crunching performance. The Cortex-
M3 processor also supports unaligned data accesses, a feature previously available only in high
end processors.
1.5 Advantages of Cortex M3 processors

The Cortex-M3 addresses the requirements for the 32-bit embedded processor market in the
following ways:
 Greater performance efficiency: allowing more work to be done without increasing the
frequency or power requirements.

 Low power consumption: enabling longer battery life, especially critical in portable
products including wireless networking applications.
 Enhanced determinism: guaranteeing that critical tasks and interrupts are serviced as
quickly as possible and in a known number of cycles.
 Improved code density: ensuring that code fits in even the smallest memory footprints.
 Ease of use: providing easier programming and debugging for the growing number of 8-
bit and 16-bit users migrating to 32 bits.
 Lower cost solutions: reducing 32-bit-based system costs close to those of legacy 8-bit
and 16-bit devices and enabling low-end, 32-bit micro controllers to be priced at less than
US$1 for the first time.
 Wide choice of development tools: from low-cost or free compilers to full-featured
development suites from many development tool vendors.
Cost savings can be achieved by improving the amount of code reuse across all systems. Because
Cortex-M3 processor-based micro controllers can be easily programmed using the C language
and are based on a well-established architecture, application code can be ported and reused
easily, and reducing development time and testing costs.
1.6 Applications of Cortex M3 processors

Low-cost micro controllers: The Cortex-M3 processor is ideally suited for low-cost micro
controllers, which are commonly used in consumer products, from toys to electrical appliances.
It is a highly competitive market due to the many well-known 8-bit and 16-bit micro controller
products on the market. Its lower power, high performance, and ease-of-use advantages enable
embedded developers to migrate to 32-bit systems and develop products with the ARM
architecture.
Automotive: Another ideal application for the Cortex-M3 processor is in the automotive
industry. The Cortex-M3 processor has very high-performance efficiency and low interrupt
latency, allowing it to be used in real-time systems. The Cortex-M3 processor supports up to 240
external vectored interrupts, with a built-in interrupt controller with nested interrupt supports and
an optional MPU, making it ideal for highly integrated and cost-sensitive automotive
applications.

Data communications: The processor‟s low power and high efficiency, coupled with
instructions in Thumb-2 for bit-field manipulation, make the Cortex-M3 ideal for many
communications applications, such as Bluetooth and ZigBee.
Industrial control: In industrial control applications, simplicity, fast response, and reliability are
key factors. Again, the Cortex-M3 processors interrupt feature, low interrupt latency, and
enhanced fault-handling features make it a strong candidate in this area.
Consumer products: In many consumer products, a high-performance microprocessor (or
several of them) is used. The Cortex-M3 processor, being a small processor, is highly efficient
and low in power and supports an MPU enabling complex software to execute while providing
robust memory protection.
1.7 The Cortex-M3 Processor versus Cortex-M3-Based Micro
Controllers
The Cortex-M3 processor is the central processing unit (CPU) of a micro controller chip. In
addition, a number of other components are required for the whole Cortex-M3 processor-based
micro controller. After chip manufacturers license the Cortex-M3 processor, they can put the
Cortex-M3 processor in their silicon designs, adding memory, peripherals, input/output (I/O),
and other features. Cortex-M3 processor-based chips from different manufacturers will have
different memory sizes, types, peripherals, and features.
2. INTRODUCTION TO MICRO CONTROLLER LPC1768

2.1 Architectural Overview

The LPC1768FBD100 is an ARM Cortex-M3 based micro controller for embedded applications
requiring a high level of integration and low power dissipation. The ARM Cortex-M3 is a next
generation core that offers system enhancements such as modernized debug features and a higher
level of support block integration. LPC1768 operate up to 100 MHz CPU frequency.
The peripheral complement of the LPC1768 includes up to 512 kilo bytes of flash memory, up to
64KB of data memory, Ethernet MAC, a USB interface that can be configured as either Host,
Device, or OTG, 8 channel general purpose DMA controller, 4 UARTs, 2 CAN channels, 2 SSP
controllers, SPI interface, 3 I2C interfaces, 2-input plus 2-output I2S interface, 8 channel 12-bit
ADC, 10-bit DAC, motor control PWM, Quadrature Encoder interface, 4 general purpose timers,
6-output general purpose PWM, ultra-low power RTC with separate battery supply, and up to 70
general purpose I/O pins.
The LPC1768 use a multi layer AHB(Advanced High Performance Bus) matrix to connect the
ARM Cortex-M3 buses and other bus masters to peripherals in a flexible manner that optimizes
performance by allowing peripherals that are on different slaves ports of the matrix to be
accessed simultaneously by different bus masters.
On-chip flash memory system
The LPC1768 contains up to 512 KB of on-chip flash memory. A flash memory accelerator
maximizes performance for use with the two fast AHB Lite buses. This memory may be used for
both code and data storage. Programming of the flash memory may be accomplished in several
ways. It may be programmed In System via the serial port. The application program may also
erase and/or program the flash while the application is running, allowing a great degree of
flexibility for data storage field firmware upgrades, etc.
On-chip Static RAM
The LPC1768 contains up to 64 KB of on-chip static RAM memory. Up to 32 KB of SRAM,
accessible by the CPU and all three DMA controllers are on a higher-speed bus. Devices
containing more than 32 KB SRAM have two additional 16 KB SRAM blocks, each situated on
separate slave ports on the AHB multilayer matrix. This architecture allows the possibility for
CPU and DMA accesses to be separated in such a way that there are few or no delays for the bus
masters.

2.2 Block Diagram of LPC1768FBD10
2.3 A brief description of the blocks:

Nested vector interrupt controller

The NVIC is an integral part of the Cortex-M3. The tight coupling to the CPU allows for low
interrupt latency and efficient processing of late arriving interrupts.
Features
 Controls system exceptions and peripheral interrupts
 In the LPC1768, the NVIC supports 33 vectored interrupts
 32 programmable interrupt priority levels, with hardware priority level masking
 Relocatable vector table
 Non-Maskable Interrupt (NMI)
 Software interrupt generation
Interrupt sources
Each peripheral device has one interrupt line connected to the NVIC but may have several
interrupt flags. Individual interrupt flags may also represent more than one interrupt source. Any
pin on Port 0 and Port 2 (total of 42 pins) regardless of the selected function, can be programmed
to generate an interrupt on a rising edge, a falling edge, or both.
General purpose DMA controller
The GPDMA (General Purpose Direct Memory Access) is an AMBA AHB (Advanced Micro
controller Bus Architecture Advance high performance bus) compliant peripheral allowing
selected peripherals to have DMA support. The GPDMA enables peripheral-to-memory,
memory-to-peripheral, peripheral-to-peripheral, and memory-to-memory transactions. The
source and destination areas can each be either a memory region or a peripheral, and can be
accessed through the AHB master. The GPDMA controller allows data transfers between the
USB and Ethernet controllers and the various onchip SRAM areas. The supported APB
peripherals are SSP0/1, all UARTs, the I2S-bus interface, the ADC, and the DAC. Two match
signals for each timer can be used to trigger DMA transfers.
Function Configuration block
The selected pins of the micro controller to have more than one function. Configuration registers
control the multiplexers to allow connection between the pin and the on-chip peripherals.
Peripherals should be connected to the appropriate pins prior to being activated and prior to any
related interrupt(s) being enabled. Activity of any enabled peripheral function that is not mapped

to a related pin should be considered undefined. Most pins can also be configured as open-drain
outputs or to have a pullup, pull-down, or no resistor enabled.
Fast general purpose parallel I/O
Device pins that are not connected to a specific peripheral function are controlled by the GPIO
registers. Pins may be dynamically configured as inputs or outputs. Separate registers allow
setting or clearing any number of outputs simultaneously. The value of the output register may
be read back as well as the current state of the port pins.
USB interface
The Universal Serial Bus (USB) is a 4-wire bus that supports communication between a host and
one or more (up to 127) peripherals. The host controller allocates the USB bandwidth to attached
devices through a token-based protocol. The bus supports hot plugging and dynamic
configuration of the devices. All transactions are initiated by the host controller.
The USB interface includes a device, Host, and OTG controller with on-chip PHY for device and
Host functions. The OTG switching protocol is supported through the use of an external
controller.
USB device controller enables 12 Mbit/s data exchange with a USB Host controller. It consists
of a register interface, serial interface engine, endpoint buffer memory, and a DMA controller.
The serial interface engine decodes the USB data stream and writes data to the appropriate
endpoint buffer. The status of a completed USB transfer or error condition is indicated via status
registers. An interrupt is also generated if enabled. When enabled, the DMA controller transfers
data between the endpoint buffer and the on-chip SRAM.
12-bit ADC
The LPC1768 contain a single 12-bit successive approximation ADC with eight channels and
DMA support.
10-bit DAC
The DAC allows to generate a variable analog output. The maximum output value of the DAC is
VREFP.
UART's
The LPC1768 contain four UART's. In addition to standard transmit and receive data lines,
UART1 also provides a full modem control handshake interface and support for RS-485/9-bit
mode allowing both software address detection and automatic address detection using 9-bit

mode. The UART's include a fractional baud rate generator. Standard baud rates such as 115200
Baud can be achieved with any crystal frequency above 2 MHz
SPI serial I/O controller
The LPC1768 contain one SPI controller. SPI is a full duplex serial interface designed to handle
multiple masters and slaves connected to a given bus. Only a single master and a single slave can
communicate on the interface during a given data transfer. During a data transfer the master
always sends 8 bits to 16 bits of data to the slave, and the slave always sends 8 bits to 16 bits of
data to the master.
SSP serial I/O controller
The LPC1768 contain two SSP controllers. The SSP controller is capable of operation on a SPI,
4-wire SSI, or Micro wire bus. It can interact with multiple masters and slaves on the bus. Only a
single master and a single slave can communicate on the bus during a given data transfer. The
SSP supports full duplex transfers, with frames of 4 bits to 16 bits of data flowing from the
master to the slave and from the slave to the master. In practice, often only one of these data
flows carries meaningful data.
I2C-bus serial I/O controllers
The LPC1768 each contain three I2C-bus controllers. The I2C-bus is bidirectional for inter-IC
control using only two wires: a Serial Clock line (SCL) and a Serial DAta line (SDA). Each
device is recognized by a unique address and can operate as either a receiver-only device or a
transmitter with the capability to both receive and send information (such as memory).
Transmitters and/or receivers can operate in either master or slave mode, depending on whether
the chip has to initiate a data transfer or is only addressed. The I2C is a multi-master bus and can
be controlled by more than one bus master connected to it.
General purpose 32-bit timers/external event counters
The LPC1768 include four 32-bit timer/counters. The timer/counter is designed to count cycles
of the system derived clock or an externally-supplied clock. It can optionally generate interrupts,
generate timed DMA requests, or perform other actions at specified timer values, based on four
match registers. Each timer/counter also includes two capture inputs to trap the timer value when
an input signal transitions, optionally generating an interrupt.
Pulse width modulator

The PWM is based on the standard Timer block and inherits all of its features, although only the
PWM function is pinned out on the LPC1768. The Timer is designed to count cycles of the
system derived clock and optionally switch pins, generate interrupts or perform other actions
when specified timer values occur, based on seven match registers. The PWM function is in
addition to these features, and is based on match register events.
Watchdog timer
The purpose of the watchdog is to reset the micro controller within a reasonable amount of time
if it enters an erroneous state. When enabled, the watchdog will generate a system reset if the
user program fails to „feed‟ (or reload) the watchdog within a predetermined amount of time.
RTC and backup registers
The RTC is a set of counters for measuring time when system power is on, and optionally when
it is off. The RTC on the LPC1768 is designed to have extremely low power consumption, i.e.
less than 1 uA. The RTC will typically run from the main chip power supply, conserving battery
power while the rest of the device is powered up. When operating from a battery, the RTC will
continue working down to 2.1 V. Battery power can be provided from a standard 3 V Lithium
button cell. An ultra-low power 32 kHz oscillator will provide a 1 Hz clock to the time counting
portion of the RTC, moving most of the power consumption out of the time counting function.
Clocking and Power Control
Crystal oscillators
The LPC1768 include three independent oscillators. These are the main oscillator, the IRC
oscillator, and the RTC oscillator. Each oscillator can be used for more than one purpose as
required in a particular application. Any of the three clock sources can be chosen by software to
drive the main PLL and ultimately the CPU. Following reset, the LPC1768 will operate from the
Internal RC oscillator until switched by software. This allows systems to operate without any
external crystal and the boot loader code to operate at a known frequency.
Power control
The LPC1768 support a variety of power control features. There are four special modes of
processor power reduction: Sleep mode, Deep-sleep mode, Power-down mode, and Deep power-
down mode. The CPU clock rate may also be controlled as needed by changing clock sources,
reconfiguring PLL values, and/or altering the CPU clock divider value. This allows a trade-off of
power versus processing speed based on application requirements. In addition, Peripheral Power

Control allows shutting down the clocks to individual on-chip peripherals, allowing fine tuning
of power consumption by eliminating all dynamic power use in any peripherals that are not
required for the application. Each of the peripherals has its own clock divider which provides
even better power control.
Integrated PMU (Power Management Unit) automatically adjust internal regulators to minimize
power consumption during Sleep, Deep sleep, Power-down, and Deep power- down modes. The
LPC1768 also implement a separate power domain to allow turning off power to the bulk of the
device while maintaining operation of the RTC and a small set of registers for storing data during
any of the power-down modes.
Clock generation block diagram for LPC1768 is shown below
System Control
Reset
Reset has four sources on the LPC1768: the RESET pin, the Watchdog reset, power-on reset
(POR), and the Brown-Out Detection (BOD) circuit. The RESET pin is a Schmitt trigger input
pin. Assertion of chip Reset by any source, once the operating voltage attains a usable level,
causes the RSTOUT pin to go LOW. Once reset is de-asserted, or, in case of a BOD- triggered
reset, once the voltage rises above the BOD threshold, the RSTOUT pin goes HIGH. In other
words RSTOUT is high when the controller is in its active state.
Emulation and debugging

Debug and trace functions are integrated into the ARM Cortex-M3. Serial wire debug and trace
functions are supported in addition to a standard JTAG debug and parallel trace functions. The
ARM Cortex-M3 is configured to support up to eight breakpoints and four watch points.
Note: For further details on Controller blocks refer the User manual of LPC176x/5x – UM10360
available at www.nxp.com
3. TECHNICAL SPECIFICATIONS of LPC1768

3.1 Specifications of LPC1768:
 ARM Cortex-M3 processor runs up to 100 MHz frequency.
 ARM Cortex-M3 built-in Nested Vectored Interrupt Controller (NVIC).
 Up to 512kB on-chip flash program memory with In-System Programming (ISP) and In-
Application Programming (IAP) capabilities. The combination of an enhanced flash memory
accelerator and location of the flash memory on the CPU local code/data bus provides high code
performance from flash.
 Up to 64kB on-chip SRAM includes: Up to 32kB of SRAM on the CPU with local
code/data bus for high-performance CPU access. Up to two 16kB SRAM blocks with
separate access paths for higher throughput. These SRAM blocks may be used for
Ethernet, USB, and DMA memory, as well as for general purpose instruction and data
storage.
 Eight channel General Purpose DMA controller (GPDMA) on the AHB multilayer matrix
that can be used with the SSP, I2S, UART, the Analog-to-Digital and Digital-to-Analog
converter peripherals, timer match signals, GPIO, and for memory-to-memory transfers.
 Serial interfaces:
- Ethernet MAC with RMII interface and dedicated DMA controller.
- USB 2.0 full-speed controller that can be configured for either device, Host, or OTG operation
with an on-chip PHY for device and Host functions and a dedicated DMA controller.
- Four UART's with fractional baud rate generation, internal FIFO, IrDA, and DMA support.
One UART has modem control I/O and RS-485/EIA-485 support.
- Two-channel CAN controller.
- Two SSP controllers with FIFO and multi-protocol capabilities. The SSP interfaces can be used
with the GPDMA controller.

- SPI controller with synchronous, serial, full duplex communication and programmable data
length. SPI is included as a legacy peripheral and can be used instead of SSP0.
- Three enhanced I2C-bus interfaces, one with an open-drain output supporting the full I2C
specification and Fast mode plus with data rates of 1Mbit/s, two with standard port pins.
Enhancements include multiple address recognition and monitor mode.
- I2S (Inter-IC Sound) interface for digital audio input or output, with fractional rate control. The
I2S interface can be used with the GPDMA. The I2S interface supports 3-wire data transmit and
receive or 4-wire combined transmit and receive connections, as well as master clock output.
 Other peripherals:
- 70 General Purpose I/O (GPIO) pins with configurable pull-up/down resistors, open drain
mode, and repeater mode. All GPIOs are located on an AHB bus for fast access, and support
Cortex-M3 bit-banding. GPIOs can be accessed by the General Purpose DMA Controller. Any
pin of ports 0 and 2 can be used to generate an interrupt.
- 12-bit Analog-to-Digital Converter (ADC) with input multiplexing among eight pins,
conversion rates up to 200 kHz, and multiple result registers. The 12-bit ADC can be used with
the GPDMA controller.
- 10-bit Digital-to-Analog Converter (DAC) with dedicated conversion timer and DMA support.
- Four general purpose timers/counters, with a total of eight capture inputs and ten compare
outputs. Each timer block has an external count input. Specific timer events can be selected to
generate DMA requests.
- One motor control PWM with support for three-phase motor control.
- Quadrature encoder interface that can monitor one external quadrature encoder.
- One standard PWM/timer block with external count input.
- Real-Time Clock (RTC) with a separate power domain. The RTC is clocked by a dedicated
RTC oscillator. The RTC block includes 20 bytes of battery-powered backup registers, allowing
system status to be stored when the rest of the chip is powered off. Battery power can be
supplied from a standard 3 V Lithium button cell. The RTC will continue working when the
battery voltage drops to as low as 2.1 V. An RTC interrupt can wake up the CPU from any
reduced power mode.
- Watchdog Timer (WDT). The WDT can be clocked from the internal RC oscillator, the RTC
oscillator, or the APB clock.

- Cortex-M3 system tick timer, including an external clock input option.

- Repetitive interrupt timer provides programmable and repeating timed interrupts.
 Standard JTAG test/debug interface as well as Serial Wire Debug and Serial Wire Trace
Port options.
 Emulation trace module supports real-time trace.
 Four reduced power modes: Sleep, Deep-sleep, Power-down, and Deep power-down.
 Single 3.3 V power supply (2.4 V to 3.6 V). Temperature range of -40 °C to 85 °C.
 Four external interrupt inputs configurable as edge/level sensitive. All pins on PORT0
and PORT2 can be used as edge sensitive interrupt sources.
 Non Maskable Interrupt (NMI) input.
 Clock output function that can reflect the main oscillator clock, IRC clock, RTC clock,
CPU clock, or the USB clock.
 The Wake-up Interrupt Controller (WIC) allows the CPU to automatically wake up from
any priority interrupt that can occur while the clocks are stopped in deep sleep,
Powerdown, and Deep power-down modes
 Processor wake-up from Power-down mode via any interrupt able to operate during
Power-down mode (includes external interrupts, RTC interrupt, USB activity, Ethernet
wake-up interrupt, CAN bus activity, PORT0/2 pin interrupt, and NMI).
 Each peripheral has its own clock divider for further power savings.
 Brownout detect with separate threshold for interrupt and forced reset.
 On-chip Power-On Reset (POR).
 On-chip crystal oscillator with an operating range of 1 MHz to 25 MHz.
 4 MHz internal RC oscillator trimmed to 1% accuracy that can optionally be used as a
system clock.
 An on-chip PLL allows CPU operation up to the maximum CPU rate without the need for
a high-frequency crystal. May be run from the main oscillator, the internal RC oscillator,
or the RTC oscillator.
 A second, dedicated PLL may be used for the USB interface in order to allow added
flexibility for the Main PLL settings.
 Versatile pin function selection feature allows many possibilities for using on-chip
peripheral functions.

3.2 SPECIFICATIONS OF ALS-SDA-ARMCTXM3-06

 LPC1768 is ARM Cortex M3 based micro controller with
 512KB flash memory and 64KB SRAM In-System Programming (ISP) and In-
Application Programming (IAP) capabilities.
 Single 3.3 V power supply (2.4 V to 3.6 V).
 70 General Purpose I/O (GPIO) pins with configurable pull-up/down resistors, open drain
mode, and repeater mode.
 12-bit Analog-to-Digital Converter (ADC) and up to 8 analog channels.
 10-bit Digital-to-Analog Converter (DAC) with dedicated conversion timer.
 Four general purpose timers/counters, with a total of eight capture inputs and ten compare
outputs.
 Four UART's with fractional baud rate generation, internal FIFO, IrDA.
 SPI controller with synchronous, serial, full duplex communication.
 Three enhanced I2C-bus interfaces
 Four reduced power modes: Sleep, Deep-sleep, Power-down, and Deep powerdown.
 Real-Time Clock (RTC) with a separate power domain.
 Standard JTAG test/debug interface as well as Serial Wire Debug.
 Four external interrupt inputs configurable as edge/level sensitive.
 12MHz Crystal allows easy communication setup
 One on board voltage regulator for generating 3.3V. Input to this will be from External
 +5V DC Power supply through a 9-pin DSUB connector
 Piggy Back module containing LPC1768 controller
 Standard JTAG connector with ARM 2×10 pin layout for programming/debugging with
ARM-JTAG
 Reset push-button for resetting the controller
 One RS232 interface circuit with 9 pin DSUB connector: this is used by the Boot loader
program, to program LPC1768 Flash memory without external Programmer
 DC motor interface with direction and speed control
 Stepper motor interface with direction and speed control
 16×2 alphanumeric LCD Display
 On chip ADC interface circuit using AD0.5(P1.31)

 8-bit DAC interface

 4x4 Key-Matrix connected to the port lines of the controller
 One External interrupt circuit with LED indication
 Two-digit multiplexed 7-segment display interface
 Interface circuit for on board Buzzer, Relay and Led indication controlled through push
button.
 SPI Interface: 2 channel ADC IC with POT and Temperature sensor
 I2C Interface: NVROM IC
 Standard 26-pin FRC connectors to connect to on-board interface or some of ALS
standard External Interfaces.
 A number of software examples in „C-language‟ to illustrate the functioning of the
interfaces. The software examples are compiled using an evaluation version of KEIL4
„C‟ compiler for ARM.
 Compact elegant plastic enclosure
 Optional USB to Serial interface (RS232) cable.

Embedded Controller Lab- 15ECL67
PART-A
Conduct the following Study experiments to learn ALP using ARM Cortex M3 Registers using
an Evaluation board and the required software tool.
1. ALP to multiply two 16 bit binary numbers
#include <LPC17xx.h>
extern void MULTIPLY(void);

extern unsigned long int globvar; //global variable to access at asm code
unsigned long int globvar,result;
#include "LCD.h"
int main(void)
{
SystemInit();
MULTIPLY(); //Function Call
result = globvar;
LCD_DISP(globvar);
while(1);
2. ALP to find the sum of first 10 integer numbers
extern void sumten(void); //Name of assembly routine
extern unsigned long int globvar; //global variable to access at asm code
unsigned long int globvar,result;

#include "LCD.h"
int main(void)
{
SystemInit();
sumten(); //calling asm code
result = globvar;
LCD_DISP(globvar);
while(1);
Dept. of TCE, GSSSIETW, Mysuru Page 1

PART-B
Conduct the following experiments on an ARM CORTEX M3 evaluation board using

evaluation version of Embedded 'C' & Keil Uvision-4 tool/compiler.
1) Display “Hello World” message using Internal UART
#include<LPC17xx.h>
void delay(unsigned int r1);

void UART0_Init(void);
void UART0_IRQHandler(void);
unsigned long int r=0, i = 0;

unsigned char tx0_flag=0;
unsigned char *ptr, arr[] = "Hello world\r";
int main(void)
{

SystemInit();
SystemCoreClockUpdate();
UART0_Init();
while(1)
{
ptr = arr;
while ( *ptr != '\0'){
LPC_UART0->THR = *ptr++;
while(tx0_flag == 0x00);
tx0_flag = 0x00;
for (i=0; i<200; i++);
}
for (i=0; i<500; i++)
delay(625); //delay
}
}
void UART0_Init(void)
{
LPC_SC->PCONP |= 0x00000008; //UART0 peripheral enable
LPC_PINCON->PINSEL0 |= 0x00000050;
LPC_UART0->LCR = 0x00000083; //enable divisor latch, parity disable,
1 stop bit, 8bit word length
LPC_UART0->DLM = 0X00;
LPC_UART0->DLL = 0x13; //select baud rate 9600 bps
LPC_UART0->LCR = 0X00000003;
LPC_UART0->FCR = 0x07;
LPC_UART0->IER = 0X03; //select Transmit and receive
interrupt
NVIC_EnableIRQ(UART0_IRQn); //Assigning channel

}
void UART0_IRQHandler(void)
{
unsigned long Int_Stat;
Int_Stat = LPC_UART0->IIR; //reading the data from
interrupt identification register
Int_Stat = Int_Stat & 0x06; //masking other than txmit int & rcve
data indicator
if((Int_Stat & 0x02)== 0x02) //transmit interrupt

tx0_flag = 0xff;
}
void delay(unsigned int r1)

{
for(r=0;r<r1;r++);
}
2) a. Interface and Control a Speed of DC Motor.
#include <lpc17xx.h>
void pwm_init(void);
void PWM1_IRQHandler(void);
unsigned long int i,j;

unsigned char flag,flag1,flag2;
int main(void)
{
SystemInit();
pwm_init();
while(1)
{
for(i=0;i<=1000;i++); // delay
}//end of while
}//end of main
void pwm_init(void)
{
LPC_SC->PCONP |= (1<<6); //PWM1 is
powered

LPC_PINCON->PINSEL3 |= 0x00020000; //pwm1.5 is selected for the pin P1.24
LPC_PWM1->PR = 0x00000000; //Count frequency : Fpclk

LPC_PWM1->PCR = 0x0002000; //select PWM5 single edge and PWM5
output is enabled
LPC_PWM1->MCR = 0x00000003; //Reset and interrupt on PWMMR0
LPC_PWM1->MR0 = 30000; //setup match register 0 count
LPC_PWM1->MR5 = 0x00000100; //setup match register MR5
LPC_PWM1->LER = 0x000000FF; //enable shadow copy register
LPC_PWM1->TCR = 0x00000002; //RESET COUNTER AND PRESCALER
LPC_PWM1->TCR = 0x00000009; //enable PWM and counter
NVIC_EnableIRQ(PWM1_IRQn);
return;
}
void PWM1_IRQHandler(void)
{
LPC_PWM1->IR = 0xff; //clear the interrupts
if(flag == 0x00)
{
LPC_PWM1->MR5 += 100;
LPC_PWM1->LER = 0x000000FF;
if(LPC_PWM1->MR5 >= 37000)

{
flag1 = 0xff;
flag = 0xff;
LPC_PWM1->LER = 0x000000fF;
}
for(i=0;i<8000;i++);
}
else if(flag1 == 0xff)

{
LPC_PWM1->MR5 -= 100;
if(LPC_PWM1->MR5 <= 0x500)

{
flag = 0x00;
flag1 = 0x00;

LPC_PWM1->LER = 0X000000fF;
}
for(i=0;i<8000;i++);
}
}
b. Interface and Control a Direction of DC Motor.
#include <LPC17xx.H>
void Clock_Wise(void);
void AClock_Wise(void);
unsigned long i;
int main(void)
{
SystemInit();
LPC_PINCON->PINSEL1 &= 0xFFCFFFFF; //P0.26 GPIO, P0.26 controls dir
LPC_PINCON->PINSEL3 &= 0xFFFFCFFF; //P1.24 GPIO
LPC_GPIO0->FIODIR |= 0x04000000; //P0.26 output
while(1)
{
Clock_Wise();
for(i=0;i<200000;i++);
AClock_Wise();
for(i=0;i<200000;i++);
} //end while(1)
} //end main
void Clock_Wise(void)
{
LPC_GPIO1->FIOCLR = 0x01000000; //P0.23 Kept low to off DCM
for(i=0;i<10000;i++); //delay to componsate
inertia
LPC_GPIO0->FIOSET = 0x04000000; //coil is on
LPC_GPIO1->FIOSET = 0x01000000; //motor in on
return;
} //end void
Clock_Wise(void)
void AClock_Wise(void)

{
LPC_GPIO1->FIOCLR = 0x01000000; //P0.23 Kept low to off DCM
for(i=0;i<10000;i++); //delay to componsate inertia
LPC_GPIO0->FIOCLR = 0x04000000; //coil is off
LPC_GPIO1->FIOSET = 0x01000000; //Motor is on
return;
} //end void
AClock_Wise(void)
3) Interface a Stepper motor and rotate it in clockwise and anti-clockwise direction.
void clock_wise(void);
void anti_clock_wise(void);
unsigned long int var1,var2;
unsigned int i=0,j=0,k=0;

int main(void)
{
SystemInit();
LPC_PINCON->PINSEL4 = 0x00000000; //P2.0 to P2.3 GPIO

LPC_GPIO2->FIODIR = 0x0000000F; //P2.0 to P2.3 output
while(1)
{
for(j=0;j<50;j++) //50 times in Clock wise Rotation
clock_wise();
for(k=0;k<65000;k++); //Delay to show anti_clock Rotation
for(j=0;j<50;j++) //50 times in Anti Clock wise Rotation

anti_clock_wise();
for(k=0;k<65000;k++); //Delay to show clock Rotation

} //End of while(1)
} //End of main
void clock_wise(void)
{
var1 = 0x00000001; //For Clockwise
for(i=0;i<=3;i++) //for A B C D Stepping
{
LPC_GPIO2->FIOCLR = 0X0000000F;
LPC_GPIO2->FIOSET = var1;
var1 = var1<<1; //For Clockwise
for(k=0;k<15000;k++); //for step speed variation
}
}
void anti_clock_wise(void)
{
var1 = 0x0000008; //For Anticlockwise
for(i=0;i<=3;i++) //for A B C D Stepping
{
LPC_GPIO2->FIOCLR = 0X0000000F;
LPC_GPIO2->FIOSET = var1;
var1 = var1>>1; //For Anticlockwise
for(k=0;k<15000;k++); //for step speed variation
}

4) Determine Digital output for a given Analog input using Internal ADC of ARM
controller.
#include "AN_LCD.h"
unsigned long int temp1=0, temp2=0 ;
//lcd initialization
void lcd_init()
{
/* Ports initialized as GPIO */
LPC_PINCON->PINSEL4 &= 0xFFF000FF; //P2.4 to P2.9
/* Setting the directions as output */

LPC_GPIO2->FIODIR |= DT_CTRL;
LPC_GPIO2->FIODIR |= RS_CTRL;
LPC_GPIO2->FIODIR |= EN_CTRL;
clear_ports();
delay_lcd(3200);
temp2 = (0x30<<2);
wr_cn();
delay_lcd(30000);
temp2 = (0x30<<2);
wr_cn();
delay_lcd(30000);

temp2 = (0x30<<2);
wr_cn();
delay_lcd(30000);
temp2 = (0x20<<2);
wr_cn();
delay_lcd(30000);
temp1 = 0x28;
lcd_com();
delay_lcd(30000);
temp1 = 0x0c;
lcd_com();
delay_lcd(800);
temp1 = 0x06;
lcd_com();
delay_lcd(800);
temp1 = 0x01;
lcd_com();
delay_lcd(10000);
temp1 = 0x80;
lcd_com();
delay_lcd(800);
return;
}
void lcd_com(void)
{
temp2 = temp1 & 0xf0;//move data (26-8+1) times : 26 - HN place, 4 - Bits
temp2 = temp2 << 2;//data lines from 23 to 26
wr_cn();
temp2 = temp1 & 0x0f; //26-4+1
temp2 = temp2 << 6;
wr_cn();
delay_lcd(1000);
return;
}
// command nibble o/p routine

void wr_cn(void) //write command reg
{
clear_ports();

LPC_GPIO2->FIOPIN = temp2; // Assign the value to the data lines

LPC_GPIO2->FIOCLR = RS_CTRL; // clear bit RS
LPC_GPIO2->FIOSET = EN_CTRL; // EN=1
delay_lcd(25);
LPC_GPIO2->FIOCLR = EN_CTRL; // EN =0
return;
// data o/p routine which also outputs high nibble first

// and lower nibble next
void lcd_data(void)
{
temp2 = temp1 & 0xf0;
temp2 = temp2 << 2;
wr_dn();
temp2= temp1 & 0x0f;
temp2= temp2 << 6;
wr_dn();
delay_lcd(1000);
return;
}
// data nibble o/p routine

void wr_dn(void)
{
clear_ports();

LPC_GPIO2->FIOSET = RS_CTRL; // set bit RS
delay_lcd(25);
return;
}
void delay_lcd(unsigned int r1)
{
unsigned int r;
for(r=0;r<r1;r++);
return;
}
void clr_disp(void)
{
temp1 = 0x01;
lcd_com();

delay_lcd(10000);
return;
}
void clear_ports(void)
{
/* Clearing the lines at power on */
LPC_GPIO2->FIOCLR = DT_CTRL; //Clearing data lines
LPC_GPIO2->FIOCLR = RS_CTRL; //Clearing RS line
LPC_GPIO2->FIOCLR = EN_CTRL; //Clearing Enable line
return;
}
void lcd_puts(unsigned char *buf1)

{
unsigned int i=0;
while(buf1[i]!='\0')
{
temp1 = buf1[i];
lcd_data();
i++;
if(i==16)
{
temp1 = 0xc0;
lcd_com();
}
}
return;
}

5) Interface a DAC and generate Sine, Triangular and Square waveforms.
SINE WAVEFORM
int count=0,sinevalue,value;
unsigned char sine_tab[49]=
{ 0x80,0x90,0xA1,0xB1,0xC0,0xCD,0xDA,0xE5,0xEE,0xF6,0xFB,0xFE,
0xFF,0xFE,0xFB,0xF6,0xEE,0xE5,0xDA,0xCD,0xC0,0xB1,0xA1,0x90,
0x80,0x70,0x5F,0x4F,0x40,0x33,0x26,0x1B,0x12,0x0A,0x05,0x02,
0x00,0x02,0x05,0x0A,0x12,0x1B,0x26,0x33,0x40,0x4F,0x5F,0x70,0x80};
int main(void)
{
LPC_PINCON->PINSEL0 &= 0xFF0000FF ;
// Configure P0.0 to P0.15 as GPIO
LPC_GPIO0->FIODIR |= 0x00000FF0 ;
count = 0;
while(1)
{
for(count=0;count<48;count++)
{
sinevalue = sine_tab[count];//+0X10 ;
value= 0x00000FF0 & (sinevalue << 4);
LPC_GPIO0->FIOPIN = value;
}

}
}
TRIANGULAR WAVEFORM
int main ()
{
unsigned long int temp=0x00000000;
unsigned int i=0;
LPC_PINCON->PINSEL0 &= 0xFF0000FF ; //

Configure P0.4 to P0.11 as GPIO
while(1)
{
//output 0 to FE
for(i=0;i!=0xFF;i++)
{
temp=i;
temp = temp << 4;
LPC_GPIO0->FIOPIN = temp;
}
// output FF to 1
for(i=0xFF; i!=0;i--)
{
temp=i;
temp = temp << 4;
LPC_GPIO0->FIOPIN = temp;
}
}//End of while(1)
}//End of main()
SQUARE WAVEFORM
void delay(void);
int main ()
{

LPC_PINCON->PINSEL0 &= 0xFF0000FF ;

// Configure P0.4 to P0.11 as GPIO
while(1)
{
LPC_GPIO0->FIOPIN = 0x00000FF0 ;
delay();
LPC_GPIO0->FIOCLR = 0x00000FF0 ;
delay();
}
}
void delay(void)
{
unsigned int i=0;
for(i=0;i<=9500;i++);
}
6) Interface a 4x4 keyboard and display the key code on an LCD.

#include "AN_LCD.h"
unsigned long int temp1=0, temp2=0 ;
//lcd initialization
void lcd_init()
{
/* Ports initialized as GPIO */
LPC_PINCON->PINSEL4 &= 0xFFF000FF; //P2.4 to P2.9
/* Setting the directions as output */

LPC_GPIO2->FIODIR |= DT_CTRL;
LPC_GPIO2->FIODIR |= RS_CTRL;
LPC_GPIO2->FIODIR |= EN_CTRL;
clear_ports();
delay_lcd(3200);
temp2 = (0x30<<2);
wr_cn();
delay_lcd(30000);
temp2 = (0x30<<2);
wr_cn();
delay_lcd(30000);

temp2 = (0x30<<2);
wr_cn();
delay_lcd(30000);
temp2 = (0x20<<2);
wr_cn();
delay_lcd(30000);
temp1 = 0x28;
lcd_com();
delay_lcd(30000);
temp1 = 0x0c;
lcd_com();
delay_lcd(800);
temp1 = 0x06;
lcd_com();
delay_lcd(800);
temp1 = 0x01;
lcd_com();
delay_lcd(10000);
temp1 = 0x80;
lcd_com();
delay_lcd(800);
return;
}
void lcd_com(void)
{
temp2 = temp1 & 0xf0;//move data (26-8+1) times : 26 - HN place, 4 - Bits
temp2 = temp2 << 2;//data lines from 23 to 26
wr_cn();
temp2 = temp1 & 0x0f; //26-4+1
temp2 = temp2 << 6;
wr_cn();
delay_lcd(1000);
return;
}
// command nibble o/p routine

void wr_cn(void) //write command reg
{

clear_ports();
LPC_GPIO2->FIOCLR = RS_CTRL; // clear bit RS
delay_lcd(25);
return;
// data o/p routine which also outputs high nibble first

// and lower nibble next
void lcd_data(void)
{
temp2 = temp1 & 0xf0;
temp2 = temp2 << 2;
wr_dn();
temp2= temp1 & 0x0f;
temp2= temp2 << 6;
wr_dn();
delay_lcd(1000);
return;
}
// data nibble o/p routine

void wr_dn(void)
{
clear_ports();

LPC_GPIO2->FIOSET = RS_CTRL; // set bit RS
delay_lcd(25);
return;
}
void delay_lcd(unsigned int r1)

{
unsigned int r;
for(r=0;r<r1;r++);
return;
}
void clr_disp(void)
{

temp1 = 0x01;
lcd_com();
delay_lcd(10000);
return;
}
void clear_ports(void)
{
/* Clearing the lines at power on */
LPC_GPIO2->FIOCLR = DT_CTRL; //Clearing data lines
LPC_GPIO2->FIOCLR = RS_CTRL; //Clearing RS line
LPC_GPIO2->FIOCLR = EN_CTRL; //Clearing Enable line
return;
}
void lcd_puts(unsigned char *buf1)

{
unsigned int i=0;
while(buf1[i]!='\0')
{
temp1 = buf1[i];
lcd_data();
i++;
if(i==16)
{
temp1 = 0xc0;
lcd_com();
}
}
return;
}

7) Using the Internal PWM module of ARM controller generate PWM and vary its
duty cycle.
void pwm_init(void);
void PWM1_IRQHandler(void);
unsigned long int i;

unsigned char flag,flag1;
int main(void)
{
SystemInit();
pwm_init();
while(1)
{
for(i=0;i<=1000;i++); // delay
}//end of while
}//end of main
void pwm_init(void)
{
LPC_SC->PCONP |= (1<<6); //PWM1 is powered
LPC_PINCON->PINSEL7 |= 0x000C0000; //pwm1.2 is selected for the pin P3.25
LPC_PWM1->PR = 0x00000000; //Count frequency : Fpclk

LPC_PWM1->PCR = 0x00000400; //select PWM2 single edge

LPC_PWM1->MCR = 0x00000003; //Reset and interrupt on PWMMR0
LPC_PWM1->MR0 = 30000; //setup match register 0 count
LPC_PWM1->MR2 = 0x00000100; //setup match register MR1
LPC_PWM1->LER = 0x000000FF; //enable shadow copy register
LPC_PWM1->TCR = 0x00000002; //RESET COUNTER AND PRESCALER
LPC_PWM1->TCR = 0x00000009; //enable PWM and counter
NVIC_EnableIRQ(PWM1_IRQn);
return;
}
void PWM1_IRQHandler(void)
{
LPC_PWM1->IR = 0xff; //clear the interrupts
if(flag == 0x00)
{
LPC_PWM1->MR2 += 100;
LPC_PWM1->LER = 0x000000FF;
if(LPC_PWM1->MR2 >= 27000)

{
flag1 = 0xff;
flag = 0xff;
}
}
else if(flag1 == 0xff)
{
LPC_PWM1->MR2 -= 100;
if(LPC_PWM1->MR2 <= 0x500)

{
flag = 0x00;
flag1 = 0x00;
LPC_PWM1->LER = 0X000000fF;
}
}
}

8) Demonstrate the use of an external interrupt to toggle an LED On/Off.
#include<LPC17xx.h>
void EINT3_IRQHandler(void);
unsigned char int3_flag=0;
int main(void)
{
unsigned char flag=0;
SystemInit();
LPC_PINCON->PINSEL4 |= 0x04000000; //P2.13 as EINT3
LPC_PINCON->PINSEL4 &= 0xFCFFFFFF; //P2.12 GPIO for

LED
LPC_GPIO2->FIODIR = 0x00001000; //P2.12 is assigned
output
LPC_GPIO2->FIOSET = 0x00001000; //Initiall LED is kept
on
LPC_SC->EXTINT = 0x00000008; //writing 1 cleares the

interrupt, get set if there is interrupt
LPC_SC->EXTMODE = 0x00000008; //EINT3 is initiated as
edge senitive, 0 for level sensitive
LPC_SC->EXTPOLAR = 0x00000000; //EINT3 is falling
edge sensitive, 1 for rising edge

//above
registers, bit0-EINT0, bit1-EINT1, bit2-EINT2,bit3-EINT3
NVIC_EnableIRQ(EINT3_IRQn); //core_cm3.h
while(1)
{
while(int3_flag == 0x00); //wait till interrupt
int3_flag = 0x00;
if(flag == 0x00) //when flag is '0' off

the LED
{
LPC_GPIO2->FIOCLR = 0x00001000;
flag = 0xFF;
} //when
flag is FF on the LED
else
{
LPC_GPIO2->FIOSET = 0x00001000;
flag = 0x00;
}
}
}
void EINT3_IRQHandler(void)
{
int3_flag = 0xff;
LPC_SC->EXTINT = 0x00000008; //cleares the interrupt
}

9) Display the Hex digits 0 to F on a 7-segment LED interface, with an appropriate delay
in between.
unsigned int delay, count=0, Switchcount=0,j;
unsigned int Disp[16]={0x000003f0, 0x00000060, 0x000005b0, 0x000004f0,

0x00000660,0x000006d0,
0x000007d0, 0x00000070, 0x000007f0, 0x000006f0,
0x00000770,0x000007c0,
0x00000390, 0x000005e0, 0x00000790, 0x00000710 };
#define ALLDISP 0x00180000 //Select all display

#define DATAPORT 0x00000ff0 //P0.16 to P0.23 : Data lines
connected to drive Seven Segments
int main (void)

{
LPC_PINCON->PINSEL0 = 0x00000000;
LPC_PINCON->PINSEL1 = 0x00000000;
LPC_GPIO0->FIODIR = 0x00180ff0;
while(1)
{
LPC_GPIO0->FIOSET |= ALLDISP;
LPC_GPIO0->FIOCLR = 0x00000ff0; // clear the data lines to 7-
segment displays
LPC_GPIO0->FIOSET = Disp[Switchcount]; // get the 7-segment display
value from the array
for(j=0;j<3;j++)

for(delay=0;delay<30000;delay++); // 1s delay
Switchcount++;
if(Switchcount == 0x10) // 0 to F has been displayed ? go
back to 0
{
Switchcount = 0;
LPC_GPIO0->FIOCLR = 0x00180ff0;
}
}
}
10) Interface a simple Switch and display its status through Relay, Buzzer and LED.
unsigned int count=0;
int main(void)
{
unsigned int i;
SystemInit();

LPC_PINCON->PINSEL1 &= 0xFFF0FFFF; //P0.25 GPIO

while(1)
{
if(!(LPC_GPIO2->FIOPIN & 0x00000800))
{
for(i=0;i<10;i++)
{
LPC_GPIO0->FIOSET = 0x03000000; //relay on
for(i=0;i<10000;i++);
}
else
{
LPC_GPIO0->FIOCLR = 0x03000000; //relay off
for(i=0;i<100000;i++);
}
}
} //end
int main(void)
11) Measure Ambient temperature using a sensor and SPI ADC IC.

#include "SPI.h"
unsigned char spi_flag = 0, temp=0;
void SPI_Init(void)
{
// LPC_SC->PCONP |= (1<<8); //Enable the peripheral SPI
LPC_PINCON->PINSEL0 |= 0xC0000000; //P0.15 as SCK
LPC_PINCON->PINSEL1 |= 0x0000003C; //select MISO-P0.17,MOSI-P0.18
LPC_SPI->SPCCR = 0x1E; // SPI CLOCK SELECTED AS 100KHZ

LPC_SPI->SPCR = 0xA0; //8 bit data, actve high clk, master SPI mode,SPI Int enable
// Master mode and SCK line is active high
LPC_SPI->SPINT = 0x01; //clear the interrupt flag
NVIC_EnableIRQ(SPI_IRQn);
}
void SPI_IRQHandler(void)
{
spi_flag = 1;
temp = LPC_SPI->SPSR; // To clear SPIF bit we have to read status register.
temp = LPC_SPI->SPDR; // Then read the data register(optional)
LPC_SPI->SPINT = 0x01; // To clear the SPI interrupt
}

Geetha Shishu Shikshana Sangha (R)
GSSS INSTITUTE OF ENGINEERING AND TECHNOLOGY FOR WOMEN
(Affiliated to VTU, Belagavi, Approved by AICTE, New Delhi & Govt. of Karnataka)
KRS Road, Metagalli, Mysuru 570 016, Karnataka, India
INSTITUTION VISION&MISSION
VISION
To become a recognized world class Women Educational Institution, by imparting
professional education to the students, creating technical opportunities through academic
excellence and technical achievements, with ethical values.
MISSION
M1. To support value based education with state of art infrastructure.
M2. To empower women with the additional skill for professional future carrier.
M3. To enrich students with research blends in order to fulfill the International challenges.
M4. To create multidisciplinary center of excellence.
M5. To achieve Accreditation standards towards intentional education recognition.
M6. To establish more Post Graduate & Research course.
M7. To increase Doctorates numbers towards the Research quality of academics.
Vision of the Institute
“To become a recognized world class women educational institution, by imparting professional
education to the students, creating technical opportunities through academic excellence and
technical achievements, with ethical values”
Mission of the Institute
M1: To support value based education with state of art infrastructure.
M2: To empower women with the additional skill for professional future career
M3: To enrich students with research blends in order to fulfill the International challenges
M4: To create multidisciplinary center of excellence
M5: To achieve Accreditation standards towards International education recognition.
M6: To establish more Post Graduate & Research courses.
M7: To increase Doctorates numbers towards the Research quality of academics.

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Geetha Shishu Shikshana Sangha(R)

GSSS INSTITUTE OF ENGINEERING AND TECHNOLOGY

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

EMBEDDED CONTROLLER LAB (15ECL67)

Smt Thilagavathy R , Assistant Professor, Dept of ECE, GSSSIETW,Mysuru

Mission of the Department:

M1: To impart value based Technical education and training.

M2: To impart Theoretical Knowledge, Practical Knowledge and Entrepreneurship Skills.

M3: To develop Innovation and Creativity in Students.

M4: To conduct Application oriented research.

M6: To provide sufficient Industry exposure to the Students.

PROGRAM EDUCATIONAL OBJECTIVES

PEO4: To prepare the students to be able to exhibit professionalism, ethical attitude,

Engineering Graduates will be able to:

1. Engineering knowledge: Apply the knowledge of mathematics, science, engineering

Program Specific Outcomes

PSO2. Implementation of functional Blocks of hardware software co-design for signal

Subject Code: 15ECL67 I.A. Marks: 20

using an Evaluation board and the required software tool.

1. ALP to multiply two 16 bit binary numbers.

2. ALP to find the sum of first 10 integer numbers.

evaluation version of Embedded 'C' & Keil Uvision-4 tool/compiler.

1. Display “Hello World” message using Internal UART.

2. Interface and Control a DC Motor.

3. Interface a Stepper motor and rotate it in clockwise and anti-clockwise direction.

5. Interface a DAC and generate Triangular and Square waveforms.

6. Interface a 4x4 keyboard and display the key code on an LCD.

8. Demonstrate the use of an external interrupt to toggle an LED On/Off.

1. Check the components before you start the experiment.

1. INTRODUCTION TO ARM CORTEX M3 PROCESSOR

A simplified block diagram of the Cortex-m3 architecture is shown below

Dept. of ECE, GSSSIETW, Mysuru Page 1

1.2 Background of ARM architecture

1.3 Architecture versions

Dept. of ECE, GSSSIETW, Mysuru Page 2

In this version, the architecture design is divided into three profiles:

Bit more details on these profiles

Dept. of ECE, GSSSIETW, Mysuru Page 3

Below figure shows the development stages of ARM versions

1.4 Instruction Set Development

1.4.1 The Thumb-2 Technology and Instruction Set Architecture

1.5 Advantages of Cortex M3 processors

Dept. of ECE, GSSSIETW, Mysuru Page 5

1.6 Applications of Cortex M3 processors

Dept. of ECE, GSSSIETW, Mysuru Page 6

2. INTRODUCTION TO MICRO CONTROLLER LPC1768

Dept. of ECE, GSSSIETW, Mysuru Page 7

Dept. of ECE, GSSSIETW, Mysuru Page 8

2.2 Block Diagram of LPC1768FBD10

2.3 A brief description of the blocks:

Dept. of ECE, GSSSIETW, Mysuru Page 9

Nested vector interrupt controller

Dept. of ECE, GSSSIETW, Mysuru Page 10

Dept. of ECE, GSSSIETW, Mysuru Page 11

Dept. of ECE, GSSSIETW, Mysuru Page 12

Dept. of ECE, GSSSIETW, Mysuru Page 13

Clock generation block diagram for LPC1768 is shown below

Dept. of ECE, GSSSIETW, Mysuru Page 14

3. TECHNICAL SPECIFICATIONS of LPC1768