35080
35080
35080
D Q
Table 1. Signal Names
C
C Serial Clock M35080
S
D Serial Data Input
W
Q Serial Data Output
S Chip Select
W Write Protect
VSS
VCC Supply Voltage
AI02143
VSS Ground
2/18
M35080
0 or 1 0 Software Writeable (if the WREN Software write protected Writeable (if the WREN
Protected instruction has set the by the BP0 and BP1 bits instruction has set the
1 1 (SPM) WEL bit) of the status register WEL bit)
(though not to the WIP and WEL bits, which are It is possible to enter the Hardware Protected
set or reset by the devices internal logic). Mode (HPM) either by setting the SRWD bit after
Bit 7 of the status register (as shown in Table 4) is pulling low the W pin, or by pulling low the W pin
the Status Register Write Disable bit (SRWD). after setting the SRWD bit.
When this is set to 0 (its initial delivery state) it is The only way to abort the Hardware Protected
possible to write to the status register if the WEL Mode, once entered, is to pull high the W pin.
bit (Write Enable Latch) has been set by the If W pin is permanently tied to the high level, the
WREN instruction (irrespective of the level being Hardware Protected Mode is never activated, and
applied to the W input). the memory device only allows the user to protect
When bit 7 (SRWD) of the status register is set to a part of the memory, using the BP1 and BP0 bits
1, the ability to write to the status register depends of the status register, in the Software Protected
on the logic level being presented at pin W: Mode (SPM).
If W pin is high, it is possible to write to the sta- IMPORTANT: if W pin is left floating, not driven by
tus register, after having set the WEL bit using the application, W is read as a logical 0.
the WREN instruction (Write Enable Latch).
If W pin is low, any attempt to modify the status
register is ignored by the device, even if the
WEL bit has been set. As a consequence, all the
data bytes in the EEPROM area, protected by Table 4. Status Register Format
the BP1 and BP0 bits of the status register, are b7 b0
also hardware protected against data corrup-
tion, and appear as a Read Only EEPROM area SRWD UV X INC BP1 BP0 WEL WIP
for the microcontroller. This mode is called the Note: 1. BP0, BP1: Read and write bits
Hardware Protected Mode (HPM). 2. UV, INC, WEL, WIP: Read only bits.
3. SRWD: Read and Write bit.
CPOL CPHA
0 0 C
1 1 C
D or Q MSB LSB
AI01438
3/18
M35080
Master
(ST6, ST7, ST9, C Q D C Q D C Q D
ST10, Others)
M35xxx M35xxx M35xxx
AI02148C
4/18
M35080
0 1 2 3 4 5 6 7 8 9 10 20 21 22 23 24 25 26 27 28 29 30
D 15 14 13 3 2 1 0
DATA OUT
HIGH IMPEDANCE
Q 7 6 5 4 3 2 1 0
MSB
AI01793
Note: 1. The most significant address bits, A15-A10, are treated as Dont Care.
The latch becomes reset by any of the following A single, prolonged RDSR instruction
events: (consisting of S being taken low, C being
Power on clocked 8 times for the instruction and kept
WRDI instruction completion running for repeated read operations), as
WRSR instruction completion shown in Figure 6.
WRITE instruction completion. The Write-In-Process (WIP) bit is read-only, and
As soon as the WREN or WRDI instruction is re- indicates whether the memory is busy with a Write
ceived, the memory device first executes the in- operation. A 1 indicates that a write is in progress,
struction, then enters a wait mode until the device and a 0 that no write is in progress.
is deselected. The Write Enable Latch (WEL) bit indicates the
Read Status Register (RDSR) status of the write enable latch. It, too, is read-only.
The RDSR instruction allows the status register to Its value can only be changed by one of the events
be read, and can be sent at any time, even during listed earlier, or as a result of executing WREN or
a Write operation. Indeed, when a Write is in WRDI instruction. It cannot be changed using a
progress, it is recommended that the value of the WRSR instruction. A 1 indicates that the latch is
Write-In-Progress (WIP) bit be checked. The value set (the forthcoming Write instruction will be exe-
in the WIP bit (whose position in the status register cuted), and a 0 that it is reset (and any forthcom-
is shown in Table 4) can be continuously polled, ing Write instructions will be ignored).
before sending a new WRITE instruction. This can The Block Protect (BP0 and BP1) bits indicate the
be performed in one of two ways: amount of the memory that is to be write-protect-
Repeated RDSR instructions (each one
ed. These two bits are non-volatile. They are set
using a WRSR instruction.
consisting of S being taken low, C being clocked
During a Write operation (whether it be to the
8 times for the instruction and 8 times for the
memory area or to the status register), all bits of
read operation, and S being taken high) the status register remain valid, and can be read
using the RDSR instruction. However, during a
Write operation, the values of the non-volatile bits
5/18
M35080
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
INSTRUCTION
AI02031
(SRWD, BP0, BP1) become frozen at a constant the 16 th clock pulse, and before the rising edge of
value. The updated value of these bits becomes the 17th clock (as indicated in Figure 7), otherwise
available when a new RDSR instruction is execut- the internal write sequence is not performed.
ed, after completion of the write cycle. On the oth- The WRSR instruction is used for the following:
er hand, the two read-only bits (WEL, WIP) are
to select the size of memory area that is to be
dynamically updated during internal write cycles.
Using this facility, it is possible to poll the WIP bit write-protected
to detect the end of the internal write cycle. to select between SPM (Software Protected
The Comparator bit (INC) indicates if the new val- Mode) and HPM (Hardware Protected Mode).
ue written in the 16 first word is lower 1 or higher
The size of the write-protection area applies equal-
0 than the previous stored value.
ly in SPM and HPM. The BP1 and BP0 bits of the
The UV bit indicates if the memory chip has been status register have the appropriate value (see Ta-
erased. ble 7) written into them after the contents of the
Write Status Register (WRSR) protected area of the EEPROM have been written.
The format of the WRSR instruction is shown in The initial delivery state of the BP1 and BP0 bits is
Figure 7. After the instruction and the eight bits of 00, indicating a write-protection size of 0.
the status register have been latched-in, the inter-
nal Write cycle is triggered by the rising edge of
the S line. This must occur after the falling edge of
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
D 7 6 5 4 3 2 1 0
MSB
HIGH IMPEDANCE
Q
AI01797
6/18
M35080
0 0 none 1 none 1
0 1 Upper quarter 0300h - 03FFh
1 0 Upper half 0200h - 03FFh
Note: 1. Except for the first sixteen pairs of bytes (see Table 6).
Software Protected Mode (SPM) An alternative method is to write the protected da-
The act of writing a non-zero value to the BP1 and ta, and to set the BP1, BP0 and SRWD bits, before
BP0 bits causes the Software Protected Mode soldering the memory device to the board. Again,
(SPM) to be started. All attempts to write a byte or this results in the memory device being placed in
page in the protected area are ignored, even if the its hardware protected mode.
Write Enable Latch is set. However, writing is still If the W pin has been connected to V SS by a pull-
allowed in the unprotected area of the memory ar- down resistor, the memory device can be taken
ray and to the SRWD, BP1 and BP0 bits of the sta- out of the hardware protected mode by driving the
tus register, provided that the WEL bit is first set. W pin high, to override the pull-down resistor.
Hardware Protected Mode (HPM) If the W pin has been directly soldered to V SS,
The Hardware Protected Mode (HPM) offers a there is only one way of taking the memory device
higher level of protection, and can be selected by out of the hardware protected mode: the memory
setting the SRWD bit after pulling down the W pin device must be de-soldered from the board, and
or by pulling down the W pin after setting the connected to external equipment in which the W
SRWD bit. The SRWD is set by the WSR instruc- pin is allowed to be taken high.
tion, provided that the WEL bit is first set. The set- Read Operation
ting of the SRWD bit can be made independently The chip is first selected by holding S low. The se-
of, or at the same time as, writing a new value to rial one byte read instruction is followed by a two
the BP1 and BP0 bits. byte address (A15-A0), each bit being latched-in
Once the device is in the Hardware Protected during the rising edge of the clock (C). The data
Mode, the data bytes in the protected area of the stored in the memory, at the selected address, is
memory array, and the content of the status regis- shifted out on the Q output pin. Each bit is shifted
ter, are write-protected. The only way to re-enable out during the falling edge of the clock (C) as
writing new values to the status register is to pull shown in Figure 5.
the W pin high. This cause the device to leave the The internal address counter is automatically in-
Hardware Protected Mode, and to revert to being cremented to the next higher address after each
in the Software Protected Mode. (The value in the byte of data has been shifted out. The data stored
BP1 and BP0 bits will not have been changed). in the memory, at the next address, can be read by
Further details of the operation of the Write Protect successive clock pulses. When the highest ad-
pin (W) are given earlier, on page 2. dress is reached, the address counter rolls over to
Typical Use of HPM and SPM 0000h, allowing the read cycle to be continued
indefinitely. The read operation is terminated by
The W pin can be dynamically driven by an output
deselecting the chip. The chip can be deselected
port of a microcontroller. It is also possible,
at any time during data output. If a read instruction
though, to connect it permanently to V SS (by a sol- is received during a write cycle, it is rejected, and
der connection, or through a pull-down resistor).
the memory device deselects itself.
The manufacturer of such a printed circuit board
can take the memory device, still in its initial deliv- Byte Write Operation
ery state, and can solder it directly on to the board. Before any write can take place, the WEL bit must
After power on, the microcontroller can be instruct- be set, using the WREN instruction, as shown in
ed to write the protected data into the appropriate Figure 8. The write state is entered by selecting
area of the memory. When it has finished, the ap- the chip, issuing three bytes of instruction and ad-
propriate values are written to the BP1, BP0 and dress, and one byte of data. Chip Select (S) must
SRWD bits, thereby putting the device in the hard- remain low throughout the operation, as shown in
ware protected mode. Figure 9. The device must be deselected just after
the eighth bit of the data byte has been latched in,
7/18
M35080
0 1 2 3 4 5 6 7
HIGH IMPEDANCE
Q
AI01794
as shown in Figure 9, otherwise the write process deselected, by taking S high for at least t SHSL. The
is cancelled. As soon as the memory device is de- device sets the write enable latch, and remains in
selected, the self-timed internal write cycle is initi- its stand-by state, until it is deselected. Then the
ated. While the write is in progress, the status write state is entered by selecting the chip, by tak-
register may be read to check the status of the SR- ing S low. The WRINC instruction is issued, and
WD, BP1, BP0, WEL and WIP bits. In particular, the address is sent (always an even address, with
WIP contains a 1 during the self-timed write cy- A0=0) along with two bytes of data. The Chip Se-
cle, and a 0 when the cycle is complete, (at which lect input (S) must remain low for the entire dura-
point the write enable latch is also reset). tion of the operation.
Write Data In the Incremental Registers The device must be deselected just after the
Due to the special control on the first page of the eighth bit of the second data byte has been
memory, the byte write operation is not usable on latched in. Otherwise, the write process is can-
the first 32 bytes. Instead, the WRINC instruction celled. As a further protection, the WRINC instruc-
must be used, the timing of which is shown in Fig- tion is cancelled if its duration is not exactly equal
ure 10. to 40 clock pulses.
Prior to any write attempt, the write enable latch As soon as the device is deselected, the self-timed
must be set by issuing the WREN instruction. First write cycle is initiated. While the write is in
the device is selected (by taking S low) and a seri- progress, the status register may be read, to check
al WREN instruction is issued. Then the device is the values of the UV, INC, BP1, BP0, WEL and
0 1 2 3 4 5 6 7 8 9 10 20 21 22 23 24 25 26 27 28 29 30 31
D 15 14 13 3 2 1 0 7 6 5 4 3 2 1 0
HIGH IMPEDANCE
Q
AI01795
Note: 1. The most significant address bits, A15-A10, are treated as Dont Care.
8/18
M35080
0 1 2 3 4 5 6 7 8 9 10 20 21 22 23 24 25 26 27 28 29 30 31
D 15 14 13 3 2 1 0 7 6 5 4 3 2 1 0
32 33 34 35 36 37 38 39
DATA BYTE 2
D 7 6 5 4 3 2 1 0
AI02146B
Note: 1. The most significant address bits, A15-A10, are treated as Dont Care.
WIP bits. WIP is high during the self-timed write correctly formulated commands. The main securi-
cycle. When the cycle is completed, the write en- ty measures can be summarized as follows:
able latch is reset. The WEL bit is reset at power-up.
Page Write Operation S must rise after the eighth clock count (or mul-
A maximum of 32 bytes of data can be written dur- tiple thereof) in order to start a non-volatile write
ing one Write time, tW, provided that they are all to cycle (in the memory array or in the status reg-
the same page (see Figure 11). The Page Write ister).
operation is the same as the Byte Write operation, Accesses to the memory array are ignored dur-
except that instead of deselecting the device after ing the non-volatile programming cycle, and the
the first byte of data, up to 31 additional bytes can programming cycle continues unaffected.
be shifted in (and the device is deselected after the
After execution of a WREN, WRDI, or RDSR in-
last byte).
struction, the device enters a wait state, and
Any address of the memory can be chosen as the waits to be deselected.
first address to be written. If the address counter
Invalid S transitions are ignored.
reaches the end of the page (an address of the
form xxxx xxxx xxx1 1111) and the clock contin-
ues, the counter rolls over to the first address of
the same page (xxxx xxxx xxx0 0000) and over-
writes any previously written data.
As before, the Write cycle only starts if the S tran-
sition occurs just after the eighth bit of the last data
byte has been received, as shown in Figure 12.
9/18
M35080
W High Voltage
Control Logic Generator
S
D
I/O Shift Register
Q
Status
Register
An - 31 An Size of the
Read only
EEPROM
area
Y Decoder
32 Bytes
X Decoder
AI02145C
10/18
M35080
0 1 2 3 4 5 6 7 8 9 10 20 21 22 23 24 25 26 27 28 29 30 31
D 15 14 13 3 2 1 0 7 6 5 4 3 2 1 0
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
D 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 6 5 4 3 2 1 0
AI01796
Note: 1. The most significant address bits, A15-A10, are treated as Dont Care.
2. The number of clock pulses must be a multiple of 8. Otherwise, the write is aborted.
11/18
M35080
Table 9. DC Characteristics
(TA = 0 to 70C, 40 to 85C or 40 to 125C; VCC = 4.5V to 5.5V)
Symbol Parameter Test Condition Min Max Unit
ILI Input Leakage Current 2 A
12/18
M35080
13/18
M35080
tSHSL
tDVCH tCHCL
tCHDX tCLCH
D MSB IN LSB IN
tDLDH
tDHDL
HIGH IMPEDANCE
Q
AI01447
tCH
tCLQX
Q LSB OUT
tQLQH
tQHQL
D ADDR.LSB IN
AI01449B
14/18
M35080
ORDERING INFORMATION
The notation used for the device number is as
shown in Table 13. For a list of available options
(speed, package, etc.) or for further information on
any aspect of this device, please contact the ST
Sales Office nearest to you.
Example: M35080 MN 6 T
Package
BN PSDIP8 (0.25 mm frame)
MN SO8 (150 mil width)
15/18
M35080
Table 14. PSDIP8 - 8 pin Plastic Skinny DIP, 0.25mm lead frame
mm inches
Symb.
Typ. Min. Max. Typ. Min. Max.
A 3.90 5.90 0.154 0.232
A1 0.49 0.019
A2 3.30 5.30 0.130 0.209
B 0.36 0.56 0.014 0.022
B1 1.15 1.65 0.045 0.065
C 0.20 0.36 0.008 0.014
D 9.20 9.90 0.362 0.390
E 7.62 0.300
E1 6.00 6.70 0.236 0.264
e1 2.54 0.100
eA 7.80 0.307
eB 10.00 0.394
L 3.00 3.80 0.118 0.150
N 8 8
A2 A
A1 L
B e1 C
B1 eA
D eB
E1 E
1
PSDIP-a
16/18
M35080
Table 15. SO8 - 8 lead Plastic Small Outline, 150 mils body width
mm inches
Symb.
Typ. Min. Max. Typ. Min. Max.
A 1.35 1.75 0.053 0.069
A1 0.10 0.25 0.004 0.010
B 0.33 0.51 0.013 0.020
C 0.19 0.25 0.007 0.010
D 4.80 5.00 0.189 0.197
E 3.80 4.00 0.150 0.157
e 1.27 0.050
H 5.80 6.20 0.228 0.244
h 0.25 0.50 0.010 0.020
L 0.40 0.90 0.016 0.035
0 8 0 8
N 8 8
CP 0.10 0.004
h x 45
A
C
B
e CP
E H
1
A1 L
SO-a
17/18
M35080
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of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
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authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
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18/18
This datasheet has been downloaded from:
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