M93C86, M93C76, M93C66

M93C56, M93C46, M93C06

16K/8K/4K/2K/1K/256 (x8/x16) Serial Microwire Bus EEPROM

PRELIMINARY DATA

INDUSTRY STANDARD MICROWIRE BUS

1 MILLION ERASE/WRITE CYCLES, with
40 YEARS DATA RETENTION
DUAL ORGANIZATION: by WORD (x16) or by
BYTE (x8)
8 8
BYTE/WORD and ENTIRE MEMORY
PROGRAMMING INSTRUCTIONS
1 1
SELF-TIMED PROGRAMMING CYCLE with
AUTO-ERASE PSDIP8 (BN) SO8 (MN)
READY/BUSY SIGNAL DURING 0.25mm Frame 150mil Width
PROGRAMMING
SINGLE SUPPLY VOLTAGE:
– 4.5V to 5.5V for M93Cx6 version
– 2.5V to 5.5V for M93Cx6-W version
– 1.8V to 3.6V for M93Cx6-R version
Figure 1. Logic Diagram
SEQUENTIAL READ OPERATION
5ms TYPICAL PROGRAMMING TIME
ENHANCED ESD/LATCH-UP
PERFORMANCES

DESCRIPTION
This M93C86/C76/C66/C56/C46/C06 specifica-
tion covers a range of 16K/8K/4K/2K/1K/256 bit VCC
serial EEPROM products respectively. In this text,
products are referred to as M93Cx6. The M93Cx6
is an Electrically Erasable Programmable Memory
(EEPROM) fabricated with STMicroelectronics’s D Q
High Endurance Single Polysilicon CMOS technol-
ogy. The M93Cx6 memory is accessed through a C
serial input (D) and output (Q) using the MI- M93Cx6
CROWIRE bus protocol. S

ORG
Table 1. Signal Names
S Chip Select Input
VSS
D Serial Data Input
AI01928

Q Serial Data Output

C Serial Clock

ORG Organisation Select

VCC Supply Voltage

VSS Ground

November 1998 1/18

This is preliminary information on a new product now in developmentor undergoing evaluation . Detail s are subject to change without notice.
M93C86, M93C76, M93C66, M93C56, M93C46, M93C06

Figure 2A. DIP and SO Pin Connections Figure 2B. SO 90° Turn Pin Connections

M93Cx6 M93Cx6

S 1 8 VCC DU 1 8 ORG
C 2 7 DU VCC 2 7 VSS
D 3 6 ORG S 3 6 Q
Q 4 5 VSS C 4 5 D
AI01929B AI00900

Warning: DU = Don’t Use Warning: DU = Don’t Use

Table 2. Absolute Maximum Ratings (1)

Symbol Parameter Value Unit

TA Ambient Operating Temperature –40 to 125 °C

TSTG Storage Temperature –65 to 150 °C

TLEAD Lead Temperature, Soldering (SO8 package) 40 sec 215

°C
(PSDIP8 package) 10 sec 260
VIO Input or Output Voltages (Q = VOH or Hi-Z) –0.3 to VCC +0.5 V

VCC Supply Voltage –0.3 to 6.5 V

Electrostatic Discharge Voltage (Human Body model) (2) 4000 V

VESD
(3)
Electrostatic Discharge Voltage (Machine model) 500 V
Notes: 1. Except for the rating ”Operating Temperature Range”, stresses above those listed in the Table ”Absolute Maximum Ratings”
may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other
conditions above those indicated in the Operating sections of this specification is not i mplied. Exposure to Absolute Maximum
Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other
relevant quality documents.
2. MIL-STD-883C, 3015.7 (100pF, 1500 Ω).
3. EIAJ IC-121 (Condition C) (200pF, 0 Ω).

DESCRIPTION (cont’d) Write a Byte/Word, Erase a Byte/Word, Erase All

and Write All. A Read instructionloads the address
The M93Cx6 specified at 5V±10%, the M93Cx6-W of the first byte/word to be read into an internal
specified at 2.5V to 5.5V and the M93Cx6-R speci- addresspointer. The data contained at this address
fied at 1.8V to 3.6V. is then clocked out serially. The address pointer is
The M93Cx6 memory array organization may be automatically incremented after the data is output
divided into either bytes (x8) or words (x16) which and, if the Chip Select input (S) is held High, the
may be selected by a signal applied on the ORG M93Cx6 can output a sequential stream of data
input. The M93C86/C76/C66/C56/C46/C06 is di- bytes/words. In this way, the memory can be read
vided into either 2048/1024/512/256/128/32x8 bit as a data stream from 8 up to 16,384 bits long (for
bytes or 1024/512/256/128/64/16 x16 bit words the M93C86 only), or continuously as the address
respectively. These memory devices are available counter automatically rolls over to ’00’ when the
in both PSDIP8 and SO8 package. highest address is reached.
The M93Cx6 memory is accessed by a set of Programming is internally self-timed (the external
instructions which includes Read a Byte/Word, clock signal on C input may be disconnectedor left

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 M93C86, M93C76, M93C66, M93C56, M93C46, M93C06

Table 3. AC Measurement Conditions

Input Rise and Fall Times ≤ 50ns
Input Pulse Voltages (M93Cxx) 0.4V to 2.4V
Input Pulse Voltages (M93Cxx-W, M93Cxx-R) 0.2VCC to 0.8V CC
Input Timing Reference Voltages (M93Cxx) 1.0V to 2.0V

Output Timing Reference Voltages (M93Cxx) 0.8V to 2.0V

Input and Output Timing Reference Voltages (M93Cxx-W, M93Cxx-R) 0.3VCC to 0.7V CC

Output Load CL = 100pF

Note that Output Hi-Z is defined as the point where data is no longer driven.

Figure 3. AC Testing Input Output Waveforms be left unconnected or may be connected to VCC
or VSS. Direct connection of DU to VSS is recom-
mended for the lowest standby power consump-
tion.
M93CXX
2.4V MEMORY ORGANIZATION
2V 2.0V
The M93Cx6 is organised in either bytes (x8) or
1V 0.8V words (x16). If the ORG input is left unconnected
0.4V
INPUT OUTPUT
(or connected to VCC) the x16 organization is se-
lected; when ORG is connected to Ground (V SS)
M93CXX-W & M93CXX-R
the x8 organization is selected. When the M93Cx6
0.8VCC
is in standby mode, the ORG input should be set
0.7VCC to either VSS or VCC in order to achieve minimum
power consumption.Any voltage between VSS and
0.2VCC VCC applied to the ORG input pin may increase the
0.2VCC
standby current value.
AI02553

POWER-ON DATA PROTECTION

In order to prevent data corruption and inadvertent
write operations during power-up, a Power On
running after the start of a Write cycle) and does Reset (POR)circuit resets all internal programming
not require an erase cycle prior to the Write instruc- circuitry and sets the device in the Write Disable
tion. The Write instruction writes 8 or 16 bits at one mode.
time into one of the byte or word locations of the – At Power-up and Power-down, the device must
M93Cx6. After the start of the programming cycle, NOT be selected (that is, the S input must be
a Busy/Readysignal is availableon the Data output driven low) until the supply voltage reaches the
(Q) when Chip Select (S) is driven High. operating value VCC specified in the AC and DC
An internal feature of the M93Cx6 provides Power- tables.
on Data Protection by inhibiting any operation – When VCC reaches its functional value, the de-
when the Supply is too low for reliable operation. vice is properly reset (in the Write Disable mode)
The design of the M93Cx6 and the High Endurance and is ready to decode and execute an incoming
CMOS technology used for its fabrication give an instruction.
Erase/Write cycle Endurance of 1,000,000 cycles For the M93Cx6 specifiedat 5V,the POR threshold
and a data retention of 40 years. voltage is around 3V. For all the other M93Cx6
The DU (Don’t Use) pin does not affect the function specified at low VCC (with -W and -R VCC range
of the memory. It is reserved for use by STMi- options),the POR threshold voltageis around1.5V.
croelectronics during test sequences. The pin may

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M93C86, M93C76, M93C66, M93C56, M93C46, M93C06

Table 4. Capacitance (1)

(TA = 25 °C, f = 1 MHz )
Symbol Parameter Test Condition Min Max Unit

CIN Input Capacitance VIN = 0V 5 pF

C OUT Output Capacitance VOUT = 0V 5 pF
Note: 1. Sampled only, not 100% tested.

Table 5A. DC Characteristics for M93CXX

(TA = 0 to 70°C or –40 to 85°C; VCC = 4.5V to 5.5V)
Symbol Parameter Test Condition Min Max Unit
ILI Input Leakage Current 0V ≤ VIN ≤ VCC ±2.5 µA
ILO Output Leakage Current 0V ≤ VOUT ≤ VCC, Q in Hi-Z ±2.5 µA
ICC Supply Current VCC = 5V, S = VIH, f = 1 MHz 1.5 mA
VCC = 5V, S = VSS, C = VSS ,
ICC1 Supply Current (Standby) 50 µA
ORG = VSS or VCC

VIL Input Low Voltage (D, C, S) VCC = 5V ± 10% –0.3 0.8 V

VIH Input High Voltage (D, C, S) VCC = 5V ± 10% 2 VCC + 1 V

VOL Output Low Voltage (Q) VCC = 5V, IOL = 2.1mA 0.4 V
VOH Output High Voltage (Q) VCC = 5V, IOH = –400µA 2.4 V

Table 5B. DC Characteristics for M93CXX

(TA = –40 to 125°C; VCC = 4.5V to 5.5V)
Symbol Parameter Test Condition Min Max Unit
ILI Input Leakage Current 0V ≤ VIN ≤ VCC ±2.5 µA
ILO Output Leakage Current 0V ≤ VOUT ≤ VCC, Q in Hi-Z ±2.5 µA
ICC Supply Current VCC = 5V, S = VIH, f = 1 MHz 1.5 mA

VCC = 5V, S = VSS, C = VSS ,

ICC1 Supply Current (Standby) 50 µA
ORG = VSS or VCC
VIL Input Low Voltage (D, C, S) VCC = 5V ± 10% –0.3 0.8 V

VIH Input High Voltage (D, C, S) VCC = 5V ± 10% 2 VCC + 1 V

VOL Output Low Voltage (Q) VCC = 5V, IOL = 2.1mA 0.4 V
VOH Output High Voltage (Q) VCC = 5V, IOH = –400µA 2.4 V

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 M93C86, M93C76, M93C66, M93C56, M93C46, M93C06

Table 5C. DC Characteristics for M93CXX-W

(TA = 0 to 70°C or –40 to 85°C; VCC = 2.5V to 5.5V)
Symbol Parameter Test Condition Min Max Unit
ILI Input Leakage Current 0V ≤ VIN ≤ VCC ±2.5 µA
ILO Output Leakage Current 0V ≤ VOUT ≤ VCC, Q in Hi-Z ±2.5 µA
VCC = 5V, S = VIH, f = 1 MHz 1.5 mA
ICC Supply Current (CMOS Inputs)
VCC = 2.5V, S = VIH, f = 1 MHz 1 mA
VCC = 2.5V, S = VSS, C = VSS,
ICC1 Supply Current (Standby) 10 µA
ORG = VSS or VCC

VIL Input Low Voltage (D, C, S) –0.3 0.2 VCC V

VIH Input High Voltage (D, C, S) 0.7 VCC VCC + 1 V
VCC = 5V, IOL = 2.1mA 0.4 V
VOL Output Low Voltage (Q)
VCC = 2.5V, I OL = 100µA 0.2 V
VCC = 5V, IOH = –400µA 2.4 V
VOH Output High Voltage (Q)
VCC = 2.5V, I OH = –100µA VCC – 0.2 V

Table 5D. DC Characteristics for M93CXX-R (1)

(TA = 0 to 70°C or –20 to 85°C; VCC = 1.8V to 3.6V)
Symbol Parameter Test Condition Min Max Unit
ILI Input Leakage Current 0V ≤ VIN ≤ VCC ±2.5 µA
ILO Output Leakage Current 0V ≤ VOUT ≤ VCC, Q in Hi-Z ±2.5 µA
VCC = 3.6V, S = VIH, f = 1 MHz 1.5 mA
ICC Supply Current (CMOS Inputs)
VCC = 1.8V, S = VIH, f = 1 MHz 1 mA
VCC = 1.8V, S = VSS, C = VSS,
ICC1 Supply Current (Standby) 5 µA
ORG = VSS or VCC
VIL Input Low Voltage (D, C, S) –0.3 0.2 VCC V
VIH Input High Voltage (D, C, S) 0.8 VCC VCC + 1 V
VOL Output Low Voltage (Q) VCC = 1.8V, I OL = 100µA 0.2 V

VOH Output High Voltage (Q) VCC = 1.8V, I OH = –100µA VCC – 0.2 V
Note: 1. This is preliminary data.

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M93C86, M93C76, M93C66, M93C56, M93C46, M93C06

Table 6A. AC Characteristics

M93C86/76/66/56/46/06
VCC = 4.5V to 5.5V,
Symbol Alt Parameter VCC = 4.5V to 5.5V, Unit
TA = 0 to 70°C,
TA = –40 to 125°C
TA = –40 to 85°C
Min Max Min Max
Chip Select Set-up Time
50 50 ns
M93C06, M39C46, M93C56, M93C66
tSHCH tCSS
Chip Select Set-up time
100 100 ns
M93C76, M93C86

tCLSH tSKS Clock Set-up Time (relative to S) 100 100 ns

tDVCH tDIS Data In Set-up Time 100 100 ns
tCHDX tDIH Data In Hold Time 100 100 ns
tCHQL tPD0 Delay to Output Low 400 400 ns
tCHQV tPD1 Delay to Output Valid 400 400 ns
tCLSL tCSH Chip Select Hold Time 0 0 ns
tSLCH (1) Chip Select Low to Clock High 250 250 ns
tSLSH tCS Chip Select Low to Chip Select High 250 250 ns
tSHQV tSV Chip Select to Ready/Busy Status 400 400 ns

tSLQZ tDF Chip Select Low to Output Hi-Z 200 200 ns

tCHCL (2) tSKH Clock High Time 250 250 ns

tCLCH (2) tSKL Clock Low Time 250 250 ns

tW tWP Erase/Write Cycle time 10 10 ms
fC fSK Clock Frequency 0 1 0 1 MHz
Notes: 1. Chip Select must be brought low for a minimum of 250ns (tSLSH) between consecutive instruction cycles.
2. The Clock frequency specification calls for a minimum clock period of 1µs, therefore the sum of the timings t CHCL + tCLCH
must be greater or equal to 1µs. For example, if tCHCL is 250ns, then tCLCH must be at least 750ns.

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 M93C86, M93C76, M93C66, M93C56, M93C46, M93C06

Table 6B. AC Characteristics

M93C86/76/66/56/46/06
VCC = 2.5V to 5.5V, VCC = 1.8V to 3.6V,(3)
Symbol Alt Parameter Unit
TA = 0 to 70°C, TA = 0 to 70°C,
TA = –40 to 85°C TA = –20 to 85°C
Min Max Min Max

tSHCH tCSS Chip Select Set-up Time 100 100 ns

tCLSH tSKS Clock Set-up Time (relative to S) 100 100 ns
tDVCH tDIS Data In Set-up Time 100 100 ns
tCHDX tDIH Data In Hold Time 100 100 ns
tCHQL tPD0 Delay to Output Low 400 500 ns
tCHQV tPD1 Delay to Output Valid 400 500 ns
tCLSL tCSH Chip Select Hold Time 0 0 ns
(1)
tSLCH Chip Select Low to Clock High 250 250 ns
tSLSH tCS Chip Select Low to Chip Select High 1000 1000 ns

tSHQV tSV Chip Select to Ready/Busy Status 400 500 ns

tSLQZ tDF Chip Select Low to Output Hi-Z 200 200 ns
(2)
tCHCL tSKH Clock High Time 350 350 ns
(2)
tCLCH tSKL Clock Low Time 250 250 ns
tW tWP Erase/Write Cycle time 10 10 ms
fC fSK Clock Frequency 0 1 0 1 MHz
Notes: 1. Chip Select must be brought low for a minimum of 250ns (tSLSH) between consecutive instruction cycles.
2. The Clock frequency specification calls for a minimum clock period of 1µs, therefore the sum of the timings t CHCL + tCLCH
must be greater or equal to 1µs. For example, if tCHCL is 250ns, then tCLCH must be at least 750ns.
3. This is preliminary data.

Figure 4. Synchronous Timing, Start and Op-Code Input

tCLSH tCHCL

tSHCH tCLCH

tDVCH tCHDX

D START OP CODE OP CODE

START OP CODE INPUT

AI01428

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M93C86, M93C76, M93C66, M93C56, M93C46, M93C06

Figure 5. Synchronous Timing, Read or Write

tCLSL

tDVCH tCHDX tCHQV tSLSH

D An A0

tCHQL tSLQZ
Hi-Z
Q Q15/Q7 Q0

ADDRESS INPUT DATA OUTPUT

AI00820C

tSLCH

tCLSL

tDVCH tCHDX tSLSH

D An A0/D0

tSHQV tSLQZ
Hi-Z
Q BUSY READY

tW

ADDRESS/DATA INPUT WRITE CYCLE

AI01429

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 M93C86, M93C76, M93C66, M93C56, M93C46, M93C06

INSTRUCTIONS the power-on reset Threshold voltage. To protect

the memory contents from accidental corruption, it
The M93C86/C76/C66/C56/C46/C06 have seven is advisable to issue the EWDS instruction after
instructions, as shown in Table 7. Each instruction every write cycle. The READ instruction is not
is preceded by the rising edge of the signal applied affected by the EWEN or EWDS instructions.
on the S input (assuming that the clock C is low).
After the device is selected, the internal logic waits Erase
for the start bit, which defines the beginning of the
instructionbit stream. The start bit is the first ’1’ read The Erase instruction (ERASE) programs the ad-
on the D input during the rising edge of the clock dressed memory byte or word bits to ’1’. Once the
C. Following the start bit, the op-codes of the addressis correctly decoded,the falling edge of the
instructions are made up of the 2 following bits. Chip Select input (S) startsa self-timederase cycle.
Note that some instructions use only these first two If the M93Cx6 is still performing the erase cycle,
bits, others use also the first two bits of the address the Busy signal (Q = 0) will be returnedif S is driven
to define the op-code.The op-codeis thenfollowed high after the tSLSH delay, and the M93Cx6 will
by the address of the byte/word to be accessed. ignore any data on the bus. When the erase cycle
For the M93C06 and M93C46, the addressis made is completed, the Ready signal (Q = 1) will indicate
up of 6 bits for the x16 organization or 7 bits for the (if S is driven high) that the M93Cx6 is ready to
x8 organization (see Table 7A). For the M93C56 receive a new instruction.
and M93C66, the address is made up of 8 bits for Write
the x16 organizationor 9 bits for the x8 organization
(see Table 7B). For the M93C76 and M93C86, the The Write instruction (WRITE) is composed of the
address is made up of 10 bits for the x16 organiza- Op-Code followed by the address and the 8 or 16
tion or 11 bits for the x8 organization (see Table data bits to be written. Data input is sampled on the
7C). Low to High transition of the clock. After the last
data bit has been sampled, Chip Select (S) must
TheM93Cx6 is fabricatedin CMOS technologyand be brought Low before the next rising edge of the
is therefore able to run from 0Hz (static input sig- clock (C) in order to start the self-timed program-
nals) up to the maximum ratings (specified in Table ming cycle. This is important as, if S is brought low
6). before or after this specific frame window, the
Read addressed location will not be programmed.
The Read instruction (READ) outputs serial data If the M93Cx6 is still performing the write cycle, the
on the Data Output (Q). When a READ instruction Busy signal (Q = 0) will be returned if S is driven
is received, the instruction and address are de- high after the tSLSH delay, and the M93Cx6 will
coded and the data from the memory is transferred ignore any data on the bus. When the write cycle
intoan outputshift register. Adummy ’0’ bit isoutput is completed, the Ready signal (Q = 1) will indicate
first followed by the 8 bit byte or the 16 bit word with (if S is driven high) that the M93Cx6 is ready to
the MSB first. Output data changes are triggered receive a new instruction. Programming is inter-
by the Low to High transition of the Clock (C). The nally self-timed (the externalclock signal on C input
M93Cx6 will automatically increment the address may be disconnected or left running after the start
and will clock out the next byte/word as long as the of a Write cycle). The Write instruction includes an
Chip Select input (S) is held High. In this case the automatic Erase cycle before writing the data, it is
dummy ’0’ bit is NOT output between bytes/words thereforeunnecessaryto executean Eraseinstruc-
and a continuous stream of data can be read. tion before a Write instruction execution.
Erase/Write Enable and Disable Erase All
The Erase/Write Enable instruction (EWEN) The Erase All instruction (ERAL) erases the whole
authorizesthe following Erase/Write instructions to memory (all memory bits are set to ’1’). A dummy
be executed. The Erase/Write Disable instruction address is input during the instruction transfer and
(EWDS) disables the execution of the following the erase is made in the same way as the ERASE
Erase/Write instructions and the internal program- instruction above. If the M93Cx6 is still performing
ming cycle cannot run. When power is first applied, the erase cycle, the Busy signal (Q = 0) will be
the M93Cx6 is in Erase/Write Disable mode and all returned if S isdriven high after the tSLSH delay,and
Erase/Write instructions are inhibited. When the the M93Cx6 will ignore any data on the bus. When
EWEN instruction is executed,Erase/Write instruc- the erase cycle is completed, the Ready signal (Q
tions remain enabled until an Erase/Write Disable = 1) will indicate (if S is driven high) that the
instruction (EWDS) is executed or VCC falls below M93Cx6 is ready to receive a new instruction.

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M93C86, M93C76, M93C66, M93C56, M93C46, M93C06

Table 7A. Instruction Set for the M93C06 and M93C46

x8 Org Req. x16 Org Req.
Start Op-
Instr. Description Address Data Clock Address Data Clock
bit Code (1, 2) (1, 3)
(ORG = 0) Cycles (ORG = 1) Cycles

Read Data from

READ 1 10 A6-A0 Q7-Q0 A5-A0 Q15-Q0
Memory

Write Data to
WRITE 1 01 A6-A0 D7-D0 18 A5-A0 D15-D0 25
Memory

Erase/Write
EWEN 1 00 11X XXXX 10 11 XXXX 9
Enable

Erase/Write
EWDS 1 00 00X XXXX 10 00 XXXX 9
Disable

Erase Byte or
ERASE 1 11 A6-A0 10 A5-A0 9
Word

ERAL Erase All Memory 1 00 10X XXXX 10 10 XXXX 9

Write All Memory
WRAL 1 00 01X XXXX D7-D0 18 01 XXXX D15-D0 25
with same Data
Notes: 1. X = don’t care bit.
2. Address bits A6 and A5 are not decoded by the M93C06.
3. Address bits A5 and A4 are not decoded by the M93C06.

Table 7B. Instruction Set for the M93C56 and M93C66

x8 Org Req. x16 Org Req.
Start Op-
Instr. Description Address Data Clock Address Data Clock
bit Code
(ORG = 0) (1, 2) Cycles (ORG = 1) (1, 3) Cycles

Read Data from

READ 1 10 A8-A0 Q7-Q0 A7-A0 Q15-Q0
Memory

Write Data to
WRITE 1 01 A8-A0 D7-D0 20 A7-A0 D15-D0 27
Memory

Erase/Write
EWEN 1 00 1 1XXX XXXX 12 11XX XXXX 11
Enable

Erase/Write
EWDS 1 00 0 0XXX XXXX 12 00XX XXXX 11
Disable

Erase Byte or
ERASE 1 11 A8-A0 12 A7-A0 11
Word

ERAL Erase All Memory 1 00 1 0XXXX XXXX 12 10XX XXXX 11

Write All Memory

WRAL 1 00 0 1XXXX XXXX D7-D0 20 01XX XXXX D15-D0 27
with same Data
Notes: 1. X = don’t care bit.
2. Address bit A8 is not decoded by the M93C56.
3. Address bit A7 is not decoded by the M93C56.

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 M93C86, M93C76, M93C66, M93C56, M93C46, M93C06

Table 7C. Instruction Set for the M93C76 and M93C86

x8 Org Req. x16 Org Req.
Start Op-
Instr. Description Address Data Clock Address Data Clock
bit Code (1, 2) (1, 3)
(ORG = 0) Cycles (ORG = 1) Cycles

Read Data from

READ 1 10 A10-A0 Q7-Q0 A9-A0 Q15-Q0
Memory

Write Data to
WRITE 1 01 A10-A0 D7-D0 22 A9-A0 D15-D0 29
Memory

Erase/Write
EWEN 1 00 11X XXXX XXXX 14 11 XXXX XXXX 13
Enable

Erase/Write
EWDS 1 00 00X XXXX XXXX 14 00 XXXX XXXX 13
Disable

Erase Byte or
ERASE 1 11 A10-A0 14 A9-A0 13
Word

ERAL Erase All Memory 1 00 10X XXXX XXXX 14 10 XXXX XXXX 13

Write All Memory
WRAL 1 00 01X XXXX XXXX D7-D0 22 01 XXXX XXXX D15-D0 29
with same Data
Notes: 1. X = don’t care bit.
2. Address bit A10 is not decoded by the M93C76.
3. Address bit A9 is not decoded by the M93C76.

Write All put (Q) indicates the Ready/Busy status of the

memory when the Chip Select is driven High. Once
The Write All instruction (WRAL) writes the Data
the M93Cx6 is Ready, the Data Output is set to ’1’
Input byte or word into all the addresses of the
until a new start bit is decoded or the Chip Select
memory device. As for the Erase All instruction, a
is brought Low.
dummy address is input during the instruction
transfer.
If the M93Cx6 is still performing the write cycle, the COMMON I/O OPERATION
Busy signal (Q = 0) will be returned if S is driven The Data Output (Q) and Data Input(D) signalscan
high after the tSLSH delay, and the M93Cx6 will be connected together, through a current limiting
ignore any data on the bus. When the write cycle resistor, to form a common, one wire data bus.
is completed, the Ready signal (Q = 1) will indicate Some precautions must be taken when operating
(if S is driven high) that the M93Cx6 is ready to the memory with this connection,mostly to prevent
receive a new instruction. a short circuit between the last entered address bit
(A0) and the first data bit output by Q. The reader
should refer to the STMicroelectronics application
READY/BUSY Status
note AN394 ”MICROWIRE EEPROM Common
During every programming cycle (after a WRITE, I/O Operation”.
ERASE, WRAL or ERAL instruction) the Data Out-

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M93C86, M93C76, M93C66, M93C56, M93C46, M93C06

Figure 6. READ, WRITE, EWEN, EWDS Sequences

READ S

D 1 1 0 An A0

Q Qn Q0

ADDR DATA OUT

OP
CODE

WRITE S

CHECK
STATUS
D 1 0 1 An A0 Dn D0

ADDR DATA IN BUSY READY

OP
CODE

ERASE S ERASE S
WRITE WRITE
ENABLE DISABLE

D 1 0 0 1 1 Xn X0 D 1 0 0 0 0 Xn X0

OP OP
CODE CODE
AI00878C

Note: An, Xn, Qn, Dn: Refer to Table 6a for the M93C06 and M93C46; to Table 6b for the M93C56 and M93C66; to Table 6c for the
M93C76 and M93C86.

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 M93C86, M93C76, M93C66, M93C56, M93C46, M93C06

Figure 7. ERASE, ERAL Sequences

ERASE S
CHECK
STATUS
D 1 1 1 An A0

ADDR BUSY READY

OP
CODE

ERASE S
ALL
CHECK
STATUS
D 1 0 0 1 0 Xn X0

ADDR BUSY READY

OP
CODE
AI00879B

Note: An, Xn: Refer to Table 7a for the M93C06 and M93C46; to Table 7b for the M93C56 and M93C66; to Table 7c for the M93C76 and
M93C86.

Figure 8. WRAL Sequence

WRITE S
ALL
CHECK
STATUS
D 1 0 0 0 1 Xn X0 Dn D0

ADDR DATA IN BUSY READY

OP
CODE
AI00880C

Note: Xn, Dn: Refer to Table 7a for the M93C06 and M93C46; to Table 7b for the M93C56 and M93C66; to Table 7c for the M93C76 and
M93C86.

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M93C86, M93C76, M93C66, M93C56, M93C46, M93C06

Figure 9. WRITE Sequence with One Clock Glitch

An An-1 An-2

START ”0” ”1” Glitch D0

ADDRESS AND DATA

WRITE ARE SHIFTED BY ONE BIT
AI01395

CLOCK PULSE COUNTER Selectsignal (1 Start bit+ 2 Op-codebit + 9 Address

The M93Cx6 offers a functional security block bit + 8 Databit = 20):if so, the M93C56(or M93C66)
which filters glitches on the clock input (C), the executes the WRITE instruction; if the number of
clock pulse counter. In a normal environment, the clock pulses is not equal to 20, the instruction will
M93Cx6 expects to receive the exact number of not be executed (and data will not be corrupted).
data bits on the D input (start bit, Op-Code, Ad- In the same way, when the organisation x16 is
dress, Data); that is the exact amount of clock selected with the M93C56 (or M93C66), the num-
pulses on the C input. ber of clock pulses incoming to the counter must
In a noisy environment, the number of pulses re- be exactly 27 (1 Start bit + 2 Op-code bit + 8
ceived (on the clock input C) may be greater than Address bit + 16 Data bit = 27) from the Start bit to
the clock pulses delivered by the Master (Microcon- the falling edge of Chip Select signal: if so, the
troller) driving the M93Cx6. In such a case, a part M93C56(or M93C66)executes theWRITE instruc-
of the instruction can be delayed by one or more tion; if the number of clock pulses is not equal to
bits (see Figure 9), and may induce an erroneous 27, the instruction will not be executed (and data
write of data at an invalid address. The M93Cx6 will not be corrupted). The clock pulse counter is
has an on-chip counter which counts the clock active on the WRITE, ERASE, ERAL and WRALL
pulses from the Start bit until the falling edge of the instructions.
Chip Select signal. In order to determine the exact number of clock
For the WRITE instructions with a M93C56 (or pulses needed for all the M93Cx6 family on ERASE
M93C66), the number of clock pulses incoming to and WRITE instructions, refer to the Tables 7A, 7B
the counter must be exactly 20 (with the organisa- and 7C, in the column: Requested Clock Cycles.
tion x8) from the Start bit to the falling edge of Chip

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 M93C86, M93C76, M93C66, M93C56, M93C46, M93C06

ORDERING INFORMATION SCHEME

Example: M93C86 – T W MN 6 T

Memory Density Option

86 16 Kbit T Tape & Reel
Packing
76 (1) 8 Kbit
66 4 Kbit
56 2 Kbit
46 1 Kbit
06 256 bit

Turned Mode Operating Voltage Package Temperature Range

(5) (2)
T 90° Turned die blank 4.5V to 5.5V BN PSDIP8 1 0 to 70 °C
0.25mm Frame
blank Standard W 2.5V to 5.5V 5 –20 to 85 °C
MN SO8
R (4) 1.8V to 3.6V 150mil Width 6 –40 to 85 °C
3 (3)
–40 to 125 °C

Notes: 1. This is preliminary information on a new product now in development. Details are subject to change without notice.
2. Temperature range on request only.
3. Produced with High Reliability Certified Flow (HRCF), in VCC range 4.5V to 5.5V at 1MHz only.
4. -R version (1.8V to 3.6V) are only available in temperature ranges 5 or 1.
5. Turned die option is not available for all devices. Please contact the STMicroelectronics Sales Office nearest to you.

Devices are shipped from the factory with the memory content set at all ”1’s” (FFFFh for x16, FFh for x8).
For a list of available options (Operating Voltage, Package, etc...) or for further information on any aspect
of this device, please contact the STMicroelectronics Sales Office nearest to you.

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M93C86, M93C76, M93C66, M93C56, M93C46, M93C06

PSDIP8 - 8 pin Plastic Skinny DIP, 0.25mm lead frame

mm inches
Symb
Typ Min Max Typ Min Max

A 3.90 5.90 0.154 0.232

A1 0.49 – 0.019 –

A2 3.30 5.30 0.130 0.209

B 0.36 0.56 0.014 0.022

B1 1.15 1.65 0.045 0.065

C 0.20 0.36 0.008 0.014

D 9.20 9.90 0.362 0.390

E 7.62 – – 0.300 – –

E1 6.00 6.70 0.236 0.264

e1 2.54 – – 0.100 – –

eA 7.80 – 0.307 –
eB 10.00 0.394

L 3.00 3.80 0.118 0.150

N 8 8

A2 A

A1 L
B e1 C
B1 eA
D eB

E1 E

1
PSDIP-a

Drawing is not to scale

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 M93C86, M93C76, M93C66, M93C56, M93C46, M93C06

SO8 - 8 lead Plastic Small Outline, 150 mils body width

mm inches
Symb
Typ Min Max Typ Min Max

A 1.35 1.75 0.053 0.069

A1 0.10 0.25 0.004 0.010

B 0.33 0.51 0.013 0.020

C 0.19 0.25 0.007 0.010

D 4.80 5.00 0.189 0.197

E 3.80 4.00 0.150 0.157

e 1.27 – – 0.050 – –
H 5.80 6.20 0.228 0.244

h 0.25 0.50 0.010 0.020

L 0.40 0.90 0.016 0.035

α 0° 8° 0° 8°
N 8 8

CP 0.10 0.004

h x 45°

A
C
B
e CP

E H
1

A1 α L

SO-a

Drawing is not to scale

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M93C86, M93C76, M93C66, M93C56, M93C46, M93C06

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Spec ifications mentioned in this publication are subject to
change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.

The ST logo is a registered trademark of STMicroelectronics

 1998 STMicroelectronics - All Rights Reserved

 MICROWIRE is a registered trademark of National Semiconductor Corp.

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