ST24C16, ST25C16

ST24W16, ST25W16
16 Kbit Serial I2C Bus EEPROM
with User-Defined Block Write Protection

1 MILLION ERASE/WRITE CYCLES, with

40 YEARS DATA RETENTION
SINGLE SUPPLY VOLTAGE:
– 4.5V to 5.5V for ST24x16 versions
– 2.5V to 5.5V for ST25x16 versions
8 8
HARDWARE WRITE CONTROL VERSIONS:
ST24W16 and ST25W16
TWO WIRE SERIAL INTERFACE, FULLY I2C 1 1
BUS COMPATIBLE PSDIP8 (B) SO8 (M)
BYTE and MULTIBYTE WRITE (up to 8 0.25mm Frame 150mil Width
BYTES) for the ST24C16
PAGE WRITE (up to 16 BYTES)
BYTE, RANDOM and SEQUENTIAL READ
MODES
SELF TIMED PROGRAMING CYCLE Figure 1. Logic Diagram
AUTOMATIC ADDRESS INCREMENTING
ENHANCED ESD/LATCH UP
PERFORMANCES

DESCRIPTION
This specification covers a range of 16 Kbit I2C bus
EEPROM products, the ST24/25C16 and the VCC
ST24/25W16. In the text, products are referred to
as ST24/25x16 where "x" is: "C" for Standard ver-
sion and "W" for hardware Write Control version.
2
The ST24/25x16 are 16 Kbit electrically erasable
programmable memories (EEPROM), organized PB0-PB1 SDA
as 8 blocks of 256 x8 bits. These are manufactured
in STMicroelectronics’s Hi-Endurance Advanced PRE ST24x16
CMOS technology which guarantees an endur- ST25x16
SCL

Table 1. Signal Names MODE/WC*

PRE Write Protect Enable

PB0, PB1 Protect Block Select
VSS
SDA Serial Data Address Input/Output AI00866B

SCL Serial Clock

Multybyte/Page Write Mode
MODE
(C version)
WC Write Control (W version)
VCC Supply Voltage
VSS Ground Note: WC signal is only available for ST24/25W16 products.

February 1999 1/17

ST24/25C16, ST24/25W16

Figure 2A. DIP Pin Connections Figure 2B. SO8 Pin Connections

ST24x16 ST24x16
ST25x16 ST25x16

PRE 1 8 VCC PRE 1 8 VCC

PB0 2 7 MODE/WC PB0 2 7 MODE/WC
PB1 3 6 SCL PB1 3 6 SCL
VSS 4 5 SDA VSS 4 5 SDA
AI00867B AI00500B

Table 2. Absolute Maximum Ratings (1)

Symbol Parameter Value Unit

TA Ambient Operating Temperature –40 to 125 °C

TSTG Storage Temperature –65 to 150 °C

TLEAD Lead Temperature, Soldering (SO8) 40 sec 215

°C
(PSDIP8) 10 sec 260

VIO Input or Output Voltages –0.6 to 6.5 V

VCC Supply Voltage –0.3 to 6.5 V

Electrostatic Discharge Voltage (Human Body model) (2) 4000 V

VESD
Electrostatic Discharge Voltage (Machine model) (3) 500 V
Notes: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings"
may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other
conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum
Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and
other relevant quality documents.
2. 100pF through 1500Ω; MIL-STD-883C, 3015.7
3. 200pF through 0Ω; EIAJ IC-121 (condition C)

DESCRIPTION (cont’d) carry a built-in 4 bit, unique device identification

code (1010) corresponding to the I2C bus defini-
ance of one million erase/write cycles with a data tion. The memories behave as slave devices in the
retention of 40 years. The ST25x16 operates with I2C protocol with all memory operations synchro-
a power supply value as low as 2.5V. Both Plastic nized by the serial clock. Read and write operations
Dual-in-Line and Plastic Small Outline packages are initiated by a START condition generated by the
are available. bus master. The START condition is followed by a
The memories are compatible with the I2C stand- stream of 4 bits (identification code 1010), 3 block
ard, two wire serial interface which uses a bi-direc- select bits, plus one read/write bit and terminated
tional data bus and serial clock. The memories by an acknowledge bit. When writing data to the

2/17
 ST24/25C16, ST24/25W16

Table 3. Device Select Code

Device Code Memory MSB Addresses RW
Bit b7 b6 b5 b4 b3 b2 b1 b0
Device Select 1 0 1 0 A10 A9 A8 RW
Note: The MSB b7 is sent first.

Table 4. Operating Modes

Mode RW bit MODE pin Bytes Initial Sequence
Current Address Read ’1’ X 1 START, Device Select, RW = ’1’
’0’ START, Device Select, RW = ’0’, Address,
Random Address Read X 1
’1’ reSTART, Device Select, RW = ’1’
Sequential Read ’1’ X 1 to 2048 As CURRENT or RANDOM Mode
Byte Write ’0’ X 1 START, Device Select, RW = ’0’
Multibyte Write ’0’ VIH 8 START, Device Select, RW = ’0’
Page Write ’0’ VIL 16 START, Device Select, RW = ’0’
Note: X = VIH or VIL.

memory it responds to the 8 bits received by as- Power On Reset: VCC lock out write protect. In
serting an acknowledge bit during the 9th bit time. order to prevent data corruption and inadvertent
When data is read by the bus master, it acknow- write operations during power up, a Power On
ledges the receipt of the data bytes in the same Reset (POR) circuit is implemented. Untill the VCC
way. Data transfers are terminated with a STOP voltage has reached the POR threshold value, the
condition. internal reset is active: all operations are disabled
Data in the 4 upper blocks of the memory may be and the device will not respond to any command.
write protected. The protected area is programma- In the same way, when VCC drops down from the
ble to start on any 16 byte boundary. The block in operating voltage to below the POR threshold
which the protection starts is selected by the input value, all operations are disabled and the device
pins PB0, PB1. Protection is enabled by setting a will not respond to any command. A stable VCC
Protect Flag bit when the PRE input pin is driven must be applied before applying any logic signal.
High.

3/17
ST24/25C16, ST24/25W16

SIGNALS DESCRIPTION Mode (MODE). The MODE input is available on pin

7 (see also WC feature) and may be driven dynami-
Serial Clock (SCL). The SCL input signal is used
cally. It must be at VIL or VIH for the Byte Write
to synchronise all data in and out of the memory. A
mode, VIH for Multibyte Write mode or VIL for Page
resistor can be connected from the SCL line to VCC
Write mode. When unconnected, the MODE input
to act as a pull up (see Figure 3).
is internally read as VIH (Multibyte Write mode).
Serial Data (SDA). The SDA signal is bi-directional Write Control (WC). An hardware Write Control
and is used to transfer data in or out of the memory. feature is offered only for ST24W16 and ST25W16
It is an open drain output that may be wire-OR’ed versions on pin 7. This feature is usefull to protect
with other open drain or open collector signals on the contents of the memory from any erroneous
the bus. A resistor must be connected from the SDA erase/write cycle. The Write Control signal is used
bus line to VCC to act as pull up (see Figure 3). to enable (WC at VIH) or disable (WC at VIL) the
Protected Block Select (PB0, PB1). PB0 and PB1 internal write protection. When unconnected, the
input signals select the block in the upper part of WC input is internally read as VIL. The devices with
the memory where write protection starts. These this Write Control feature no longer supports the
inputs have a CMOS compatible input level. Multibyte Write mode of operation, however all
other write modes are fully supported.
Protect Enable (PRE). The PRE input signal, in
Refer to the AN404 Application Note for more de-
addition to the status of the Block Address Pointer
tailed information about Write Control feature.
bit (b2, location 7FFh as in Figure 7), sets the PRE
write protection active.

Figure 3. Maximum RL Value versus Bus Capacitance (CBUS) for an I2C Bus

20

VCC

16

RL RL
12
RL max (kΩ)

SDA

MASTER CBUS
SCL
8

CBUS

4
VCC = 5V

0
100 200 300 400

CBUS (pF) AI01100

4/17
 ST24/25C16, ST24/25W16

Table 5. Input Parameters (1) (TA = 25 °C, f = 100 kHz )

Symbol Parameter Test Condition Min Max Unit
CIN Input Capacitance (SDA) 8 pF

CIN Input Capacitance (other pins) 6 pF

ZWCL WC Input Impedance (ST24/25W16) VIN ≤ 0.3 VCC 5 20 kΩ
ZWCH WC Input Impedance (ST24/25W16) VIN ≥ 0.7 VCC 500 kΩ
Low-pass filter input time constant
tLP 100 ns
(SDA and SCL)
Note: 1. Sampled only, not 100% tested.

Table 6. DC Characteristics
(TA = 0 to 70 °C or –40 to 85 °C; VCC = 4.5V to 5.5V or 2.5V to 5.5V)
Symbol Parameter Test Condition Min Max Unit

ILI Input Leakage Current 0V ≤ VIN ≤ VCC ±2 µA

0V ≤ VOUT ≤ VCC
ILO Output Leakage Current ±2 µA
SDA in Hi-Z

VCC = 5V, fC = 100kHz

Supply Current (ST24 series) 2 mA
ICC (Rise/Fall time < 10ns)

Supply Current (ST25 series) VCC = 2.5V, fC = 100kHz 1 mA

VIN = VSS or VCC,

100 µA
Supply Current (Standby) VCC = 5V
ICC1
(ST24 series)
VIN = VSS or VCC,
300 µA
VCC = 5V, fC = 100kHz

VIN = VSS or VCC,

5 µA
Supply Current (Standby) VCC = 2.5V
ICC2
(ST25 series)
VIN = VSS or VCC,
50 µA
VCC = 2.5V, fC = 100kHz

VIL Input Low Voltage (SCL, SDA) –0.3 0.3 VCC V

VIH Input High Voltage (SCL, SDA) 0.7 VCC VCC + 1 V

Input Low Voltage

VIL –0.3 0.5 V
(PB0 - PB1, PRE, MODE, WC)

Input High Voltage

VIH VCC – 0.5 VCC + 1 V
(PB0 - PB1, PRE, MODE, WC)

Output Low Voltage (ST24 series) IOL = 3mA, VCC = 5V 0.4 V

VOL
Output Low Voltage (ST25 series) IOL = 2.1mA, VCC = 2.5V 0.4 V

5/17
ST24/25C16, ST24/25W16

Table 7. AC Characteristics
(TA = 0 to 70 °C or –40 to 85 °C; VCC = 4.5V to 5.5V or 2.5V to 5.5V)
Symbol Alt Parameter Min Max Unit

tCH1CH2 tR Clock Rise Time 1 µs

tCL1CL2 tF Clock Fall Time 300 ns

tDH1DH2 tR Input Rise Time 1 µs

tDL1DL1 tF Input Fall Time 300 ns

tCHDX (1)
tSU:STA Clock High to Input Transition 4.7 µs

tCHCL tHIGH Clock Pulse Width High 4 µs

tDLCL tHD:STA Input Low to Clock Low (START) 4 µs

tCLDX tHD:DAT Clock Low to Input Transition 0 µs

tCLCH tLOW Clock Pulse Width Low 4.7 µs

tDXCX tSU:DAT Input Transition to Clock Transition 250 ns

tCHDH tSU:STO Clock High to Input High (STOP) 4.7 µs

tDHDL tBUF Input High to Input Low (Bus Free) 4.7 µs

(2)
tCLQV tAA Clock Low to Next Data Out Valid 0.3 3.5 µs

tCLQX tDH Data Out Hold Time 300 ns

fC fSCL Clock Frequency 100 kHz
(3)
tW tWR Write Time 10 ms
Notes: 1. For a reSTART condition, or following a write cycle.
2. The minimum value delays the falling/rising edge of SDA away from SCL = 1 in order to avoid unwanted START and/or STOP
conditions.
3. In the Multibyte Write mode only, if accessed bytes are on two consecutive 8 bytes rows (5 address MSB are not constant)
the maximum programming time is doubled to 20ms.

Table 8. AC Measurement Conditions DEVICE OPERATION

Input Rise and Fall Times ≤ 50ns
I2C Bus Background
The ST24/25x16 support the I2C protocol. This
Input Pulse Voltages 0.2VCC to 0.8VCC protocol defines any device that sends data onto
Input and Output Timing Ref. the bus as a transmitter and any device that reads
0.3VCC to 0.7VCC the data as a receiver. The device that controls the
Voltages
data transfer is known as the master and the other
as the slave. The master will always initiate a data
Figure 4. AC Testing Input Output Waveforms transfer and will provide the serial clock for syn-
chronisation. The ST24/25x16 are always slave
devices in all communications.
0.8VCC Start Condition. START is identified by a high to
0.7VCC low transition of the SDA line while the clock SCL
is stable in the high state. A START condition must
0.3VCC
0.2VCC precede any command for data transfer. Except
during a programming cycle, the ST24/25x16 con-
AI00825 tinuously monitor the SDA and SCL signals for a
START condition and will not respond unless one
is given.

6/17
 ST24/25C16, ST24/25W16

Figure 5. AC Waveforms

tCHCL tCLCH

SCL

tDLCL tDXCX tCHDH

SDA IN

tCHDX tCLDX tDHDL

START SDA SDA STOP &

CONDITION INPUT CHANGE BUS FREE

SCL

tCLQV tCLQX

SDA OUT DATA VALID

DATA OUTPUT

SCL

tW

SDA IN

tCHDH tCHDX

STOP WRITE CYCLE START

CONDITION CONDITION

AI00795B

7/17
ST24/25C16, ST24/25W16

Figure 6. I2C Bus Protocol

SCL

SDA

START SDA SDA STOP

CONDITION INPUT CHANGE CONDITION

SCL 1 2 3 7 8 9

SDA MSB ACK

START
CONDITION

SCL 1 2 3 7 8 9

SDA MSB ACK

STOP
CONDITION

AI00792

Stop Condition. STOP is identified by a low to high Data Input. During data input the ST24/25x16
transition of the SDA line while the clock SCL is samples the SDA bus signal on the rising edge of
stable in the high state. A STOP condition termi- the clock SCL. Note that for correct device opera-
nates communication between the ST24/25x16 tion the SDA signal must be stable during the clock
and the bus master. A STOP condition at the end low to high transition and the data must change
of a Read command forces the standby state. A ONLY when the SCL line is low.
STOP condition at the end of a Write command
Memory Addressing. To start communication be-
triggers the internal EEPROM write cycle.
tween the bus master and the slave ST24/25x16,
Acknowledge Bit (ACK). An acknowledge signal the master must initiate a START condition. The 8
is used to indicate a successful data transfer. The bits sent after a START condition are made up of a
bus transmitter, either master or slave, will release device select of 4 bits that identifie the device type
the SDA bus after sending 8 bits of data. During the (1010), 3 Block select bits and one bit for a READ
9th clock pulse period the receiver pulls the SDA (RW = 1) or WRITE (RW = 0) operation.
bus low to acknowledge the receipt of the 8 bits of
data. There are three modes both for read and write.
They are summarised in Table 4 and described
hereafter. A communication between the master
and the slave is ended with a STOP condition.

8/17
 ST24/25C16, ST24/25W16

Figure 7. Memory Protection

PB1 PB0

Block
Select 1

Protect Location

16 byte Protect Flag

boundary Enable = 0
address Disable = 1
PB1 PB0
b7 b4 b2
7FFh 0 X X
Block 7 1 1
700h

Block 6 1 0
600h

Block 5 0 1
500h

Block 4 0 0
400h

AI00870B

Write Operations is independant of the state of the MODE pin which

could be left floating if only this mode was to be
The Multibyte Write mode (only available on the
used. However it is not a recommended operating
ST24/25C16 versions) is selected when the MODE
mode, as this pin has to be connected to either VIH
pin is at VIH and the Page Write mode when MODE
or VIL, to minimize the stand-by current.
pin is at VIL. The MODE pin may be driven dynami-
cally with CMOS input levels. Multibyte Write (ST24/25C16 only). For the Mul-
tibyte Write mode, the MODE pin must be at VIH.
Following a START condition the master sends a The Multibyte Write mode can be started from any
device select code with the RW bit reset to ’0’. The address in the memory. The master sends from one
memory acknowledges this and waits for a byte up to 8 bytes of data, which are each acknowledged
address. The byte address of 8 bits provides ac- by the memory. The transfer is terminated by the
cess to any of the 256 bytes of one memory block. master generating a STOP condition. The duration
After receipt of the byte address the device again of the write cycle is tW = 10ms maximum except
responds with an acknowledge. when bytes are accessed on 2 contiguous rows
For the ST24/25W16 versions, any write command (one row is 16 bytes), the programming time is then
with WC = ’1’ (during a period of time from the doubled to a maximum of 20ms. Writing more than
START condition untill the end of the Byte Address) 8 bytes in the Multibyte Write mode may modify
will not modify data and will NOT be acknowledged data bytes in an adjacent row (one row is 16 bytes
on data bytes, as in Figure 10. long). However, the Multibyte Write can properly
write up to 16 consecutive bytes only if the first
Byte Write. In the Byte Write mode the master address of these 16 bytes is the first address of the
sends one data byte, which is acknowledged by the row, the 15 following bytes being written in the 15
memory. The master then terminates the transfer following bytes of this same row.
by generating a STOP condition. The Write mode

9/17
ST24/25C16, ST24/25W16

Page Write. For the Page Write mode, the MODE Minimizing System Delay by Polling On ACK.
pin must be at VIL. The Page Write mode allows up During the internal Write cycle, the memory discon-
to 16 bytes to be written in a single write cycle, nects itself from the bus in order to copy the data
provided that they are all located in the same ’row’ from the internal latches to the memory cells. The
in the memory: that is the same Block Address bits maximum value of the Write time (tW) is given in the
(b3, b2, b1 of Device Select code in Table 3) and AC Characteristics table, this timing value may be
the same 4 MSBs in the Byte Address. The master reduced by an ACK polling sequence issued by the
sends one up to 16 bytes of data, which are each master.
acknowledged by the memory. After each byte is The sequence is:
transfered, the internal byte address counter (4
– Initial condition: a Write is in progress (see Fig-
Least Significant Bits only) is incremented. The
ure 8).
transfer is terminated by the master generating a
STOP condition. Care must be taken to avoid ad- – Step 1: the Master issues a START condition
dress counter ’roll-over’ which could result in data followed by a Device Select byte (1st byte of
being overwritten. Note that for any write mode, the the new instruction).
generation by the master of the STOP condition – Step 2: if the memory is internally writing, no
starts the internal memory program cycle. All inputs ACK will be returned. The Master goes back
are disabled until the completion of this cycle and to Step1. If the memory has terminated the in-
the memory will not respond to any request. ternal writing, it will issue an ACK indicating
that the memory is ready to receive the sec-
ond part of the instruction (the first byte of this
instruction was already sent during Step 1).
Figure 8. Write Cycle Polling using ACK

WRITE Cycle
in Progress

START Condition

DEVICE SELECT
with RW = 0

NO ACK
Returned

First byte of instruction YES

with RW = 0 already
decoded by ST24xxx

Next
NO Operation is YES
Addressing the
Memory
Send
Byte Address
ReSTART

STOP

Proceed Proceed
WRITE Operation Random Address
READ Operation

AI01099B

10/17
 ST24/25C16, ST24/25W16

Write Protection. Data in the upper four blocks of – select the block by hardwiring the signals PB0
256 bytes of the memory may be write protected. & PB1;
The memory is write protected between a boundary – set the protection by writing the correct bottom
address and the top of memory (address boundary address in the Address Pointer (4
7FFh).The boundary address is user defined by MSBs of location 7FFh) with bit b2 (Protect
writing it in the Block Address Pointer (location Flag) set to ’0’.
7FFh).
Note that for a correct fonctionality of the memory,
The Block Address Pointer is an 8 bit EEPROM all the 4 LSBs of the Block Address Pointer must
register located at the address 7FFh. It is com- also be programmed at ’0’. The area will be pro-
posed by 4 MSBs Address Pointer, which defines tected when the PRE input is taken High.
the bottom boundary address, and 4 LSBs which
must be programmed at ’0’. This Address Pointer Remark: The Write Protection is active if and only
can therefore address a boundary by page of 16 if the PRE input pin is driven High and the bit 2 of
bytes. location 7FFh is set to ’0’. In all the other cases, the
memory Block will not be protected. While the PRE
The block in which the Block Address Pointer de- input pin is read at ’0’ by the memory, the location
fines the boundary of the write protected memory 7FFh can be used as a normal EEPROM byte.
is defined by the logic level applied on the PB1 and
PB0 input pins: Caution: Special attention must be used when
using the protect mode together with the Multibyte
– PB1 =’0’and PB0 =’0’ select block 4 Write mode (MODE input pin High). If the Multibyte
– PB1 =’0’and PB0 =’1’ select block 5 Write starts at the location right below the first byte
– PB1 =’1’and PB0 =’0’ select block 6 of the Write Protected area, then the instruction will
write over the first 7 bytes of the Write Protected
– PB1 =’1’and PB0 =’1’ select block 7 area. The area protected is therefore smaller than
The following sequence should be used to set the the content defined in the location 7FFh, by 7 bytes.
Write Protection: This does not apply to the Page Write mode as the
– write the data to be protected into the top of address counter ’roll-over’ and thus cannot go
the memory, up to, but not including, location above the 16 bytes lower boundary of the protected
7FFh; area.

Figure 9. Write Modes Sequence (ST24/25C16)

ACK ACK ACK

BYTE WRITE DEV SEL BYTE ADDR DATA IN

START

STOP

R/W

ACK ACK ACK

MULTIBYTE
AND DEV SEL BYTE ADDR DATA IN 1 DATA IN 2
PAGE WRITE
START

R/W

ACK ACK

DATA IN N
STOP

AI00793

11/17
ST24/25C16, ST24/25W16

Figure 10. Write Modes Sequence with Write Control = 1 (ST24/25W16)

WC

ACK ACK NO ACK

BYTE WRITE DEV SEL BYTE ADDR DATA IN

START

STOP
R/W

WC

ACK ACK NO ACK

PAGE WRITE DEV SEL BYTE ADDR DATA IN 1 DATA IN 2

START

R/W

WC (cont'd)

NO ACK NO ACK

PAGE WRITE DATA IN N

(cont'd)
STOP

AI01161B

Read Operation Random Address Read. A dummy write is per-

Read operations are independent of the state of the formed to load the address into the address counter
MODE signal. On delivery, the memory content is (see Figure 11). This is followed by another START
set at all "1’s" (or FFh). condition from the master and the byte address
repeated with the RW bit set to ’1’. The memory
Current Address Read. The memory has an in- acknowledges this and outputs the byte ad-
ternal byte address counter. Each time a byte is
dressed. The master does NOT acknowledge the
read, this counter is incremented. For the Current byte output, but terminates the transfer with a
Address Read mode, following a START condition, STOP condition.
the master sends a memory address with the RW
bit set to ’1’. The memory acknowledges this and Sequential Read. This mode can be initiated with
outputs the byte addressed by the internal byte either a Current Address Read or a Random Ad-
address counter. This counter is then incremented. dress Read. However, in this case the master
The master does NOT acknowledge the byte out- DOES acknowledge the data byte output and the
put, but terminates the transfer with a STOP con- memory continues to output the next byte in se-
dition. quence. To terminate the stream of bytes, the
master must NOT acknowledge the last byte out-

12/17
 ST24/25C16, ST24/25W16

Figure 11. Read Modes Sequence

ACK NO ACK
CURRENT
ADDRESS DEV SEL DATA OUT
READ

START

STOP
R/W

ACK ACK ACK NO ACK

RANDOM
ADDRESS DEV SEL * BYTE ADDR DEV SEL * DATA OUT
READ
START

START

STOP
R/W R/W

ACK ACK ACK NO ACK

SEQUENTIAL
CURRENT DEV SEL DATA OUT 1 DATA OUT N
READ
START

STOP
R/W

ACK ACK ACK ACK

SEQUENTIAL
RANDOM DEV SEL * BYTE ADDR DEV SEL * DATA OUT 1
READ
START

START

R/W R/W

ACK NO ACK

DATA OUT N
STOP

AI00794C

Note: * The 7 Most Significant bits of DEV SEL bytes of a Random Read (1st byte and 3rd byte) must be identical.

put, but MUST generate a STOP condition. The Acknowledge in Read Mode. In all read modes
output data is from consecutive byte addresses, the ST24/25x16 wait for an acknowledge during the
with the internal byte address counter automat- 9th bit time. If the master does not pull the SDA line
ically incremented after each byte output. After a low during this time, the ST24/25x16 terminate the
count of the last memory address, the address data transfer and switches to a standby state.
counter will ’roll- over’ and the memory will continue
to output data.

13/17
ST24/25C16, ST24/25W16

ORDERING INFORMATION SCHEME

Example: ST24C16 M 1 TR

Operating Voltage Range Package Temperature Range Option

24 4.5V to 5.5V C Standard B PSDIP8 1 0 to 70 °C TR Tape & Reel
0.25mm Frame Packing
25 2.5V to 5.5V W Hardware 6 –40 to 85 °C
Write Control M SO8
150mil Width 3 (1) –40 to 125 °C

Note: 1. Temperature range on special request only.

Devices are shipped from the factory with the memory content set at all "1’s" (FFh).

For a list of available options (Operating Voltage, Package, etc...) or for further information on any aspect
of this device, please contact the STMicroelectronics Sales Office nearest to you.

14/17
 ST24/25C16, ST24/25W16

PSDIP8 - 8 pin Plastic Skinny DIP, 0.25mm lead frame

mm inches
Symb
Typ Min Max Typ Min Max
A 3.90 5.90 0.154 0.232
A1 0.49 – 0.019 –
A2 3.30 5.30 0.130 0.209
B 0.36 0.56 0.014 0.022
B1 1.15 1.65 0.045 0.065
C 0.20 0.36 0.008 0.014
D 9.20 9.90 0.362 0.390
E 7.62 – – 0.300 – –
E1 6.00 6.70 0.236 0.264
e1 2.54 – – 0.100 – –
eA 7.80 – 0.307 –
eB – 10.00 – 0.394
L 3.00 3.80 0.118 0.150
N 8 8

A2 A

A1 L
B e1 C
B1 eA
D eB

E1 E

1
PSDIP-a

Drawing is not to scale.

15/17
ST24/25C16, ST24/25W16

SO8 - 8 lead Plastic Small Outline, 150 mils body width

mm inches
Symb
Typ Min Max Typ Min Max
A 1.35 1.75 0.053 0.069
A1 0.10 0.25 0.004 0.010
B 0.33 0.51 0.013 0.020
C 0.19 0.25 0.007 0.010
D 4.80 5.00 0.189 0.197
E 3.80 4.00 0.150 0.157
e 1.27 – – 0.050 – –
H 5.80 6.20 0.228 0.244
h 0.25 0.50 0.010 0.020
L 0.40 0.90 0.016 0.035
α 0° 8° 0° 8°
N 8 8
CP 0.10 0.004

h x 45˚

A
C
B
e CP

E H
1

A1 α L

SO-a

Drawing is not to scale.

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 ST24/25C16, ST24/25W16

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