24C32
24C32
DESCRIPTION SDA
YDEC
The Microchip Technology Inc. 24C32 is a 4K x 8 (32K
bit) Serial Electrically Erasable PROM. This device has VCC
been developed for advanced, low power applications SENSE AMP
VSS
such as personal communications or data acquisition. R/W CONTROL
VHYS
SCL
T HD:STA
T SU:STA T SU:STO
SDA
START STOP
tF tR
t HIGH
t LOW
SCL
t SU:STA tHD:DAT t SU:DAT t SU:STO
t HD:STA
SDA t SP
IN
t BUF
tAA
t AA
SDA
OUT
3.1 Bus not Busy (A) A device that acknowledges must pull down the SDA
line during the acknowledge clock pulse in such a way
Both data and clock lines remain HIGH. that the SDA line is stable LOW during the HIGH period
of the acknowledge related clock pulse. Of course,
3.2 Start Data Transfer (B) setup and hold times must be taken into account. Dur-
ing reads, a master must signal an end of data to the
A HIGH to LOW transition of the SDA line while the slave by NOT generating an acknowledge bit on the
clock (SCL) is HIGH determines a START condition. last byte that has been clocked out of the slave. In this
All commands must be preceded by a START condi- case, the slave (24C32) will leave the data line HIGH to
tion. enable the master to generate the STOP condition.
3.3 Stop Data Transfer (C)
A LOW to HIGH transition of the SDA line while the
clock (SCL) is HIGH determines a STOP condition. All
operations must be ended with a STOP condition.
SDA
A A
1 0 1 0 A A A R/W 0 0 0 0 A A A A 7 • • • • • • 0
2 1 0 11 10 9 8
Slave Device
Address Select
Bits
FIGURE 4-4: PAGE WRITE (FOR CACHE WRITE, SEE FIGURE 6-3)
S
T S
BUS A CONTROL WORD WORD T
ACTIVITY: R BYTE ADDRESS (1) ADDRESS (0) DATA n DATA n + 7
O
MASTER T P
SDA LINE 0 0 0 0
A A A A A
BUS C C C C C
ACTIVITY: K K K K K
Send Stop
Random read operations allow the master to access
Condition to any memory location in a random manner. To perform
Initiate Write Cycle this type of read operation, first the word address must
be set. This is done by sending the word address to the
24C32 as part of a write operation (R/W bit set to 0).
Send Start After the word address is sent, the master generates a
start condition following the acknowledge. This termi-
nates the write operation, but not before the internal
address pointer is set. Then the master issues the con-
Send Control Byte trol byte again but with the R/W bit set to a one. The
with R/W = 0
24C32 will then issue an acknowledge and transmit the
eight bit data word. The master will not acknowledge
the transfer but does generate a stop condition which
Did Device No causes the 24C32 to discontinue transmission (see
Acknowledge
(ACK = 0)? Figure 6-2).
Yes
Next
Operation
S
T S
A CONTROL T
BUS ACTIVITY R BYTE DATA n O
MASTER T P
SDA LINE
A N
BUS ACTIVITY C O
K
A
C
K
6.4 Sequential Read The SCL and SDA inputs have filter circuits which sup-
press noise spikes to ensure proper device operation
Sequential reads are initiated in the same way as a ran- even on a noisy bus. All I/O lines incorporate Schmitt
dom read except that after the 24C32 transmits the first triggers for 400 kHz (Fast Mode) compatibility.
data byte, the master issues an acknowledge as
opposed to the stop condition used in a random read.
This acknowledge directs the 24C32 to transmit the
next sequentially addressed 8 bit word. (See Figure 6-
3). Following the final byte transmitted to the master,
the master will NOT generate an acknowledge but will
generate a stop condition.
S S
T T S
A CONTROL WORD WORD A CONTROL T
BYTE ADDRESS (1) ADDRESS (0) R BYTE DATA n
R T O
T P
SDA LINE 0 0 0 0
A A A A N
BUS C C C C O
ACTIVITY: K K K K
A
C
K
S
t
Data n Data n + 1 Data n + 2 Data n + X o
Bus Activity: Control
Master Byte p
SDA Line
Bus Activity A A A A N
C C C C O
K K K K
A
C
K
cache page 0
page 0 page 1 page 2 byte 0 byte 1 • • • byte 7 page 4 • • • page 7 array row n
page 0 page 1 page 2 page 3 page 4 • • • page 7 array row n + 1
1 Write command initiated; 64 bytes of data 2 Last 2 bytes loaded 'roll over'
loaded into cache starting at byte 2 of page 0. to beginning.
Last 2 bytes 3
loaded into
page 0 of cache. cache cache cache cache cache page 1 cache page 2 cache page 7
• • • • • •
byte 0 byte 1 byte 2 byte 7 bytes 8-15 bytes 16-23 bytes 56-63
page 0 page 1 page 2 byte 0 byte 1 byte 2 byte 3 byte 4 • • • byte 7 page 4 • • • page 7 array
row n
page 0 page 1 page 2 page 3 page 4 • • • page 7 array
row
n+1
6 Last 3 pages in cache written to next row in array.
24C32 - /P
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