24AA52/24LCS52

2K 2.2V I2C™ Serial EEPROM with Software Write-Protect

Features Description
• Single supply with operation down to 1.8V The Microchip Technology Inc. 24AA52/24LCS52
• Low-power CMOS technology (24XX52*) is a 2 Kbit Electrically Erasable PROM
- 1 mA active current typical capable of operation across a broad voltage range
(1.8V to 5.5V). This device has a software write-protect
- 1 µA standby current typical (I-temp)
feature for the lower half of the array, as well as an
• Organized as 1 block of 256 bytes (256 x 8) external pin that can be used to write-protect the entire
• Software write protection for lower 128 bytes array. The software write-protect feature is enabled by
• Hardware write protection for entire array sending the device a special command. Once this
• 2-wire serial interface bus, I2C™ compatible feature has been enabled, it cannot be reversed. In
addition to the software protect feature, there is a WP
• Schmitt Trigger inputs for noise suppression
pin that can be used to write-protect the entire array,
• Output slope control to eliminate ground bounce regardless of whether the software write-protect
• 100 kHz (24AA52) and 400 kHz (24LCS52) register has been written or not. This allows the system
compatibility designer to protect none, half or all of the array,
• Self-timed write cycle (including auto-erase) depending on the application. The device is organized
• Page write buffer for up to 16 bytes as one block of 256 x 8-bit memory with a 2-wire serial
• 3.5 ms typical write cycle time for page write interface. Low voltage design permits operation down
to 1.8V, with standby and active currents of only 1 µA
• ESD protection > 4,000V
and 1 mA respectively. The 24XX52 also has a page
• 1,000,000 erase/write cycles write capability for up to 16 bytes of data. The 24XX52
• Data retention > 200 years is available in the standard 8-pin PDIP, surface mount
• 8-lead PDIP, SOIC, TSSOP and MSOP package SOIC, TSSOP and MSOP packages.
• Standard and Pb-free finishes available
• Available for extended temperature ranges: Block Diagram
- Industrial (I): -40°C to +85°C A0 A1 A2 WP
HV Generator

Device Selection Table

I/O Memory Software write
Control protected area
Part VCC Max Clock Temp Control
Logic (00h-7Fh)
Logic XDEC
Number Range Frequency Ranges
24AA52 1.8-5.5 400 kHz(1) I Standard
Array
24LCS52 2.2-5.5 400 kHz I SDA SCL

Note 1: 100 kHz for VCC <2.5V

VCC Write-Protect
Circuitry
VSS
Package Types YDEC

PDIP/SOIC/TSSOP/MSOP Sense Amp.

R/W Control
A0 1 8 VCC
24XX52

A1 2 7 WP
A2 3 6 SCL
VSS 4 5 SDA

*24XX52 is used in this document as a generic part number for the 24AA52/24LCS52 devices.

 2003 Microchip Technology Inc. DS21166G-page 1

24AA52/24LCS52
1.0 ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings(†)

VCC .............................................................................................................................................................................6.5V
All inputs and outputs w.r.t. VSS ......................................................................................................... -0.3V to VCC +1.0V
Storage temperature ...............................................................................................................................-65°C to +150°C
Ambient temperature with power applied ................................................................................................-40°C to +125°C
ESD protection on all pins ......................................................................................................................................................≥ 4 kV

† NOTICE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the
device. These are stress ratings only and functional operation of the device at these or any other conditions above
those indicated in the operation sections of the specifications is not implied. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.

TABLE 1-1: DC SPECIFICATIONS

VCC = +1.8V to +5.5V
DC CHARACTERISTICS
Industrial (I): TA = -40°C to +85°C
Param.
Symbol Characteristic Min Typ Max Units Conditions
No.
D1 VIH A0, A1, A2, SCL, SDA — — — — —
and WP pins
D2 — High-level input voltage 0.7 VCC — — V —
D3 VIL Low-level input voltage — — 0.3 VCC V 0.2 VCC for VCC < 2.5V
D4 VHYS Hysteresis of Schmitt 0.05 VCC — — V (Note)
Trigger inputs
D5 VOL Low-level output voltage — — 0.40 V IOL = 3.0 mA, VCC = 2.5V
D6 ILI Input leakage current — — ±1 mA VIN = 0.1V to VCC
D7 ILO Output leakage current — — ±1 µA VOUT = 0.1V to VCC
D8 CIN, Pin capacitance — — 10 pF VCC = 5.0V (Note)
COUT (all inputs/outputs) TA = 25°C, FCLK = 1 MHz
D9 ICC write Operating current — 1.0 3.0 mA VCC = 5.5V, SCL = 400 kHz
D10 ICC read — 0.20 1.0 mA —
D11 ICCS Standby current — 0.36 1.0 µA Industrial
— — — SDA = SCL = VCC
A0, A1, A2, WP = VSS
Note: This parameter is periodically sampled and not 100% tested.

DS21166G-page 2  2003 Microchip Technology Inc.

 24AA52/24LCS52

TABLE 1-2: AC SPECIFICATIONS

VCC = +1.8V to +5.5V
AC CHARACTERISTICS
Industrial (I): TA = -40°C to +85°C
Param.
Symbol Characteristic Min Typ Max Units Conditions
No.
1 FCLK Clock frequency — — 400 kHz 2.5V ≤ VCC ≤ 5.5V
— — 100 1.8V ≤ VCC < 2.5V (24AA52)
2 THIGH Clock high time 600 — — ns 2.5V ≤ VCC ≤ 5.5V
4000 — — 1.8V ≤ VCC < 2.5V (24AA52)
3 TLOW Clock low time 1300 — — ns 2.5V ≤ VCC ≤ 5.5V
4700 — — 1.8V ≤ VCC < 2.5V (24AA52)
4 TR SDA and SCL rise time — — 300 ns 2.5V ≤ VCC ≤ 5.5V
(Note 1) — — 1000 1.8V ≤ VCC < 2.5V (24AA52)
5 TF SDA and SCL fall time — — 300 ns (Note 1)
—
6 THD:STA Start condition hold time 600 — — ns 2.5V ≤ VCC ≤ 5.5V
4000 — — 1.8V ≤ VCC < 2.5V (24AA52)
7 TSU:STA Start condition setup 600 — — ns 2.5V ≤ VCC ≤ 5.5V
time 4700 — — 1.8V ≤ VCC < 2.5V (24AA52)
8 THD:DAT Data input hold time 0 — — ns (Note 2)
—
9 TSU:DAT Data input setup time 100 — — ns 2.5V ≤ VCC ≤ 5.5V
250 — — 1.8V ≤ VCC < 2.5V (24AA52)
10 TSU:STO Stop condition setup 600 — — ns 2.5V ≤ VCC ≤ 5.5V
time 4000 — — 1.8V ≤ VCC < 2.5V (24AA52)
11 TAA Output valid from clock — — 900 ns 2.5V ≤ VCC ≤ 5.5V
(Note 2) — — 3500 1.8V ≤ VCC < 2.5V (24AA52)
12 TBUF Bus free time: Time the 1300 — — ns 2.5V ≤ VCC ≤ 5.5V
bus must be free before 4700 — — 1.8V ≤ VCC < 2.5V (24AA52)
a new transmission can
start
13 TOF Output fall time from VIH 20+0.1CB — 250 ns 2.5V ≤ VCC ≤ 5.5V
minimum to VIL — — 250 1.8V ≤ VCC < 2.5V (24AA52)
maximum
14 TSP Input filter spike — — 50 ns (Note 1 and Note 3)
suppression
(SDA and SCL pins)
15 TWC Write cycle time — — 5 ms —
(byte or page)
16 — Endurance 1M — — cycles 25°C, VCC = 5.0V, Block
mode (Note 4)
Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
3: The combined TSP and VHYS specifications are due to new Schmitt Trigger inputs, which provide improved
noise spike suppression. This eliminates the need for a TI specification for standard operation.
4: This parameter is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance™ Model which can be obtained from Microchip’s web site:
www.microchip.com.

 2003 Microchip Technology Inc. DS21166G-page 3

24AA52/24LCS52
FIGURE 1-1: BUS TIMING DATA

5 4
2
3
SCL
7
8 9 10
6
SDA
IN 14

11 12

SDA
OUT

FIGURE 1-2: BUS TIMING START/STOP

D4

SCL
6
7 10
SDA

START STOP

DS21166G-page 4  2003 Microchip Technology Inc.

 24AA52/24LCS52
2.0 FUNCTIONAL DESCRIPTION 3.4 Data Valid (D)
The 24XX52 supports a bidirectional 2-wire bus and The state of the data line represents valid data when,
data transmission protocol. A device that sends data after a Start condition, the data line is stable for the
onto the bus is defined as a transmitter and a device duration of the high period of the clock signal.
receiving data as a receiver. The bus has to be The data on the line must be changed during the low
controlled by a master device, which generates the period of the clock signal. There is one clock pulse per
serial clock (SCL), controls the bus access and gener- bit of data.
ates the Start and Stop conditions, while the 24XX52
works as slave. Both master and slave can operate as Each data transfer is initiated with a Start condition and
transmitter or receiver, but the master device terminated with a Stop condition. The number of data
determines which mode is activated. bytes transferred between the Start and Stop
conditions is determined by the master device and is,
theoretically, unlimited; although only the last sixteen
3.0 BUS CHARACTERISTICS will be stored when doing a write operation. When an
overwrite does occur, it will replace data in a first-in,
The following bus protocol has been defined:
first-out (FIFO) fashion.
• Data transfer may be initiated only when the bus
is not busy. 3.5 Acknowledge
• During data transfer, the data line must remain
Each receiving device, when addressed, is obliged to
stable whenever the clock line is high. Changes in
generate an acknowledge after the reception of each
the data line while the clock line is high will be
byte. The master device must generate an extra clock
interpreted as a Start or Stop condition.
pulse, which is associated with this Acknowledge bit.
Accordingly, the following bus conditions have been
defined (Figure 3-1). Note: The 24XX52 does not generate any
Acknowledge bits if an internal
3.1 Bus Not Busy (A) programming cycle is in progress.
The device that acknowledges has to pull down the
Both data and clock lines remain high.
SDA line during the Acknowledge clock pulse in such a
3.2 Start Data Transfer (B) way that the SDA line is stable low during the high
period of the acknowledge related clock pulse. Of
A high-to-low transition of the SDA line while the clock course, setup and hold times must be taken into
(SCL) is high determines a Start condition. All account. During reads, a master must signal an end of
commands must be preceded by a Start condition. data to the slave by not generating an Acknowledge bit
on the last byte that has been clocked out of the slave.
3.3 Stop Data Transfer (C) In this case, the slave (24XX52) will leave the data line
high to enable the master to generate the Stop
A low-to-high transition of the SDA line while the clock
condition.
(SCL) is high determines a Stop condition. All
operations must be ended with a Stop condition.

FIGURE 3-1: DATA TRANSFER SEQUENCE ON THE SERIAL BUS

(A) (B) (D) (D) (C) (A)

SCL

SDA

START ADDRESS OR DATA STOP

CONDITION ACKNOWLEDGE ALLOWED CONDITION
VALID TO CHANGE

 2003 Microchip Technology Inc. DS21166G-page 5

24AA52/24LCS52
3.6 Device Addressing After receiving another Acknowledge signal from the
24XX52, the master device will transmit the data word
A control byte is the first byte received following the to be written into the addressed memory location. The
Start condition from the master device. The first part of 24XX52 acknowledges again and the master generates
the control byte consists of a 4-bit control code which is a Stop condition. This initiates the internal write cycle,
set to ‘1010’ for normal read and write operations and which means that, during this time, the 24XX52 will not
‘0110’ for writing to the write-protect register. The generate Acknowledge signals (Figure 4-1). If an
control byte is followed by three Chip Select bits (A2, attempt is made to write to the array when the software
A1, A0). The Chip Select bits allow the use of up to or hardware write protection has been enabled, the
eight 24XX52 devices on the same bus and are used to device will acknowledge the command but no data will
determine which device is accessed. The Chip Select be written. The write cycle time must be observed even
bits in the control byte must correspond to the logic if the write protection is enabled.
levels on the corresponding A2, A1 and A0 pins for the
device to respond. The device will not acknowledge if 4.2 Page Write
you attempt a Read command with the control code set
to ‘0110’. The write control byte, word address and the first data
byte are transmitted to the 24XX52 in the same way as
The eighth bit of slave address determines if the master
in a byte write. Instead of generating a Stop condition,
device wants to read or write to the 24XX52
the master transmits up to 15 additional data bytes to
(Figure 3-2). When set to a one, a read operation is
the 24XX52, which are temporarily stored in the on-
selected. When set to a zero, a write operation is
chip page buffer and will be written into the memory
selected.
after the master has transmitted a Stop condition. Upon
receipt of each word, the four lower order address
Control Chip pointer bits are internally incremented by one. The
Operation R/W
Code Select higher order four bits of the word address remain
Read 1010 A2 A1 A0 1 constant. If the master should transmit more than 16
Write 1010 A2 A1 A0 0 bytes prior to generating the Stop condition, the
address counter will roll over and the previously
Set Write-Protect received data will be overwritten. As with the byte write
0110 A2 A1 A0 0
Register operation, once the Stop condition is received, an
internal write cycle will begin (Figure 4-2). If an attempt
FIGURE 3-2: CONTROL BYTE is made to write to the array when the hardware write
ALLOCATION protection has been enabled, the device will acknowl-
edge the command but no data will be written. The
START READ/WRITE
write cycle time must be observed even if the write pro-
tection is enabled.
SLAVE ADDRESS R/W A
Note: Page write operations are limited to writing
bytes within a single physical page, regard-
less of the number of bytes actually being
1 0 1 0 A2 A1 A0 written. Physical page boundaries start at
addresses that are integer multiples of the
OR page buffer size (or ‘page size’) and end at
0 1 1 0 A2 A1 A0
addresses that are integer multiples of
[page size - 1]. If a Page Write command
attempts to write across a physical page
boundary, the result is that the data wraps
4.0 WRITE OPERATIONS around to the beginning of the current page
(overwriting data previously stored there),
4.1 Byte Write instead of being written to the next page,
as might be expected. It is therefore neces-
Following the Start signal from the master, the device sary for the application software to prevent
code(4 bits), the Chip Select bits (3 bits) and the R/W page write operations that would attempt to
bit, which is a logic low, are placed onto the bus by the cross a page boundary.
master transmitter. This indicates to the addressed
slave receiver that a byte with a word address will follow
once it has generated an Acknowledge bit during the
ninth clock cycle. Therefore, the next byte transmitted
by the master is the word address and will be written
into the address pointer of the 24XX52.

DS21166G-page 6  2003 Microchip Technology Inc.

 24AA52/24LCS52
FIGURE 4-1: BYTE WRITE
S S
BUS ACTIVITY T CONTROL WORD T
MASTER A BYTE ADDRESS O
R DATA
T P

SDA LINE S P

A A A
BUS ACTIVITY C C C
K K K

FIGURE 4-2: PAGE WRITE

S S
BUS ACTIVITY T CONTROL WORD T
A O
MASTER R BYTE ADDRESS (n) DATA (n) DATA (n + 1) DATA (n + 15)
P
T
SDA LINE S P
A A A A A
BUS ACTIVITY C C C C C
K K K K K

 2003 Microchip Technology Inc. DS21166G-page 7

24AA52/24LCS52
5.0 ACKNOWLEDGE POLLING
Since the device will not acknowledge during a write
cycle, this can be used to determine when the cycle is 6.0 WRITE PROTECTION
complete (this feature can be used to maximize bus The 24XX52 has a software write-protect feature that
throughput). Once the Stop condition for a Write allows the lower half of the array (addresses 00h - 7Fh)
command has been issued from the master, the device to be permanently write-protected, as well as a WP pin
initiates the internally timed write cycle. ACK polling that can be used to protect the entire array.
can be initiated immediately. This involves the master
sending a Start condition followed by the control byte 6.1 Software Write-Protect
for a Write command (R/W = 0). If the device is still
busy with the write cycle, then no ACK will be returned. The software write-protect feature is invoked by writing
If the cycle is complete, then the device will return the to the write-protect register. This is done by sending a
ACK and the master can then proceed with the next command similar to a normal Write command. As
Read or Write command. See Figure 5-1 for flow shown in Figure 6-1, the write-protect register is written
diagram. by sending a Write command with the slave address
set to ‘0110’ instead of ‘1010’ and the address bits and
FIGURE 5-1: ACKNOWLEDGE data bits are don’t cares. Once the software write-pro-
tect register has been written, the device will not
POLLING FLOW
acknowledge the ‘0110’ control byte.

Send
Write Command Note: Once the software write-protect register
has been written, the write protection is
enabled and cannot be reversed, even if
Send Stop the device is powered down.
Condition to
Initiate Write Cycle 6.2 Hardware Write-Protect
The WP pin can be tied to VCC, VSS or can be left float-
ing. If tied to VCC, the entire array will be write-protected,
Send Start regardless of whether the software write-protect register
has been written or not. If the WP pin is set to VCC, it will
prevent the software write-protect register from being
written. If the WP is tied to VSS or left floating, then write
Send Control Byte protection is determined by the status of the software
with R/W = 0 write-protect register.

Did Device
No
Acknowledge
(ACK = 0)?

Yes

Next
Operation

FIGURE 6-1: SETTING WRITE-PROTECT REGISTER

S
BUS ACTIVITY T CONTROL WORD S
MASTER A BYTE ADDRESS DATA T
R O
T P

SDA LINE S P

A A A
BUS ACTIVITY C C C
K K K

DS21166G-page 8  2003 Microchip Technology Inc.

 24AA52/24LCS52
7.0 READ OPERATION 7.3 Sequential Read
Read operations are initiated in the same way as write Sequential reads are initiated in the same way as a
operations, with the exception that the R/W bit of the random read, with the exception that after the 24XX52
slave address is set to ‘1’. There are three basic types transmits the first data byte, the master issues an
of read operations: current address read, random read acknowledge, as opposed to a Stop condition in a
and sequential read. random read. This directs the 24XX52 to transmit the
next sequentially addressed 8-bit word (Figure 7-3).
7.1 Current Address Read To provide sequential reads, the 24XX52 contains an
The 24XX52 contains an address counter that internal address pointer, which is incremented by one
maintains the address of the last word accessed, inter- at the completion of each operation. This address
nally incremented by ‘1’. Therefore, if the previous pointer allows the entire memory contents to be serially
access (either a read or write operation) was to read during one operation.
address n, the next current address read operation
would access data from address n+1. Upon receipt of 7.4 Contiguous Addressing Across
the slave address with R/W bit set to ‘1’, the 24XX52 Multiple Devices
issues an acknowledge and transmits the 8-bit data
The Chip Select bits (A2, A1, A0) can be used to
word. The master will not acknowledge the transfer but
expand the contiguous address space for up to 16K bits
does generate a Stop condition and the 24XX52
by adding up to eight 24XX52 devices on the same
discontinues transmission (Figure 7-1).
bus. In this case, software can use A0 of the control
byte as address bit A8, A1 as address bit A9 and A2 as
7.2 Random Read
address bit A10. It is not possible to sequentially read
Random read operations allow the master to access across device boundaries.
any memory location in a random manner. To perform
this type of read operation, the word address must first 7.5 Noise Protection and Brown Out
be set. This is done by sending the word address to the
The 24XX52 employs a VCC threshold detector circuit
24XX52 as part of a write operation. Once the word
which disables the internal erase/write logic if the VCC
address is sent, the master generates a Start condition
is below 1.5V at nominal conditions.
following the acknowledge. This terminates the write
operation, but not before the internal address pointer is The SCL and SDA inputs have Schmitt Trigger and
set. The master then issues the control byte again, but filter circuits which suppress noise spikes to assure
with the R/W bit set to a ‘1’. The 24XX52 then issues proper device operation even on a noisy bus.
an acknowledge and transmits the 8-bit data word. The
master will not acknowledge the transfer but does
generate a Stop condition and the 24XX52
discontinues transmission (Figure 7-2).

FIGURE 7-1: CURRENT ADDRESS READ

S
BUS ACTIVITY T CONTROL S
MASTER A BYTE T
R DATA (n)
O
T P

SDA LINE S P

A N
BUS ACTIVITY C O
K
A
C
K

 2003 Microchip Technology Inc. DS21166G-page 9

24AA52/24LCS52
FIGURE 7-2: RANDOM READ

S S
BUS ACTIVITY T CONTROL WORD T CONTROL S
MASTER A BYTE ADDRESS (n) A BYTE T
R R DATA (n) O
T T P
S S P
SDA LINE
A A A N
C C C O
K K K
BUS ACTIVITY A
C
K

FIGURE 7-3: SEQUENTIAL READ

BUS ACTIVITY CONTROL S

T
MASTER BYTE DATA (n) DATA (n + 1) DATA (n + 2) DATA (n + X) O
P

SDA LINE P
A A A A N
BUS ACTIVITY C C C C O
K K K K
A
C
K

DS21166G-page 10  2003 Microchip Technology Inc.

 24AA52/24LCS52
8.0 PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 8-1.

TABLE 8-1: PIN FUNCTION TABLE

Symbol PDIP SOIC TSSOP MSOP Description

A0 1 1 1 1 Chip Address Input
A1 2 2 2 2 Chip Address Input
A2 3 3 3 3 Chip Address Input
VSS 4 4 4 4 Ground
SDA 5 5 5 5 Serial Address/Data I/O
SCL 6 6 6 6 Serial Clock
WP 7 7 7 7 Write-Protect Input
VCC 8 8 8 8 +1.8V to 5.5V Power Supply

8.1 A0, A1, A2 8.3 Serial Clock (SCL)

The levels on these inputs are compared with the This input is used to synchronize the data transfer to
corresponding bits in the slave address. The chip is and from the device.
selected if the compare is true.
Up to eight 24XX52 devices may be connected to the
8.4 Write-Protect (WP)
same bus by using different Chip Select bit This is the hardware write-protect pin. It can be tied to
combinations. These inputs must be connected to VCC, VSS or be left floating. If tied to VCC, the hardware
either VSS or VCC. write protection is enabled. If the WP pin is tied to VSS,
the hardware write protection is disabled. If the WP pin
8.2 Serial Address/Data Input/Output is left floating, an internal pull down logic will pull the
(SDA) WP pin to VSS and the hardware write protection will be
disabled.
This is a bidirectional pin used to transfer addresses
and data into and data out of the device. It is an open
drain terminal. Therefore, the SDA bus requires a pull-
up resistor to VCC (typical 10 kΩ for 100 kHz, 2 kΩ for
400 kHz).
For normal data transfer, SDA, is allowed to change
only during SCL low. Changes during SCL high are
reserved for indicating the Start and Stop conditions.

 2003 Microchip Technology Inc. DS21166G-page 11

24AA52/24LCS52
9.0 PACKAGING INFORMATION
9.1 Package Marking Information

8-Lead PDIP (300 mil) Example:

XXXXXXXX 24AA52
XXXXXNNN I/PNNN
YYWW YYWW

8-Lead SOIC (150 mil) Example:

XXXXXXXX 24LCS52
XXXXYYWW I/SNYYWW
NNN NNN

8-Lead TSSOP Example:

XXXX S52
XYWW IYWW
NNN NNN

8-Lead MSOP Example:

XXXXXX 4S52I
YWWNNN YWWNNN

Legend: XX...X Customer specific information*

YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code

Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line thus limiting the number of available characters
for customer specific information.

*Standard OTP marking consists of Microchip part number, year code, week code and traceability code.

DS21166G-page 12  2003 Microchip Technology Inc.

 24AA52/24LCS52
8-Lead Plastic Dual In-line (P) – 300 mil (PDIP)

E1

n 1

A A2

L
c
A1

β B1
p
eB B

Units INCHES* MILLIMETERS

Dimension Limits MIN NOM MAX MIN NOM MAX
Number of Pins n 8 8
Pitch p .100 2.54
Top to Seating Plane A .140 .155 .170 3.56 3.94 4.32
Molded Package Thickness A2 .115 .130 .145 2.92 3.30 3.68
Base to Seating Plane A1 .015 0.38
Shoulder to Shoulder Width E .300 .313 .325 7.62 7.94 8.26
Molded Package Width E1 .240 .250 .260 6.10 6.35 6.60
Overall Length D .360 .373 .385 9.14 9.46 9.78
Tip to Seating Plane L .125 .130 .135 3.18 3.30 3.43
Lead Thickness c .008 .012 .015 0.20 0.29 0.38
Upper Lead Width B1 .045 .058 .070 1.14 1.46 1.78
Lower Lead Width B .014 .018 .022 0.36 0.46 0.56
Overall Row Spacing § eB .310 .370 .430 7.87 9.40 10.92
Mold Draft Angle Top α 5 10 15 5 10 15
Mold Draft Angle Bottom β 5 10 15 5 10 15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-001
Drawing No. C04-018

 2003 Microchip Technology Inc. DS21166G-page 13

24AA52/24LCS52
8-Lead Plastic Small Outline (SN) – Narrow, 150 mil (SOIC)

E1

D
2

B n 1

h α
45°

c
A A2

φ
β L A1

Units INCHES* MILLIMETERS

Dimension Limits MIN NOM MAX MIN NOM MAX
Number of Pins n 8 8
Pitch p .050 1.27
Overall Height A .053 .061 .069 1.35 1.55 1.75
Molded Package Thickness A2 .052 .056 .061 1.32 1.42 1.55
Standoff § A1 .004 .007 .010 0.10 0.18 0.25
Overall Width E .228 .237 .244 5.79 6.02 6.20
Molded Package Width E1 .146 .154 .157 3.71 3.91 3.99
Overall Length D .189 .193 .197 4.80 4.90 5.00
Chamfer Distance h .010 .015 .020 0.25 0.38 0.51
Foot Length L .019 .025 .030 0.48 0.62 0.76
Foot Angle φ 0 4 8 0 4 8
Lead Thickness c .008 .009 .010 0.20 0.23 0.25
Lead Width B .013 .017 .020 0.33 0.42 0.51
Mold Draft Angle Top α 0 12 15 0 12 15
Mold Draft Angle Bottom β 0 12 15 0 12 15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-012
Drawing No. C04-057

DS21166G-page 14  2003 Microchip Technology Inc.

 24AA52/24LCS52
8-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm (TSSOP)

E1

D
2

1
n
B

α
A

φ A1 A2

β
L

Units INCHES MILLIMETERS*

Dimension Limits MIN NOM MAX MIN NOM MAX
Number of Pins n 8 8
Pitch p .026 0.65
Overall Height A .043 1.10
Molded Package Thickness A2 .033 .035 .037 0.85 0.90 0.95
Standoff § A1 .002 .004 .006 0.05 0.10 0.15
Overall Width E .246 .251 .256 6.25 6.38 6.50
Molded Package Width E1 .169 .173 .177 4.30 4.40 4.50
Molded Package Length D .114 .118 .122 2.90 3.00 3.10
Foot Length L .020 .024 .028 0.50 0.60 0.70
Foot Angle φ 0 4 8 0 4 8
Lead Thickness c .004 .006 .008 0.09 0.15 0.20
Lead Width B .007 .010 .012 0.19 0.25 0.30
Mold Draft Angle Top α 0 5 10 0 5 10
Mold Draft Angle Bottom β 0 5 10 0 5 10
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.005” (0.127mm) per side.
JEDEC Equivalent: MO-153
Drawing No. C04-086

 2003 Microchip Technology Inc. DS21166G-page 15

24AA52/24LCS52
8-Lead Plastic Micro Small Outline Package (MS) (MSOP)

E1

D
2
B
n 1

A A2
c
φ
A1

(F) L
β

Units INCHES MILLIMETERS*

Dimension Limits MIN NOM MAX MIN NOM MAX
Number of Pins n 8 8
Pitch p .026 BSC 0.65 BSC
Overall Height A - - .043 - - 1.10
Molded Package Thickness A2 .030 .033 .037 0.75 0.85 0.95
Standoff A1 .000 - .006 0.00 - 0.15
Overall Width E .193 TYP. 4.90 BSC
Molded Package Width E1 .118 BSC 3.00 BSC
Overall Length D .118 BSC 3.00 BSC
Foot Length L .016 .024 .031 0.40 0.60 0.80
Footprint (Reference) F .037 REF 0.95 REF
Foot Angle φ 0° - 8° 0° - 8°
Lead Thickness c .003 .006 .009 0.08 - 0.23
Lead Width B .009 .012 .016 0.22 - 0.40
Mold Draft Angle Top α 5° - 15° 5° - 15°
Mold Draft Angle Bottom β 5° - 15° 5° - 15°
*Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not
exceed .010" (0.254mm) per side.
JEDEC Equivalent: MO-187
Drawing No. C04-111

DS21166G-page 16  2003 Microchip Technology Inc.

 24AA52/24LCS52
APPENDIX A: REVISION HISTORY
Revision G
Added 2.2V to document; Revised Features section to
include Standard and Pb-free finishes.
Corrections to Section 1.0, Electrical Characteristics;
Product ID System, added lead finish info.

 2003 Microchip Technology Inc. DS21166G-page 17

24AA52/24LCS52
NOTES:

DS21166G-page 18  2003 Microchip Technology Inc.

 24AA52/24LCS52
ON-LINE SUPPORT SYSTEMS INFORMATION AND
Microchip provides on-line support on the Microchip UPGRADE HOT LINE
World Wide Web site. The Systems Information and Upgrade Line provides
The web site is used by Microchip as a means to make system users a listing of the latest versions of all of
files and information easily available to customers. To Microchip's development systems software products.
view the site, the user must have access to the Internet Plus, this line provides information on how customers
and a web browser, such as Netscape® or Microsoft® can receive the most current upgrade kits. The Hot Line
Internet Explorer. Files are also available for FTP Numbers are:
download from our FTP site. 1-800-755-2345 for U.S. and most of Canada, and
1-480-792-7302 for the rest of the world.
Connecting to the Microchip Internet
Web Site 042003
The Microchip web site is available at the following
URL:
www.microchip.com
The file transfer site is available by using an FTP
service to connect to:
ftp://ftp.microchip.com
The web site and file transfer site provide a variety of
services. Users may download files for the latest
Development Tools, Data Sheets, Application Notes,
User's Guides, Articles and Sample Programs. A vari-
ety of Microchip specific business information is also
available, including listings of Microchip sales offices,
distributors and factory representatives. Other data
available for consideration is:
• Latest Microchip Press Releases
• Technical Support Section with Frequently Asked
Questions
• Design Tips
• Device Errata
• Job Postings
• Microchip Consultant Program Member Listing
• Links to other useful web sites related to
Microchip Products
• Conferences for products, Development Systems,
technical information and more
• Listing of seminars and events

 2003 Microchip Technology Inc. DS21166G-page 19

24AA52/24LCS52
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod-
uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation
can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150.
Please list the following information, and use this outline to provide us with your comments about this document.

To: Technical Publications Manager Total Pages Sent ________

RE: Reader Response

From: Name
Company
Address
City / State / ZIP / Country
Telephone: (_______) _________ - _________ FAX: (______) _________ - _________
Application (optional):
Would you like a reply? Y N

Device: 24AA52/24LCS52 Literature Number: DS21166G

Questions:

1. What are the best features of this document?

2. How does this document meet your hardware and software development needs?

3. Do you find the organization of this document easy to follow? If not, why?

4. What additions to the document do you think would enhance the structure and subject?

5. What deletions from the document could be made without affecting the overall usefulness?

6. Is there any incorrect or misleading information (what and where)?

7. How would you improve this document?

DS21166G-page 20  2003 Microchip Technology Inc.

 24AA52/24LCS52
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO. X /XX X
Examples:
Device Temperature Package Lead Finish a) 24AA52-I/P: Industrial Temperature,
Range 1.8V, PDIP package
b) 24AA52-I/SN: Industrial Temperature,
Device: 24AA52: = 1.8V, 2 Kbit I2C Serial EEPROM 1.8V, SOIC package
24AA52T: = 1.8V, 2 Kbit I2C Serial EEPROM c) 24AA52T-I/MS: Tape and Reel, Industrial
(Tape and Reel) Temperature, 1.8V, MSOP package
24LCS52: = 2.2V, 2 Kbit I2C Serial EEPROM d) 24AA52-I/SNG: Industrial Temperature,
24LCS52T: = 2.2V, 2 Kbit I2C Serial EEPROM 1.8V, SOIC package, Pb-free
(Tape and Reel) e) 24LCS52-I/P: Industrial Temperature,
2.2V, PDIP package
Temperature I = -40°C to +85°C f) 24LCS52-I/SN: Industrial Temperature,
Range: 2.2V, SOIC package
g) 24LCS52T-I/MS: Tape and Reel,
Industrial Temperature, 2.2V, MSOP
Package: P = Plastic DIP (300 mil body), 8-lead package
SN = Plastic SOIC (150 mil body), 8-lead
h) 24LCS52-I/SNG: Industrial Temperature,
ST = Plastic TSSOP (4.4 mm), 8-lead 2.2V, SOIC package, Pb-free
MS = Plastic Micro Small Outline (MSOP), 8-lead
Lead Finish Blank = Standard 63%/37% Sn/Pb
G = Pb-free (Matte Tin - Pure Sn)

Sales and Support

Data Sheets
Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recom-
mended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:

1. Your local Microchip sales office

2. The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277
3. The Microchip Worldwide Site (www.microchip.com)

Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.

New Customer Notification System

Register on our web site (www.microchip.com/cn) to receive the most current information on our products.

 2003 Microchip Technology Inc. DS21166G-page21

24AA52/24LCS52
NOTES:

DS21166G-page 22  2003 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device Trademarks

applications and the like is intended through suggestion only
The Microchip name and logo, the Microchip logo, Accuron,
and may be superseded by updates. It is your responsibility to
dsPIC, KEELOQ, MPLAB, PIC, PICmicro, PICSTART,
ensure that your application meets with your specifications.
PRO MATE and PowerSmart are registered trademarks of
No representation or warranty is given and no liability is
Microchip Technology Incorporated in the U.S.A. and other
assumed by Microchip Technology Incorporated with respect
countries.
to the accuracy or use of such information, or infringement of
patents or other intellectual property rights arising from such AmpLab, FilterLab, microID, MXDEV, MXLAB, PICMASTER,
use or otherwise. Use of Microchip’s products as critical com- SEEVAL and The Embedded Control Solutions Company are
ponents in life support systems is not authorized except with registered trademarks of Microchip Technology Incorporated
express written approval by Microchip. No licenses are con- in the U.S.A.
veyed, implicitly or otherwise, under any intellectual property Application Maestro, dsPICDEM, dsPICDEM.net, ECAN,
rights. ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,
In-Circuit Serial Programming, ICSP, ICEPIC, microPort,
Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM,
PICkit, PICDEM, PICDEM.net, PowerCal, PowerInfo,
PowerMate, PowerTool, rfLAB, rfPIC, Select Mode,
SmartSensor, SmartShunt, SmartTel and Total Endurance are
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
Serialized Quick Turn Programming (SQTP) is a service mark
of Microchip Technology Incorporated in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2003, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.

Microchip received QS-9000 quality system

certification for its worldwide headquarters,
design and wafer fabrication facilities in
Chandler and Tempe, Arizona in July 1999
and Mountain View, California in March 2002.
The Company’s quality system processes and
procedures are QS-9000 compliant for its
PICmicro® 8-bit MCUs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals,
non-volatile memory and analog products. In
addition, Microchip’s quality system for the
design and manufacture of development
systems is ISO 9001 certified.

 2003 Microchip Technology Inc. DS21166G-page 23

 WORLDWIDE SALES AND SERVICE
AMERICAS ASIA/PACIFIC Korea
168-1, Youngbo Bldg. 3 Floor
Corporate Office Australia
Samsung-Dong, Kangnam-Ku
2355 West Chandler Blvd. Suite 22, 41 Rawson Street
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Chandler, AZ 85224-6199 Epping 2121, NSW
Tel: 82-2-554-7200 Fax: 82-2-558-5932 or
Tel: 480-792-7200 Australia
82-2-558-5934
Fax: 480-792-7277 Tel: 61-2-9868-6733
Technical Support: 480-792-7627 Fax: 61-2-9868-6755 Singapore
Web Address: http://www.microchip.com 200 Middle Road
China - Beijing
#07-02 Prime Centre
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Westford, MA 01886 Rm. 2401-2402, 24th Floor, Tel: 886-7-536-4818
Tel: 978-692-3848 Ming Xing Financial Tower Fax: 886-7-536-4803
Fax: 978-692-3821 No. 88 TIDU Street
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Chicago Tel: 86-28-86766200 Taiwan Branch
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32255 Northwestern Highway, Suite 190 Tel: 852-2401-1200 Denmark
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2355 West Chandler Blvd. Room 401, Hongjian Building Fax: 49-89-627-144-44
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Tel: 480-792-7966 Shunde City, Guangdong 528303, China Via Quasimodo, 12
Fax: 480-792-4338 Tel: 86-765-8395507 Fax: 86-765-8395571 20025 Legnano (MI)
San Jose China - Qingdao Milan, Italy
2107 North First Street, Suite 590 Rm. B505A, Fullhope Plaza, Tel: 39-0331-742611
San Jose, CA 95131 No. 12 Hong Kong Central Rd. Fax: 39-0331-466781
Tel: 408-436-7950 Qingdao 266071, China Netherlands
Fax: 408-436-7955 Tel: 86-532-5027355 Fax: 86-532-5027205 P. A. De Biesbosch 14
Toronto India NL-5152 SC Drunen, Netherlands
6285 Northam Drive, Suite 108 Divyasree Chambers Tel: 31-416-690399
Mississauga, Ontario L4V 1X5, Canada 1 Floor, Wing A (A3/A4) Fax: 31-416-690340
Tel: 905-673-0699 No. 11, O’Shaugnessey Road United Kingdom
Fax: 905-673-6509 Bangalore, 560 025, India 505 Eskdale Road
Tel: 91-80-2290061 Fax: 91-80-2290062 Winnersh Triangle
Japan Wokingham
Benex S-1 6F Berkshire, England RG41 5TU
3-18-20, Shinyokohama Tel: 44-118-921-5869
Kohoku-Ku, Yokohama-shi Fax: 44-118-921-5820
Kanagawa, 222-0033, Japan
Tel: 81-45-471- 6166 Fax: 81-45-471-6122 07/28/03

DS21166G-page 24  2003 Microchip Technology Inc.